URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [sim/] [bin/] [Makefile] - Blame information for rev 36

Go to most recent revision | Details | Compare with Previous | View Log


 
CUR_DIR=$(shell pwd)
PROJECT_ROOT=$(CUR_DIR)/../..
 
# Define these tests if none were on the command line
TESTS ?= basic-nocache cbasic-nocache-O2 dhry-nocache-O2 except-nocache mmu-nocache mul-nocache-O2 syscall-nocache tick-nocache uart-nocache basic-icdc cbasic-icdc-O2 dhry-icdc-O2 except-icdc mmu-icdc mul-icdc-O2 syscall-icdc tick-icdc uart-icdc
#TESTS = basic-nocache cbasic-nocache-O2
 
SIM_DIR=$(PROJECT_ROOT)/sim
SIM_RUN_DIR=$(SIM_DIR)/run
SIM_BIN_DIR=$(SIM_DIR)/bin
SIM_RESULTS_DIR=$(SIM_DIR)/results
 
BENCH_DIR=$(PROJECT_ROOT)/bench
BACKEND_DIR=$(PROJECT_ROOT)/backend
BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
 
RTL_VERILOG_DIR=$(PROJECT_ROOT)/rtl/verilog
 
 
SW_DIR=$(PROJECT_ROOT)/sw
 
ICARUS=iverilog
ICARUS_VVP=vvp
ICARUS_COMMAND_FILE=icarus.scr
SIM_MEM_FILE="flash.in"
SIM_SUCCESS_MESSAGE=deaddead
 
.PHONY: prepare_rtl
prepare_rtl:
        @cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
 
.PHONY: prepare_sw
prepare_sw:
        @$(MAKE) -C $(SW_DIR)/support
        @$(MAKE) -C $(SW_DIR)/utils
 
tests: prepare_sw prepare_rtl
        @if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
        @echo
        @echo "Beginning loop that will complete the following tests: $(TESTS)"
        @echo
        @for TEST in $(TESTS); do \
                echo "################################################################################"; \
                echo; \
                echo "\t#### Current test: $$TEST ####"; echo; \
                echo "\t#### Compiling software ####"; echo; \
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
                rm -f $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST.hex $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
                sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
                        -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
                        -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
                        -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
                        -e \\!^//.*\$$!d -e \\!^\$$!d ; \
                echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                if [ ! -z $$VCD ]; \
                        then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                fi; \
                echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
                echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
                echo ; \
                echo "\t#### Compiling RTL ####"; \
                rm -f $(SIM_RUN_DIR)/a.out; \
                $(ICARUS) -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(RTL_SIM_FLAGS); \
                echo; \
                echo "\t#### Beginning simulation ####"; \
                time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \
                if [ $$? -gt 0 ]; then exit $$?; fi; \
                TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
                echo; echo "\t####"; \
                if [ $$TEST_RESULT -gt 0 ]; then \
                        echo "\t#### Test $$TEST PASSED ####";\
                else    echo "\t#### Test $$TEST FAILED ####";\
                fi; \
                echo "\t####"; echo; \
        done
 
 
nctests: prepare_sw prepare_rtl
        @if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
        @echo
        @echo "Beginning loop that will complete the following tests: $(TESTS)"
        @echo
        @for TEST in $(TESTS); do \
                echo "################################################################################"; \
                echo; \
                echo "\t#### Current test: $$TEST ####"; echo; \
                echo "\t#### Compiling software ####"; echo; \
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
                rm -f $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST.hex $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
                sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
                        -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
                        -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
                        -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
                        -e \\!^//.*\$$!d -e \\!^\$$!d ; \
                echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                if [ ! -z $$VCD ]; \
                        then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                        echo "+access+r" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                fi; \
                echo "+nocopyright" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
                echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
                echo ; \
                echo "\t#### Beginning simulation ####"; \
                time -p ncverilog -f $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated -Q -l $(SIM_RESULTS_DIR)/$$TEST-ius-out.log $(RTL_SIM_FLAGS); \
                if [ $$? -gt 0 ]; then exit $$?; fi; \
                TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
                echo; echo "\t####"; \
                if [ $$TEST_RESULT -gt 0 ]; then \
                        echo "\t#### Test $$TEST PASSED ####";\
                else    echo "\t#### Test $$TEST FAILED ####";\
                fi; \
                echo "\t####"; echo; \
        done
 
 
 
 
#ps aux | grep "xterm -e $(SIM_BIN_DIR)/monitor.sh $(SIM_RESULTS_DIR)/$$TEST-executed.log" | awk '{ print $2 }' | xargs kill; \
 
#               if [ ! -z $OR1K_MONITOR ]; then \
                        if [ ! -z $DISPLAY ]; then \
                                $(SIM_BIN_DIR)/monitor.sh $(SIM_RESULTS_DIR)/$$TEST-executed.log; \
                        fi; \
                fi; \
 
 
clean-sw:
        @for TEST in $(TESTS); do \
                echo "Current test: $$TEST"; \
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
                echo "Current test sw directory: " $$CURRENT_TEST_SW_DIR; \
                $(MAKE) -C $$CURRENT_TEST_SW_DIR clean; \
        done
        $(MAKE) -C $(SW_DIR)/support clean
        $(MAKE) -C $(SW_DIR)/utils clean
 
clean-sim:
        rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.*

Line No.	Rev	Author	Line
1	22	julius
2			`CUR_DIR=$(shell pwd)`
3			`PROJECT_ROOT=$(CUR_DIR)/../..`
4
5	33	julius	`# Define these tests if none were on the command line`
6			`TESTS ?= basic-nocache cbasic-nocache-O2 dhry-nocache-O2 except-nocache mmu-nocache mul-nocache-O2 syscall-nocache tick-nocache uart-nocache basic-icdc cbasic-icdc-O2 dhry-icdc-O2 except-icdc mmu-icdc mul-icdc-O2 syscall-icdc tick-icdc uart-icdc`
7			`#TESTS = basic-nocache cbasic-nocache-O2`
8	22	julius
9			`SIM_DIR=$(PROJECT_ROOT)/sim`
10			`SIM_RUN_DIR=$(SIM_DIR)/run`
11			`SIM_BIN_DIR=$(SIM_DIR)/bin`
12			`SIM_RESULTS_DIR=$(SIM_DIR)/results`
13
14			`BENCH_DIR=$(PROJECT_ROOT)/bench`
15			`BACKEND_DIR=$(PROJECT_ROOT)/backend`
16			`BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog`
17
18			`RTL_VERILOG_DIR=$(PROJECT_ROOT)/rtl/verilog`
19
20
21			`SW_DIR=$(PROJECT_ROOT)/sw`
22
23			`ICARUS=iverilog`
24			`ICARUS_VVP=vvp`
25			`ICARUS_COMMAND_FILE=icarus.scr`
26			`SIM_MEM_FILE="flash.in"`
27	32	julius	`SIM_SUCCESS_MESSAGE=deaddead`
28	22	julius
29			`.PHONY: prepare_rtl`
30			`prepare_rtl:`
31	26	julius	`@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v`
32	22	julius
33	26	julius	`.PHONY: prepare_sw`
34			`prepare_sw:`
35			`@$(MAKE) -C $(SW_DIR)/support`
36			`@$(MAKE) -C $(SW_DIR)/utils`
37
38	35	julius	`tests: prepare_sw prepare_rtl`
39	22	julius	`@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi`
40	33	julius	`@echo`
41			`@echo "Beginning loop that will complete the following tests: $(TESTS)"`
42			`@echo`
43	31	julius	`@for TEST in $(TESTS); do \`
44	33	julius	`echo "################################################################################"; \`
45			`echo; \`
46			`echo "\t#### Current test: $$TEST ####"; echo; \`
47	32	julius	`echo "\t#### Compiling software ####"; echo; \`
48	22	julius	CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST \| cut -d "-" -f 1`; \
49			`$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \`
50			`rm -f $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \`
51			`ln -s $$CURRENT_TEST_SW_DIR/$$TEST.hex $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \`
52			`sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \`
53			`-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \`
54			`-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \`
55			`-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \`
56			`-e \\!^//.*\$$!d -e \\!^\$$!d ; \`
57	34	julius	`echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
58	26	julius	`if [ ! -z $$VCD ]; \`
59			`then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
60			`fi; \`
61	34	julius	echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
62			echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
63	22	julius	`echo ; \`
64	32	julius	`echo "\t#### Compiling RTL ####"; \`
65	22	julius	`rm -f $(SIM_RUN_DIR)/a.out; \`
66			`$(ICARUS) -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(RTL_SIM_FLAGS); \`
67			`echo; \`
68	32	julius	`echo "\t#### Beginning simulation ####"; \`
69	33	julius	`time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \`
70	36	julius	`if [ $$? -gt 0 ]; then exit $$?; fi; \`
71			TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log \| grep report \| grep $(SIM_SUCCESS_MESSAGE) -c`; \
72	33	julius	`echo; echo "\t####"; \`
73	34	julius	`if [ $$TEST_RESULT -gt 0 ]; then \`
74	32	julius	`echo "\t#### Test $$TEST PASSED ####";\`
75			`else echo "\t#### Test $$TEST FAILED ####";\`
76			`fi; \`
77	33	julius	`echo "\t####"; echo; \`
78	22	julius	`done`
79	33	julius
80
81	35	julius	`nctests: prepare_sw prepare_rtl`
82			`@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi`
83			`@echo`
84			`@echo "Beginning loop that will complete the following tests: $(TESTS)"`
85			`@echo`
86			`@for TEST in $(TESTS); do \`
87			`echo "################################################################################"; \`
88			`echo; \`
89			`echo "\t#### Current test: $$TEST ####"; echo; \`
90			`echo "\t#### Compiling software ####"; echo; \`
91			CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST \| cut -d "-" -f 1`; \
92			`$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \`
93			`rm -f $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \`
94			`ln -s $$CURRENT_TEST_SW_DIR/$$TEST.hex $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \`
95			`sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \`
96			`-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \`
97			`-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \`
98			`-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \`
99			`-e \\!^//.*\$$!d -e \\!^\$$!d ; \`
100			`echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
101			`if [ ! -z $$VCD ]; \`
102			`then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
103			`echo "+access+r" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
104			`fi; \`
105	36	julius	`echo "+nocopyright" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
106			`echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
107	35	julius	echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
108			echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
109			`echo ; \`
110			`echo "\t#### Beginning simulation ####"; \`
111	36	julius	`time -p ncverilog -f $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated -Q -l $(SIM_RESULTS_DIR)/$$TEST-ius-out.log $(RTL_SIM_FLAGS); \`
112			`if [ $$? -gt 0 ]; then exit $$?; fi; \`
113			TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log \| grep report \| grep $(SIM_SUCCESS_MESSAGE) -c`; \
114	35	julius	`echo; echo "\t####"; \`
115			`if [ $$TEST_RESULT -gt 0 ]; then \`
116			`echo "\t#### Test $$TEST PASSED ####";\`
117			`else echo "\t#### Test $$TEST FAILED ####";\`
118			`fi; \`
119			`echo "\t####"; echo; \`
120			`done`
121	33	julius
122
123	35	julius
124
125	31	julius	`#ps aux \| grep "xterm -e $(SIM_BIN_DIR)/monitor.sh $(SIM_RESULTS_DIR)/$$TEST-executed.log" \| awk '{ print $2 }' \| xargs kill; \`
126	22	julius
127	31	julius	`# if [ ! -z $OR1K_MONITOR ]; then \`
128			`if [ ! -z $DISPLAY ]; then \`
129			`$(SIM_BIN_DIR)/monitor.sh $(SIM_RESULTS_DIR)/$$TEST-executed.log; \`
130			`fi; \`
131			`fi; \`
132	22	julius
133
134			`clean-sw:`
135			`@for TEST in $(TESTS); do \`
136			`echo "Current test: $$TEST"; \`
137			CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST \| cut -d "-" -f 1`; \
138			`echo "Current test sw directory: " $$CURRENT_TEST_SW_DIR; \`
139			`$(MAKE) -C $$CURRENT_TEST_SW_DIR clean; \`
140			`done`
141	31	julius	`$(MAKE) -C $(SW_DIR)/support clean`
142			`$(MAKE) -C $(SW_DIR)/utils clean`
143
144			`clean-sim:`
145	34	julius	`rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/.`

Browse

Tools

Subversion Repositories test_project

[/] [test_project/] [trunk/] [sim/] [bin/] [Makefile] - Blame information for rev 36