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julius |
######################################################################
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#### ####
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#### ORPSoCv2 Testbenches Makefile ####
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#### ####
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#### Description ####
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#### ORPSoCv2 Testbenches Makefile, containing rules for ####
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#### configuring and running different tests on the current ####
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#### ORPSoC design. ####
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#### ####
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#### To Do: ####
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#### - Verilator tests ####
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#### ####
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#### Author(s): ####
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#### - jb, jb@orsoc.se ####
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#### ####
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#### ####
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######################################################################
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#### ####
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#### Copyright (C) 2009 Authors and OPENCORES.ORG ####
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#### ####
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#### This source file may be used and distributed without ####
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#### restriction provided that this copyright statement is not ####
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#### removed from the file and that any derivative work contains ####
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#### the original copyright notice and the associated disclaimer. ####
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#### ####
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#### This source file is free software; you can redistribute it ####
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#### and/or modify it under the terms of the GNU Lesser General ####
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#### Public License as published by the Free Software Foundation; ####
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#### either version 2.1 of the License, or (at your option) any ####
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#### later version. ####
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#### ####
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#### This source is distributed in the hope that it will be ####
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#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
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#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
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#### PURPOSE. See the GNU Lesser General Public License for more ####
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#### details. ####
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#### ####
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#### You should have received a copy of the GNU Lesser General ####
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#### Public License along with this source; if not, download it ####
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#### from http://www.opencores.org/lgpl.shtml ####
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#### ####
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######################################################################
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22 |
julius |
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39 |
julius |
# Use: Type "make rtl-tests" to run all of the tests on the RTL model
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# run in the Icarus Verilog simulator.
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# The results and output of the simulation are in the results path,
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# in parallel to the simulation run and bin paths. This directory is
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# not checked into the repository, but is created when simulations are
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# run.
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# To run an individual test, specify it in the variable TESTS when
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# calling make, like "make rtl-tests TESTS="mmu-nocache mul-idcd-O2".
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# VCD (value change dumps, usable in a waveform viewer, such as gtkwave
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# to inspect the internals of the system graphically) files can be
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# generated by calling the make with VCD=1, like "make rtl-tests VCD=1"
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# and a vcd file will be created in the simulation results directory,
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# and named according to the test run which generated it.
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# The rtl simulations can also be run with Cadences NCSim by using
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# rtl-nc-tests in the place of rtl-tests.
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# It is possible to speed up the simulation slightly by disabling
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# log output of the processor's state to files by defining
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# NO_SIM_LOGGING, eg. make rtl-tests TESTS=except-icdc NO_SIM_LOGGING=1
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# Name of the directory we're currently in
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22 |
julius |
CUR_DIR=$(shell pwd)
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39 |
julius |
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# The root path of the whole project
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julius |
PROJECT_ROOT=$(CUR_DIR)/../..
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39 |
julius |
# Tests is only defined if it wasn't already defined when make was called
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# This is the default list of every test that is currently possible
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33 |
julius |
TESTS ?= basic-nocache cbasic-nocache-O2 dhry-nocache-O2 except-nocache mmu-nocache mul-nocache-O2 syscall-nocache tick-nocache uart-nocache basic-icdc cbasic-icdc-O2 dhry-icdc-O2 except-icdc mmu-icdc mul-icdc-O2 syscall-icdc tick-icdc uart-icdc
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julius |
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39 |
julius |
# Paths to other important parts of this test suite
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julius |
SIM_DIR=$(PROJECT_ROOT)/sim
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SIM_RUN_DIR=$(SIM_DIR)/run
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SIM_BIN_DIR=$(SIM_DIR)/bin
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SIM_RESULTS_DIR=$(SIM_DIR)/results
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BENCH_DIR=$(PROJECT_ROOT)/bench
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BACKEND_DIR=$(PROJECT_ROOT)/backend
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BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
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RTL_VERILOG_DIR=$(PROJECT_ROOT)/rtl/verilog
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SW_DIR=$(PROJECT_ROOT)/sw
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ICARUS=iverilog
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ICARUS_VVP=vvp
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ICARUS_COMMAND_FILE=icarus.scr
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julius |
VLT_COMMAND_FILE=verilator.scr
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julius |
SIM_MEM_FILE="flash.in"
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julius |
SIM_SUCCESS_MESSAGE=deaddead
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julius |
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.PHONY: prepare_rtl
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prepare_rtl:
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julius |
@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
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julius |
@cd $(RTL_VERILOG_DIR) && sed '/defparam/!s/\([a-zA-Z0-9_]\)\.//g' intercon.vm > intercon.v
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julius |
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julius |
.PHONY: prepare_sw
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prepare_sw:
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@$(MAKE) -C $(SW_DIR)/support
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@$(MAKE) -C $(SW_DIR)/utils
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39 |
julius |
# Rough guide to how these tests work:
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# First, the couple of custom, required, software tools under sw/utils are
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# compiled, and then the software library files.
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# Next the few verilog files that need preperation are taken care of.
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# The test begins by starting a loop in bash using on the strings defined in
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# TESTS. Each one corresponds to a certain module of software for the OpenRISC
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# that is included in this test suite. Under the sw/ path is a set of paths,
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# and all except the support/ and utils/ paths contain code which is run to test
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# the OR1k used in this test suite. For each of these software modules, it is
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# possible that different tests are done using the same module. These tests can
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# vary by either using different levels of optimisation during compilation,
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# and/or by having the OR1k's caches enabled or disabled.
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# Each test has a unique name, and under the $(SIM_RESULTS_DIR), which is
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# usually just ../results, log files, and optionally VCD files, are created for
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# inspection later and are named according to the test. Inspect the file
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# bench/verilog/or1200_monitor.v to find out in detail what each log consists of.
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# For each test, a few things occur. First the software that will run inside
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# the simulated OR1k system is compiled, converted to a format which can be read
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# into the flash memory model via $readmemh() and linked to the sim/run
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# directory as $(SIM_MEM_FILE), which currently is flash.in. Next a compilation
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# script for icarus is generated, containing a list of all the RTL files and
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# include directories. Next, an include file for the verilog testbench is
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# generated, containing a string of the name of the current test, path to the
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# results directory (for VCD generation) and any other things which might vary
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# from test to test. This is not done by +define lines in the icarus script
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# because of string handling incosistencies between different simulators and
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# shells.
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# Once all the files are generated, icarus is called to compile the rtl design,
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# and then run it.
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# Each of the tested software modules have code which will trigger the
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# simulation to be stopped by use of the l.nop instruction with an immediate
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# value of 1. When the simulation finishes, the simulation executable exits and
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# the log of the simulation is inspected for the expected output. Currently, the
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# string "deaddead" indicates that the software completed successfully. This is
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# counted as the ORPSoC "passing" the test. In fact, whether the system did the
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# right thing or not requires more inspection, but roughly this is a good
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# indicator that nothing major went wrong.
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# Once the current test is finished, the next begins with the compilation of its
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# software and linking of the resulting hex file to the run path, etc.
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rtl-tests: prepare_sw prepare_rtl
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22 |
julius |
@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
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33 |
julius |
@echo
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@echo "Beginning loop that will complete the following tests: $(TESTS)"
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@echo
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julius |
@for TEST in $(TESTS); do \
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33 |
julius |
echo "################################################################################"; \
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echo; \
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echo "\t#### Current test: $$TEST ####"; echo; \
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32 |
julius |
echo "\t#### Compiling software ####"; echo; \
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22 |
julius |
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
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$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
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rm -f $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
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ln -s $$CURRENT_TEST_SW_DIR/$$TEST.hex $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
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sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
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-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
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-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
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-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
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-e \\!^//.*\$$!d -e \\!^\$$!d ; \
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34 |
julius |
echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
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26 |
julius |
if [ ! -z $$VCD ]; \
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then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
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fi; \
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julius |
echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
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echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
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julius |
if [ -z $$NO_SIM_LOGGING ]; then \
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echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
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fi; \
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julius |
echo ; \
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32 |
julius |
echo "\t#### Compiling RTL ####"; \
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julius |
rm -f $(SIM_RUN_DIR)/a.out; \
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julius |
$(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(RTL_SIM_FLAGS); \
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julius |
echo; \
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32 |
julius |
echo "\t#### Beginning simulation ####"; \
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julius |
time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \
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julius |
if [ $$? -gt 0 ]; then exit $$?; fi; \
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TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
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julius |
echo; echo "\t####"; \
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julius |
if [ $$TEST_RESULT -gt 0 ]; then \
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julius |
echo "\t#### Test $$TEST PASSED ####";\
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else echo "\t#### Test $$TEST FAILED ####";\
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fi; \
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33 |
julius |
echo "\t####"; echo; \
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julius |
done
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33 |
julius |
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39 |
julius |
# Use NCSIM instead of icarus
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rtl-nc-tests: prepare_sw prepare_rtl
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julius |
@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
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@echo
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@echo "Beginning loop that will complete the following tests: $(TESTS)"
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@echo
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@for TEST in $(TESTS); do \
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echo "################################################################################"; \
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echo; \
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echo "\t#### Current test: $$TEST ####"; echo; \
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echo "\t#### Compiling software ####"; echo; \
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CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
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$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
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rm -f $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
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ln -s $$CURRENT_TEST_SW_DIR/$$TEST.hex $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
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sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
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-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
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-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
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-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
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-e \\!^//.*\$$!d -e \\!^\$$!d ; \
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echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
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if [ ! -z $$VCD ]; \
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then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
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echo "+access+r" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
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fi; \
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36 |
julius |
echo "+nocopyright" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
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echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
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35 |
julius |
echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
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echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
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39 |
julius |
if [ -z $$NO_SIM_LOGGING ]; then \
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echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
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fi; \
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35 |
julius |
echo ; \
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echo "\t#### Beginning simulation ####"; \
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36 |
julius |
time -p ncverilog -f $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated -Q -l $(SIM_RESULTS_DIR)/$$TEST-ius-out.log $(RTL_SIM_FLAGS); \
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if [ $$? -gt 0 ]; then exit $$?; fi; \
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TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
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35 |
julius |
echo; echo "\t####"; \
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| 230 |
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if [ $$TEST_RESULT -gt 0 ]; then \
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echo "\t#### Test $$TEST PASSED ####";\
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else echo "\t#### Test $$TEST FAILED ####";\
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fi; \
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echo "\t####"; echo; \
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done
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33 |
julius |
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41 |
julius |
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vlt-tests: prepare_sw prepare_rtl prepare_vlt
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@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
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@echo
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| 242 |
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@echo "Beginning loop that will complete the following tests: $(TESTS)"
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@echo
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| 244 |
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@for TEST in $(TESTS); do \
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echo "################################################################################"; \
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echo; \
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| 247 |
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echo "\t#### Current test: $$TEST ####"; echo; \
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echo "\t#### Compiling software ####"; echo; \
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CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
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$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
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rm -f $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
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ln -s $$CURRENT_TEST_SW_DIR/$$TEST.hex $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
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echo ; \
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| 254 |
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echo "\t#### Compiling RTL ####"; \
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rm -f $(SIM_RUN_DIR)/a.out; \
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$(ICARUS) -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(RTL_SIM_FLAGS); \
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echo; \
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echo "\t#### Beginning simulation ####"; \
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time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \
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if [ $$? -gt 0 ]; then exit $$?; fi; \
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TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
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| 262 |
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echo; echo "\t####"; \
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| 263 |
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if [ $$TEST_RESULT -gt 0 ]; then \
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| 264 |
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echo "\t#### Test $$TEST PASSED ####";\
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| 265 |
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else echo "\t#### Test $$TEST FAILED ####";\
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| 266 |
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fi; \
|
| 267 |
|
|
echo "\t####"; echo; \
|
| 268 |
|
|
done
|
| 269 |
|
|
|
| 270 |
43 |
julius |
prepare_vlt: prepare_rtl
|
| 271 |
41 |
julius |
sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(SIM_RUN_DIR)/$(VLT_COMMAND_FILE).generated \
|
| 272 |
|
|
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
|
| 273 |
|
|
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
|
| 274 |
|
|
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
| 275 |
|
|
-e \\!^//.*\$$!d -e \\!^\$$!d;
|
| 276 |
42 |
julius |
verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top -Mdir . -sc -f $(VLT_COMMAND_FILE).generated
|
| 277 |
41 |
julius |
|
| 278 |
|
|
|
| 279 |
22 |
julius |
clean-sw:
|
| 280 |
|
|
@for TEST in $(TESTS); do \
|
| 281 |
|
|
echo "Current test: $$TEST"; \
|
| 282 |
|
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
| 283 |
|
|
echo "Current test sw directory: " $$CURRENT_TEST_SW_DIR; \
|
| 284 |
|
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR clean; \
|
| 285 |
|
|
done
|
| 286 |
31 |
julius |
$(MAKE) -C $(SW_DIR)/support clean
|
| 287 |
|
|
$(MAKE) -C $(SW_DIR)/utils clean
|
| 288 |
|
|
|
| 289 |
|
|
clean-sim:
|
| 290 |
34 |
julius |
rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.*
|
