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######################################################################
####                                                              ####
####  ORPSoCv2 Testbenches Makefile                               ####
####                                                              ####
####  Description                                                 ####
####  ORPSoCv2 Testbenches Makefile, containing rules for         ####
####  configuring and running different tests on the current      ####
####  ORPSoC design.                                              ####
####                                                              ####
####  To Do:                                                      ####
####   - Verilator tests                                          ####
####                                                              ####
####  Author(s):                                                  ####
####      - jb, jb@orsoc.se                                       ####
####                                                              ####
####                                                              ####
######################################################################
####                                                              ####
#### Copyright (C) 2009 Authors and OPENCORES.ORG                 ####
####                                                              ####
#### This source file may be used and distributed without         ####
#### restriction provided that this copyright statement is not    ####
#### removed from the file and that any derivative work contains  ####
#### the original copyright notice and the associated disclaimer. ####
####                                                              ####
#### This source file is free software; you can redistribute it   ####
#### and/or modify it under the terms of the GNU Lesser General   ####
#### Public License as published by the Free Software Foundation; ####
#### either version 2.1 of the License, or (at your option) any   ####
#### later version.                                               ####
####                                                              ####
#### This source is distributed in the hope that it will be       ####
#### useful, but WITHOUT ANY WARRANTY; without even the implied   ####
#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ####
#### PURPOSE.  See the GNU Lesser General Public License for more ####
#### details.                                                     ####
####                                                              ####
#### You should have received a copy of the GNU Lesser General    ####
#### Public License along with this source; if not, download it   ####
#### from http://www.opencores.org/lgpl.shtml                     ####
####                                                              ####
######################################################################
 
# Use: Type "make rtl-tests" to run all of the tests on the RTL model
# run in the Icarus Verilog simulator.
 
# The results and output of the simulation are in the results path,
# in parallel to the simulation run and bin paths. This directory is
# not checked into the repository, but is created when simulations are
# run.
 
# To run an individual test, specify it in the variable TESTS when
# calling make, like "make rtl-tests TESTS="mmu-nocache mul-idcd-O2".
 
# VCD (value change dumps, usable in a waveform viewer, such as gtkwave
# to inspect the internals of the system graphically) files can be
# generated by calling the make with VCD=1, like "make rtl-tests VCD=1"
# and a vcd file will be created in the simulation results directory,
# and named according to the test run which generated it.
 
# The rtl simulations can also be run with Cadences NCSim by using
# rtl-nc-tests in the place of rtl-tests.
 
# It is possible to speed up the simulation slightly by disabling
# log output of the processor's state to files by defining
# NO_SIM_LOGGING, eg. make rtl-tests TESTS=except-icdc NO_SIM_LOGGING=1
 
 
# Name of the directory we're currently in
CUR_DIR=$(shell pwd)
 
# The root path of the whole project
PROJECT_ROOT=$(CUR_DIR)/../..
 
# Tests is only defined if it wasn't already defined when make was called
# This is the default list of every test that is currently possible
TESTS ?= basic-nocache cbasic-nocache-O2 dhry-nocache-O2 except-nocache mmu-nocache mul-nocache-O2 syscall-nocache tick-nocache uart-nocache basic-icdc cbasic-icdc-O2 dhry-icdc-O2 except-icdc mmu-icdc mul-icdc-O2 syscall-icdc tick-icdc uart-icdc
 
# Paths to other important parts of this test suite
SIM_DIR=$(PROJECT_ROOT)/sim
SIM_RUN_DIR=$(SIM_DIR)/run
SIM_BIN_DIR=$(SIM_DIR)/bin
SIM_RESULTS_DIR=$(SIM_DIR)/results
SIM_VLT_DIR=$(SIM_DIR)/vlt
BENCH_DIR=$(PROJECT_ROOT)/bench
BACKEND_DIR=$(PROJECT_ROOT)/backend
BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
BENCH_SYSC_DIR=$(BENCH_DIR)/sysc
BENCH_SYSC_SRC_DIR=$(BENCH_SYSC_DIR)/src
BENCH_SYSC_INCLUDE_DIR=$(BENCH_SYSC_DIR)/include
RTL_VERILOG_DIR=$(PROJECT_ROOT)/rtl/verilog
SW_DIR=$(PROJECT_ROOT)/sw
 
ICARUS=iverilog
ICARUS_VVP=vvp
ICARUS_COMMAND_FILE=icarus.scr
VLT_COMMAND_FILE=verilator.scr
SIM_SUCCESS_MESSAGE=deaddead
 
# If USE_SDRAM is defined we'll add it to the simulator's defines on the
# command line becuase it's used by many different modules and it's easier
# to do it this way than make them all include a file.
ifdef USE_SDRAM
RTL_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)"
endif
SIM_FLASH_MEM_FILE="flash.in"
FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"
SIM_SRAM_MEM_FILE="sram.vmem"
 
TESTS_PASSED=0
TESTS_PERFORMED=0;
 
################################################################################
# Event-driven simulator build rules (Icarus, NCSim)
################################################################################
 
.PHONY: prepare_rtl
prepare_rtl:
        @cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
        @cd $(RTL_VERILOG_DIR) && sed '/defparam/!s/\([a-zA-Z0-9_]\)\.//g' intercon.vm > intercon.v
 
 
ifdef UART_PRINTF
TEST_SW_MAKE_OPTS=UART_PRINTF=1
endif
 
.PHONY: prepare_sw
prepare_sw:
        @$(MAKE) -C $(SW_DIR)/support all $(TEST_SW_MAKE_OPTS)
        @$(MAKE) -C $(SW_DIR)/utils all
 
# A rule with UART_PRINTF hard defined ... used by verilator make sw
prepare_sw_uart_printf:
        @$(MAKE) -C $(SW_DIR)/support all UART_PRINTF=1 $(TEST_SW_MAKE_OPTS)
        @$(MAKE) -C $(SW_DIR)/utils all
 
 
# Rough guide to how these tests work:
# First, the couple of custom, required, software tools under sw/utils are
# compiled, and then the software library files.
# Next the few verilog files that need preperation are taken care of.
# The test begins by starting a loop in bash using on the strings defined in
# TESTS. Each one corresponds to a certain module of software for the OpenRISC
# that is included in this test suite. Under the sw/ path is a set of paths,
# and all except the support/ and utils/ paths contain code which is run to
# test the OR1k used in this test suite. For each of these software modules,
# it is possible that different tests are done using the same module. These
# tests can vary by either using different levels of optimisation during
# compilation, and/or by having the OR1k's caches enabled or disabled.
# Each test has a unique name, and under the $(SIM_RESULTS_DIR), which is
# usually just ../results, log files, and optionally VCD files, are created for
# inspection later and are named according to the test. Inspect the file
# bench/verilog/or1200_monitor.v to find out in detail what each log consists
# of.
# For each test, a few things occur. First the software that will run inside
# the simulated OR1k system is compiled, converted to a format which can be
# read
# into the flash memory model via $readmemh() and linked to the sim/run
# directory as $(SIM_FLASH_MEM_FILE), which currently is flash.in. Next a
# compilation script for icarus is generated, containing a list of all the
# RTL files and include directories. Next, an include file for the verilog
# testbench is generated, containing a string of the name of the current
# test, path to the results directory (for VCD generation) and any other
# things which might vary from test to test. This is not done by +define
# lines in the icarus script because of string handling incosistencies
# between different simulators and shells.
# Once all the files are generated, icarus is called to compile the rtl
# design, and then run it. Each of the tested software modules have code which
# will trigger the simulation to be stopped by use of the l.nop instruction
# with an immediate value of 1. When the simulation finishes, the simulation
# executable exits and the log of the simulation is inspected for the expected
# output. Currently, the string "deaddead" indicates that the software
# completed successfully. This is counted as the ORPSoC "passing" the test. In
# fact, whether the system did the right thing or not requires more
# inspection, but roughly this is a good indicator that nothing major went
# wrong.
# Once the current test is finished, the next begins with the compilation of its
# software and linking of the resulting hex file to the run path, etc.
# Main RAM setup - (RTL simulation with Icarus/NCSim only!):
# Define USE_SDRAM to enable the external SDRAM, otherwise the simulation
# defaults to an internal SRAM. Eg. $ make rtl-tests USE_SDRAM=1 VCD=1
# Verilator defaults to internal memories
rtl-tests: prepare_sw prepare_rtl
        @if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
        @echo
        @echo "Beginning loop that will complete the following tests: $(TESTS)"
        @echo
        @for TEST in $(TESTS); do \
                echo "################################################################################"; \
                echo; \
                echo "\t#### Current test: $$TEST ####"; echo; \
                echo "\t#### Compiling software ####"; echo; \
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS); \
                rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
                rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
                sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
                        -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
                        -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
                        -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
                        -e \\!^//.*\$$!d -e \\!^\$$!d ; \
                echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                if [ ! -z $$VCD ]; \
                        then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                fi; \
                if [ ! -z $$UART_PRINTF ]; \
                        then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                fi; \
                echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
                echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
                if [ -z $$NO_SIM_LOGGING ]; then \
                        echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
                fi; \
                echo ; \
                echo "\t#### Compiling RTL ####"; \
                rm -f $(SIM_RUN_DIR)/a.out; \
                $(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(RTL_SIM_FLAGS); \
                echo; \
                echo "\t#### Beginning simulation ####"; \
                time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \
                if [ $$? -gt 0 ]; then exit $$?; fi; \
                TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
                echo; echo "\t####"; \
                if [ $$TEST_RESULT -gt 0 ]; then \
                        echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
                else    echo "\t#### Test $$TEST FAILED ####";\
                fi; \
                echo "\t####"; echo; \
                TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
        done; \
        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
 
 
 
# Use NCSIM instead of icarus
rtl-nc-tests: prepare_sw prepare_rtl
        @if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
        @echo
        @echo "Beginning loop that will complete the following tests: $(TESTS)"
        @echo
        @for TEST in $(TESTS); do \
                echo "################################################################################"; \
                echo; \
                echo "\t#### Current test: $$TEST ####"; echo; \
                echo "\t#### Compiling software ####"; echo; \
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
                rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
                rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST_twobyte_sizefirst.hex $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST_fourbyte.hex $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
                sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
                        -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
                        -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
                        -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
                        -e \\!^//.*\$$!d -e \\!^\$$!d ; \
                echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                if [ ! -z $$VCD ]; \
                        then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                        echo "+access+r" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                fi; \
                if [ ! -z $$UART_PRINTF ]; \
                        then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                fi; \
                if [ ! -z $$USE_SDRAM ]; then \
                        echo "\`define USE_SDRAM" >> $(SIM_RUN_DIR)/test_define.v; \
                fi; \
                echo "+nocopyright" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
                echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
                if [ -z $$NO_SIM_LOGGING ]; then \
                        echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
                fi; \
                echo ; \
                echo "\t#### Beginning simulation ####"; \
                time -p ncverilog -f $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated -Q -l $(SIM_RESULTS_DIR)/$$TEST-ius-out.log $(RTL_SIM_FLAGS); \
                if [ $$? -gt 0 ]; then exit $$?; fi; \
                TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
                echo; echo "\t####"; \
                if [ $$TEST_RESULT -gt 0 ]; then \
                        echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
                else    echo "\t#### Test $$TEST FAILED ####";\
                fi; \
                echo "\t####"; echo; \
                TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
        done; \
        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
 
################################################################################
# Verilator model build rules
################################################################################
 
 
 
 
# List of System C models - use this list to link the sources into the Verilator
# build directory
SYSC_MODELS=OrpsocAccess TraceSC
 
# Only need the trace target if we are tracing
ifneq (,$(findstring -trace, $(VLT_FLAGS)))
VLT_TRACEOBJ = SpTraceVcdC
endif
 
# This is the list of extra models we'll issue make commands for
# Included is the SystemPerl trace model
SYSC_MODELS_BUILD=$(SYSC_MODELS) $(VLT_TRACEOBJ)
 
prepare_vlt: prepare_rtl vlt_model_links $(SIM_VLT_DIR)/Vorpsoc_top
 
$(SIM_VLT_DIR)/Vorpsoc_top: $(SIM_VLT_DIR)/libVorpsoc_top.a $(SIM_VLT_DIR)/OrpsocMain.o
# Final linking of the simulation executable. Order of libraries here is important!
        @echo; echo "\tGenerating simulation executable"; echo
        cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o Vorpsoc_top -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/lib-linux64 OrpsocMain.o -lVorpsoc_top -lmodules -lsystemc
 
$(SIM_VLT_DIR)/OrpsocMain.o:
# Now compile the top level systemC "testbench" module
        @echo; echo "\tCompiling top level SystemC testbench"; echo
        cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
 
$(SIM_VLT_DIR)/libVorpsoc_top.a: $(SIM_VLT_DIR)/Vorpsoc_top__ALL.a vlt_modules_compile $(SIM_VLT_DIR)/verilated.o
# Now archive all of the libraries from verilator witht he other modules we might have
        @echo; echo "\tArchiving libraries into libVorpsoc_top.a"; echo
        @cd $(SIM_VLT_DIR) && \
        cp Vorpsoc_top__ALL.a libVorpsoc_top.a && \
        ar rcs libVorpsoc_top.a verilated.o; \
        for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
                ar rcs libVorpsoc_top.a $$SYSCMODEL.o; \
        done
 
$(SIM_VLT_DIR)/verilated.o:
        @echo; echo "\tCompiling verilated.o"; echo
        @cd $(SIM_VLT_DIR) && \
        $(MAKE) -f Vorpsoc_top.mk verilated.o
 
.PHONY: vlt_modules_compile
vlt_modules_compile:
# Compile the module files
        @echo; echo "\tCompiling SystemC models"
        @cd $(SIM_VLT_DIR) && \
        for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
                echo;echo "\t$$SYSCMODEL"; echo; \
                $(MAKE) -f Vorpsoc_top.mk $$SYSCMODEL.o; \
        done
 
$(SIM_VLT_DIR)/Vorpsoc_top__ALL.a: $(SIM_VLT_DIR)/Vorpsoc_top.mk
        @echo; echo "\tCompiling main design"; echo
        @cd $(SIM_VLT_DIR) && \
        $(MAKE) -f Vorpsoc_top.mk Vorpsoc_top__ALL.a
 
$(SIM_VLT_DIR)/Vorpsoc_top.mk: $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated $(SIM_VLT_DIR)/libmodules.a
# Now call verilator to generate the .mk files
        @echo; echo "\tGenerating makefiles with Verilator"; echo
        cd $(SIM_VLT_DIR) && \
        verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(VLT_COMMAND_FILE).generated
 
# SystemC modules library
$(SIM_VLT_DIR)/libmodules.a:
        @echo; echo "\tCompiling SystemC modules"; echo
        @$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make
 
 
# Verilator command script
# Generate the compile script to give Verilator
$(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated:
        @echo; echo "\tGenerating verilator compile script"; echo
        @sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated \
                -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
                -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
                -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
                -e \\!^//.*\$$!d -e \\!^\$$!d;
 
.PHONY: vlt_model_links
vlt_model_links:
# Link all the required system C model files into the verilator work dir
        @echo; echo "\tLinking SystemC model source to verilator build path"; echo
        @if [ ! -d $(SIM_VLT_DIR) ]; then mkdir $(SIM_VLT_DIR); fi
        @cd $(SIM_VLT_DIR) && \
        for SYSCMODEL in $(SYSC_MODELS); do \
                if [ ! -e $$SYSCMODEL.cpp ]; then \
                        ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp .; \
                        ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h .; \
                fi; \
        done
 
 
################################################################################
# Verilator test loop
################################################################################
 
# Verilator defaults to internal memories
vlt-tests: prepare_sw_uart_printf prepare_rtl prepare_vlt
        @echo
        @echo "Beginning loop that will complete the following tests: $(TESTS)"
        @echo
        @for TEST in $(TESTS); do \
                echo "################################################################################"; \
                echo; \
                echo "\t#### Current test: $$TEST ####"; echo; \
                echo "\t#### Compiling software ####"; echo; \
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \
                rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
                echo "\t#### Beginning simulation ####"; \
                time -p $(SIM_VLT_DIR)/Vorpsoc_top; \
                if [ $$? -gt 0 ]; then exit $$?; fi; \
                TEST_RESULT=1; \
                echo; echo "\t####"; \
                if [ $$TEST_RESULT -gt 0 ]; then \
                        echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
                else    echo "\t#### Test $$TEST FAILED ####";\
                fi; \
                echo "\t####"; echo; \
                TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
        done; \
        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
 
 
################################################################################
# Cleaning rules
################################################################################
 
clean-sw:
        @for TEST in $(TESTS); do \
                echo "Current test: $$TEST"; \
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
                echo "Current test sw directory: " $$CURRENT_TEST_SW_DIR; \
                $(MAKE) -C $$CURRENT_TEST_SW_DIR clean; \
        done
        $(MAKE) -C $(SW_DIR)/support clean
        $(MAKE) -C $(SW_DIR)/utils clean
 
clean-sim:
        rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.* $(SIM_VLT_DIR)

Line No.	Rev	Author	Line
1	39	julius	`######################################################################`
2			`#### ####`
3			`#### ORPSoCv2 Testbenches Makefile ####`
4			`#### ####`
5			`#### Description ####`
6			`#### ORPSoCv2 Testbenches Makefile, containing rules for ####`
7			`#### configuring and running different tests on the current ####`
8			`#### ORPSoC design. ####`
9			`#### ####`
10			`#### To Do: ####`
11			`#### - Verilator tests ####`
12			`#### ####`
13			`#### Author(s): ####`
14			`#### - jb, jb@orsoc.se ####`
15			`#### ####`
16			`#### ####`
17			`######################################################################`
18			`#### ####`
19			`#### Copyright (C) 2009 Authors and OPENCORES.ORG ####`
20			`#### ####`
21			`#### This source file may be used and distributed without ####`
22			`#### restriction provided that this copyright statement is not ####`
23			`#### removed from the file and that any derivative work contains ####`
24			`#### the original copyright notice and the associated disclaimer. ####`
25			`#### ####`
26			`#### This source file is free software; you can redistribute it ####`
27			`#### and/or modify it under the terms of the GNU Lesser General ####`
28			`#### Public License as published by the Free Software Foundation; ####`
29			`#### either version 2.1 of the License, or (at your option) any ####`
30			`#### later version. ####`
31			`#### ####`
32			`#### This source is distributed in the hope that it will be ####`
33			`#### useful, but WITHOUT ANY WARRANTY; without even the implied ####`
34			`#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####`
35			`#### PURPOSE. See the GNU Lesser General Public License for more ####`
36			`#### details. ####`
37			`#### ####`
38			`#### You should have received a copy of the GNU Lesser General ####`
39			`#### Public License along with this source; if not, download it ####`
40			`#### from http://www.opencores.org/lgpl.shtml ####`
41			`#### ####`
42			`######################################################################`
43	22	julius
44	39	julius	`# Use: Type "make rtl-tests" to run all of the tests on the RTL model`
45			`# run in the Icarus Verilog simulator.`
46
47			`# The results and output of the simulation are in the results path,`
48			`# in parallel to the simulation run and bin paths. This directory is`
49			`# not checked into the repository, but is created when simulations are`
50			`# run.`
51
52			`# To run an individual test, specify it in the variable TESTS when`
53			`# calling make, like "make rtl-tests TESTS="mmu-nocache mul-idcd-O2".`
54
55			`# VCD (value change dumps, usable in a waveform viewer, such as gtkwave`
56			`# to inspect the internals of the system graphically) files can be`
57			`# generated by calling the make with VCD=1, like "make rtl-tests VCD=1"`
58			`# and a vcd file will be created in the simulation results directory,`
59			`# and named according to the test run which generated it.`
60
61			`# The rtl simulations can also be run with Cadences NCSim by using`
62			`# rtl-nc-tests in the place of rtl-tests.`
63
64			`# It is possible to speed up the simulation slightly by disabling`
65			`# log output of the processor's state to files by defining`
66			`# NO_SIM_LOGGING, eg. make rtl-tests TESTS=except-icdc NO_SIM_LOGGING=1`
67
68
69			`# Name of the directory we're currently in`
70	22	julius	`CUR_DIR=$(shell pwd)`
71	39	julius
72			`# The root path of the whole project`
73	22	julius	`PROJECT_ROOT=$(CUR_DIR)/../..`
74
75	39	julius	`# Tests is only defined if it wasn't already defined when make was called`
76			`# This is the default list of every test that is currently possible`
77	33	julius	`TESTS ?= basic-nocache cbasic-nocache-O2 dhry-nocache-O2 except-nocache mmu-nocache mul-nocache-O2 syscall-nocache tick-nocache uart-nocache basic-icdc cbasic-icdc-O2 dhry-icdc-O2 except-icdc mmu-icdc mul-icdc-O2 syscall-icdc tick-icdc uart-icdc`
78	22	julius
79	39	julius	`# Paths to other important parts of this test suite`
80	22	julius	`SIM_DIR=$(PROJECT_ROOT)/sim`
81			`SIM_RUN_DIR=$(SIM_DIR)/run`
82			`SIM_BIN_DIR=$(SIM_DIR)/bin`
83			`SIM_RESULTS_DIR=$(SIM_DIR)/results`
84	44	julius	`SIM_VLT_DIR=$(SIM_DIR)/vlt`
85	22	julius	`BENCH_DIR=$(PROJECT_ROOT)/bench`
86			`BACKEND_DIR=$(PROJECT_ROOT)/backend`
87			`BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog`
88	44	julius	`BENCH_SYSC_DIR=$(BENCH_DIR)/sysc`
89	47	julius	`BENCH_SYSC_SRC_DIR=$(BENCH_SYSC_DIR)/src`
90			`BENCH_SYSC_INCLUDE_DIR=$(BENCH_SYSC_DIR)/include`
91	22	julius	`RTL_VERILOG_DIR=$(PROJECT_ROOT)/rtl/verilog`
92			`SW_DIR=$(PROJECT_ROOT)/sw`
93
94			`ICARUS=iverilog`
95			`ICARUS_VVP=vvp`
96			`ICARUS_COMMAND_FILE=icarus.scr`
97	41	julius	`VLT_COMMAND_FILE=verilator.scr`
98	32	julius	`SIM_SUCCESS_MESSAGE=deaddead`
99	22	julius
100	45	julius	`# If USE_SDRAM is defined we'll add it to the simulator's defines on the`
101			`# command line becuase it's used by many different modules and it's easier`
102			`# to do it this way than make them all include a file.`
103			`ifdef USE_SDRAM`
104			`RTL_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)"`
105			`endif`
106			`SIM_FLASH_MEM_FILE="flash.in"`
107			`FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"`
108			`SIM_SRAM_MEM_FILE="sram.vmem"`
109
110	52	julius	`TESTS_PASSED=0`
111			`TESTS_PERFORMED=0;`
112
113			`################################################################################`
114			`# Event-driven simulator build rules (Icarus, NCSim)`
115			`################################################################################`
116
117	22	julius	`.PHONY: prepare_rtl`
118			`prepare_rtl:`
119	26	julius	`@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v`
120	43	julius	`@cd $(RTL_VERILOG_DIR) && sed '/defparam/!s/\([a-zA-Z0-9_]\)\.//g' intercon.vm > intercon.v`
121	22	julius
122	52	julius
123			`ifdef UART_PRINTF`
124			`TEST_SW_MAKE_OPTS=UART_PRINTF=1`
125			`endif`
126
127	26	julius	`.PHONY: prepare_sw`
128			`prepare_sw:`
129	52	julius	`@$(MAKE) -C $(SW_DIR)/support all $(TEST_SW_MAKE_OPTS)`
130			`@$(MAKE) -C $(SW_DIR)/utils all`
131	26	julius
132	54	julius	`# A rule with UART_PRINTF hard defined ... used by verilator make sw`
133	53	julius	`prepare_sw_uart_printf:`
134			`@$(MAKE) -C $(SW_DIR)/support all UART_PRINTF=1 $(TEST_SW_MAKE_OPTS)`
135			`@$(MAKE) -C $(SW_DIR)/utils all`
136	52	julius
137	53	julius
138	39	julius	`# Rough guide to how these tests work:`
139			`# First, the couple of custom, required, software tools under sw/utils are`
140			`# compiled, and then the software library files.`
141			`# Next the few verilog files that need preperation are taken care of.`
142			`# The test begins by starting a loop in bash using on the strings defined in`
143			`# TESTS. Each one corresponds to a certain module of software for the OpenRISC`
144			`# that is included in this test suite. Under the sw/ path is a set of paths,`
145	45	julius	`# and all except the support/ and utils/ paths contain code which is run to`
146			`# test the OR1k used in this test suite. For each of these software modules,`
147			`# it is possible that different tests are done using the same module. These`
148			`# tests can vary by either using different levels of optimisation during`
149			`# compilation, and/or by having the OR1k's caches enabled or disabled.`
150	39	julius	`# Each test has a unique name, and under the $(SIM_RESULTS_DIR), which is`
151			`# usually just ../results, log files, and optionally VCD files, are created for`
152			`# inspection later and are named according to the test. Inspect the file`
153	45	julius	`# bench/verilog/or1200_monitor.v to find out in detail what each log consists`
154			`# of.`
155	39	julius	`# For each test, a few things occur. First the software that will run inside`
156	45	julius	`# the simulated OR1k system is compiled, converted to a format which can be`
157			`# read`
158	39	julius	`# into the flash memory model via $readmemh() and linked to the sim/run`
159	45	julius	`# directory as $(SIM_FLASH_MEM_FILE), which currently is flash.in. Next a`
160			`# compilation script for icarus is generated, containing a list of all the`
161			`# RTL files and include directories. Next, an include file for the verilog`
162			`# testbench is generated, containing a string of the name of the current`
163			`# test, path to the results directory (for VCD generation) and any other`
164			`# things which might vary from test to test. This is not done by +define`
165			`# lines in the icarus script because of string handling incosistencies`
166			`# between different simulators and shells.`
167			`# Once all the files are generated, icarus is called to compile the rtl`
168			`# design, and then run it. Each of the tested software modules have code which`
169			`# will trigger the simulation to be stopped by use of the l.nop instruction`
170			`# with an immediate value of 1. When the simulation finishes, the simulation`
171			`# executable exits and the log of the simulation is inspected for the expected`
172			`# output. Currently, the string "deaddead" indicates that the software`
173			`# completed successfully. This is counted as the ORPSoC "passing" the test. In`
174			`# fact, whether the system did the right thing or not requires more`
175			`# inspection, but roughly this is a good indicator that nothing major went`
176			`# wrong.`
177	39	julius	`# Once the current test is finished, the next begins with the compilation of its`
178			`# software and linking of the resulting hex file to the run path, etc.`
179	45	julius	`# Main RAM setup - (RTL simulation with Icarus/NCSim only!):`
180			`# Define USE_SDRAM to enable the external SDRAM, otherwise the simulation`
181			`# defaults to an internal SRAM. Eg. $ make rtl-tests USE_SDRAM=1 VCD=1`
182			`# Verilator defaults to internal memories`
183	39	julius	`rtl-tests: prepare_sw prepare_rtl`
184	22	julius	`@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi`
185	33	julius	`@echo`
186			`@echo "Beginning loop that will complete the following tests: $(TESTS)"`
187			`@echo`
188	31	julius	`@for TEST in $(TESTS); do \`
189	33	julius	`echo "################################################################################"; \`
190			`echo; \`
191			`echo "\t#### Current test: $$TEST ####"; echo; \`
192	32	julius	`echo "\t#### Compiling software ####"; echo; \`
193	22	julius	CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST \| cut -d "-" -f 1`; \
194	52	julius	`$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS); \`
195	45	julius	`rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \`
196			`rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \`
197			`ln -s $$CURRENT_TEST_SW_DIR/$$TEST$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \`
198			`ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \`
199	22	julius	`sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \`
200			`-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \`
201			`-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \`
202			`-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \`
203			`-e \\!^//.*\$$!d -e \\!^\$$!d ; \`
204	34	julius	`echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
205	26	julius	`if [ ! -z $$VCD ]; \`
206			`then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
207			`fi; \`
208	54	julius	`if [ ! -z $$UART_PRINTF ]; \`
209			`then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
210			`fi; \`
211	34	julius	echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
212			echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
213	39	julius	`if [ -z $$NO_SIM_LOGGING ]; then \`
214			echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
215			`fi; \`
216	22	julius	`echo ; \`
217	32	julius	`echo "\t#### Compiling RTL ####"; \`
218	22	julius	`rm -f $(SIM_RUN_DIR)/a.out; \`
219	43	julius	`$(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(RTL_SIM_FLAGS); \`
220	22	julius	`echo; \`
221	32	julius	`echo "\t#### Beginning simulation ####"; \`
222	33	julius	`time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \`
223	36	julius	`if [ $$? -gt 0 ]; then exit $$?; fi; \`
224			TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log \| grep report \| grep $(SIM_SUCCESS_MESSAGE) -c`; \
225	33	julius	`echo; echo "\t####"; \`
226	34	julius	`if [ $$TEST_RESULT -gt 0 ]; then \`
227	52	julius	echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
228	32	julius	`else echo "\t#### Test $$TEST FAILED ####";\`
229			`fi; \`
230	33	julius	`echo "\t####"; echo; \`
231	52	julius	TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
232			`done; \`
233			`echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo`
234	33	julius
235
236	52	julius
237	39	julius	`# Use NCSIM instead of icarus`
238			`rtl-nc-tests: prepare_sw prepare_rtl`
239	35	julius	`@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi`
240			`@echo`
241			`@echo "Beginning loop that will complete the following tests: $(TESTS)"`
242			`@echo`
243			`@for TEST in $(TESTS); do \`
244			`echo "################################################################################"; \`
245			`echo; \`
246			`echo "\t#### Current test: $$TEST ####"; echo; \`
247			`echo "\t#### Compiling software ####"; echo; \`
248			CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST \| cut -d "-" -f 1`; \
249			`$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \`
250	45	julius	`rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \`
251			`rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \`
252			`ln -s $$CURRENT_TEST_SW_DIR/$$TEST_twobyte_sizefirst.hex $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \`
253			`ln -s $$CURRENT_TEST_SW_DIR/$$TEST_fourbyte.hex $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \`
254	35	julius	`sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \`
255			`-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \`
256			`-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \`
257			`-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \`
258			`-e \\!^//.*\$$!d -e \\!^\$$!d ; \`
259			`echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
260			`if [ ! -z $$VCD ]; \`
261			`then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
262			`echo "+access+r" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
263			`fi; \`
264	54	julius	`if [ ! -z $$UART_PRINTF ]; \`
265			`then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
266			`fi; \`
267	45	julius	`if [ ! -z $$USE_SDRAM ]; then \`
268			echo "\`define USE_SDRAM" >> $(SIM_RUN_DIR)/test_define.v; \
269			`fi; \`
270	36	julius	`echo "+nocopyright" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
271			`echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
272	35	julius	echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
273			echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
274	39	julius	`if [ -z $$NO_SIM_LOGGING ]; then \`
275			echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
276			`fi; \`
277	35	julius	`echo ; \`
278			`echo "\t#### Beginning simulation ####"; \`
279	36	julius	`time -p ncverilog -f $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated -Q -l $(SIM_RESULTS_DIR)/$$TEST-ius-out.log $(RTL_SIM_FLAGS); \`
280			`if [ $$? -gt 0 ]; then exit $$?; fi; \`
281			TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log \| grep report \| grep $(SIM_SUCCESS_MESSAGE) -c`; \
282	35	julius	`echo; echo "\t####"; \`
283			`if [ $$TEST_RESULT -gt 0 ]; then \`
284	54	julius	echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
285	35	julius	`else echo "\t#### Test $$TEST FAILED ####";\`
286			`fi; \`
287			`echo "\t####"; echo; \`
288	54	julius	TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
289			`done; \`
290			`echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo`
291	33	julius
292	52	julius	`################################################################################`
293			`# Verilator model build rules`
294			`################################################################################`
295	48	julius
296	52	julius
297
298
299			`# List of System C models - use this list to link the sources into the Verilator`
300	50	julius	`# build directory`
301	48	julius	`SYSC_MODELS=OrpsocAccess TraceSC`
302
303	52	julius	`# Only need the trace target if we are tracing`
304			`ifneq (,$(findstring -trace, $(VLT_FLAGS)))`
305			`VLT_TRACEOBJ = SpTraceVcdC`
306			`endif`
307
308	50	julius	`# This is the list of extra models we'll issue make commands for`
309			`# Included is the SystemPerl trace model`
310	52	julius	`SYSC_MODELS_BUILD=$(SYSC_MODELS) $(VLT_TRACEOBJ)`
311	50	julius
312	52	julius	`prepare_vlt: prepare_rtl vlt_model_links $(SIM_VLT_DIR)/Vorpsoc_top`
313
314			`$(SIM_VLT_DIR)/Vorpsoc_top: $(SIM_VLT_DIR)/libVorpsoc_top.a $(SIM_VLT_DIR)/OrpsocMain.o`
315			`# Final linking of the simulation executable. Order of libraries here is important!`
316			`@echo; echo "\tGenerating simulation executable"; echo`
317			`cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o Vorpsoc_top -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/lib-linux64 OrpsocMain.o -lVorpsoc_top -lmodules -lsystemc`
318
319			`$(SIM_VLT_DIR)/OrpsocMain.o:`
320			`# Now compile the top level systemC "testbench" module`
321			`@echo; echo "\tCompiling top level SystemC testbench"; echo`
322	48	julius	`cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp`
323	52	julius
324			`$(SIM_VLT_DIR)/libVorpsoc_top.a: $(SIM_VLT_DIR)/Vorpsoc_top__ALL.a vlt_modules_compile $(SIM_VLT_DIR)/verilated.o`
325	48	julius	`# Now archive all of the libraries from verilator witht he other modules we might have`
326	52	julius	`@echo; echo "\tArchiving libraries into libVorpsoc_top.a"; echo`
327			`@cd $(SIM_VLT_DIR) && \`
328	48	julius	`cp Vorpsoc_top__ALL.a libVorpsoc_top.a && \`
329			`ar rcs libVorpsoc_top.a verilated.o; \`
330	50	julius	`for SYSCMODEL in $(SYSC_MODELS_BUILD); do \`
331	48	julius	`ar rcs libVorpsoc_top.a $$SYSCMODEL.o; \`
332			`done`
333	41	julius
334	52	julius	`$(SIM_VLT_DIR)/verilated.o:`
335			`@echo; echo "\tCompiling verilated.o"; echo`
336			`@cd $(SIM_VLT_DIR) && \`
337			`$(MAKE) -f Vorpsoc_top.mk verilated.o`
338	41	julius
339	52	julius	`.PHONY: vlt_modules_compile`
340			`vlt_modules_compile:`
341			`# Compile the module files`
342			`@echo; echo "\tCompiling SystemC models"`
343			`@cd $(SIM_VLT_DIR) && \`
344			`for SYSCMODEL in $(SYSC_MODELS_BUILD); do \`
345			`echo;echo "\t$$SYSCMODEL"; echo; \`
346			`$(MAKE) -f Vorpsoc_top.mk $$SYSCMODEL.o; \`
347			`done`
348
349			`$(SIM_VLT_DIR)/Vorpsoc_top__ALL.a: $(SIM_VLT_DIR)/Vorpsoc_top.mk`
350			`@echo; echo "\tCompiling main design"; echo`
351			`@cd $(SIM_VLT_DIR) && \`
352			`$(MAKE) -f Vorpsoc_top.mk Vorpsoc_top__ALL.a`
353
354			`$(SIM_VLT_DIR)/Vorpsoc_top.mk: $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated $(SIM_VLT_DIR)/libmodules.a`
355			`# Now call verilator to generate the .mk files`
356	53	julius	`@echo; echo "\tGenerating makefiles with Verilator"; echo`
357	52	julius	`cd $(SIM_VLT_DIR) && \`
358			`verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(VLT_COMMAND_FILE).generated`
359
360	47	julius	`# SystemC modules library`
361			`$(SIM_VLT_DIR)/libmodules.a:`
362	52	julius	`@echo; echo "\tCompiling SystemC modules"; echo`
363			`@$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make`
364	47	julius
365	52	julius
366			`# Verilator command script`
367			`# Generate the compile script to give Verilator`
368			`$(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated:`
369			`@echo; echo "\tGenerating verilator compile script"; echo`
370			`@sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated \`
371			`-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \`
372			`-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \`
373			`-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \`
374			`-e \\!^//.*\$$!d -e \\!^\$$!d;`
375
376			`.PHONY: vlt_model_links`
377			`vlt_model_links:`
378			`# Link all the required system C model files into the verilator work dir`
379			`@echo; echo "\tLinking SystemC model source to verilator build path"; echo`
380			`@if [ ! -d $(SIM_VLT_DIR) ]; then mkdir $(SIM_VLT_DIR); fi`
381			`@cd $(SIM_VLT_DIR) && \`
382			`for SYSCMODEL in $(SYSC_MODELS); do \`
383			`if [ ! -e $$SYSCMODEL.cpp ]; then \`
384			`ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp .; \`
385			`ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h .; \`
386			`fi; \`
387			`done`
388
389	53	julius
390	52	julius	`################################################################################`
391	53	julius	`# Verilator test loop`
392			`################################################################################`
393
394			`# Verilator defaults to internal memories`
395			`vlt-tests: prepare_sw_uart_printf prepare_rtl prepare_vlt`
396			`@echo`
397			`@echo "Beginning loop that will complete the following tests: $(TESTS)"`
398			`@echo`
399			`@for TEST in $(TESTS); do \`
400			`echo "################################################################################"; \`
401			`echo; \`
402			`echo "\t#### Current test: $$TEST ####"; echo; \`
403			`echo "\t#### Compiling software ####"; echo; \`
404			CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST \| cut -d "-" -f 1`; \
405			`$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \`
406			`rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \`
407			`ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \`
408			`echo "\t#### Beginning simulation ####"; \`
409			`time -p $(SIM_VLT_DIR)/Vorpsoc_top; \`
410			`if [ $$? -gt 0 ]; then exit $$?; fi; \`
411			`TEST_RESULT=1; \`
412			`echo; echo "\t####"; \`
413			`if [ $$TEST_RESULT -gt 0 ]; then \`
414			echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
415			`else echo "\t#### Test $$TEST FAILED ####";\`
416			`fi; \`
417			`echo "\t####"; echo; \`
418			TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
419			`done; \`
420			`echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo`
421
422
423			`################################################################################`
424	52	julius	`# Cleaning rules`
425			`################################################################################`
426
427	22	julius	`clean-sw:`
428			`@for TEST in $(TESTS); do \`
429			`echo "Current test: $$TEST"; \`
430			CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST \| cut -d "-" -f 1`; \
431			`echo "Current test sw directory: " $$CURRENT_TEST_SW_DIR; \`
432			`$(MAKE) -C $$CURRENT_TEST_SW_DIR clean; \`
433			`done`
434	31	julius	`$(MAKE) -C $(SW_DIR)/support clean`
435			`$(MAKE) -C $(SW_DIR)/utils clean`
436
437			`clean-sim:`
438	52	julius	`rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/. $(SIM_VLT_DIR)`

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