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julius |
######################################################################
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#### ####
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#### ORPSoCv2 Testbenches Makefile ####
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#### ####
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#### Description ####
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#### ORPSoCv2 Testbenches Makefile, containing rules for ####
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#### configuring and running different tests on the current ####
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#### ORPSoC design. ####
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#### ####
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#### To Do: ####
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#### - Verilator tests ####
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#### ####
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#### Author(s): ####
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#### - jb, jb@orsoc.se ####
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#### ####
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#### ####
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######################################################################
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#### ####
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#### Copyright (C) 2009 Authors and OPENCORES.ORG ####
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#### ####
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#### This source file may be used and distributed without ####
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#### restriction provided that this copyright statement is not ####
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#### removed from the file and that any derivative work contains ####
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#### the original copyright notice and the associated disclaimer. ####
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#### ####
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#### This source file is free software; you can redistribute it ####
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#### and/or modify it under the terms of the GNU Lesser General ####
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#### Public License as published by the Free Software Foundation; ####
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#### either version 2.1 of the License, or (at your option) any ####
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#### later version. ####
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#### ####
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#### This source is distributed in the hope that it will be ####
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#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
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#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
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#### PURPOSE. See the GNU Lesser General Public License for more ####
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#### details. ####
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#### ####
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#### You should have received a copy of the GNU Lesser General ####
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#### Public License along with this source; if not, download it ####
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#### from http://www.opencores.org/lgpl.shtml ####
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#### ####
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######################################################################
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22 |
julius |
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55 |
julius |
# Usage:
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#
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# make rtl-tests
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#
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# Run the software tests in the RTL model of the ORPSoC being
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# simulated with an event-driven simulator like Icarus. Also
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# possible to use Cadence's Verilog simulators with the
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# "rtl-nc-tests" target.
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#
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# make vlt-tests
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#
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# Run all the software tests in the RTL model which has been
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# converted into a cycle-accurate SystemC model with Verilator.
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#
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39 |
julius |
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55 |
julius |
# Simulation results:
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#
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# The results and output of the event-driven simulations are in the
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# results path, in parallel to the simulation run and bin paths.
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julius |
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julius |
# Specific tests:
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#
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julius |
# To run an individual test, specify it in the variable TESTS when
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julius |
# calling make, eg:
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#
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# make rtl-tests TESTS="mmu-nocache mul-idcd-O2"
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39 |
julius |
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55 |
julius |
# UART printf:
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#
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# It is possible to enable printf to the console via the UART when
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# running the event-driven simulators. To do this define UART_PRINTF=1
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# when calling make. The SystemC cycle-acccurate model uses this by
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# default.
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# VCDs:
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#
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julius |
# VCD (value change dumps, usable in a waveform viewer, such as gtkwave
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# to inspect the internals of the system graphically) files can be
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julius |
# generated by defining a variable VCD, eg.
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#
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# make rtl-tests VCD=1
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#
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# and a dump file will be created in the simulation results directory,
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# and named according to the test run which generated it. This is
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# possible for both event-driven and cycle-accurate simulations.
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# However the cycle-accurate
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julius |
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# The rtl simulations can also be run with Cadences NCSim by using
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# rtl-nc-tests in the place of rtl-tests.
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# It is possible to speed up the simulation slightly by disabling
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# log output of the processor's state to files by defining
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# NO_SIM_LOGGING, eg. make rtl-tests TESTS=except-icdc NO_SIM_LOGGING=1
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# Name of the directory we're currently in
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julius |
CUR_DIR=$(shell pwd)
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39 |
julius |
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# The root path of the whole project
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julius |
PROJECT_ROOT=$(CUR_DIR)/../..
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julius |
# Tests is only defined if it wasn't already defined when make was called
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# This is the default list of every test that is currently possible
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julius |
TESTS ?= basic-nocache cbasic-nocache-O2 dhry-nocache-O2 except-nocache mmu-nocache mul-nocache-O2 syscall-nocache tick-nocache uart-nocache basic-icdc cbasic-icdc-O2 dhry-icdc-O2 except-icdc mmu-icdc mul-icdc-O2 syscall-icdc tick-icdc uart-icdc
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julius |
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julius |
# Paths to other important parts of this test suite
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julius |
SIM_DIR=$(PROJECT_ROOT)/sim
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SIM_RUN_DIR=$(SIM_DIR)/run
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SIM_BIN_DIR=$(SIM_DIR)/bin
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SIM_RESULTS_DIR=$(SIM_DIR)/results
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julius |
SIM_VLT_DIR=$(SIM_DIR)/vlt
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julius |
BENCH_DIR=$(PROJECT_ROOT)/bench
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BACKEND_DIR=$(PROJECT_ROOT)/backend
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BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
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julius |
BENCH_SYSC_DIR=$(BENCH_DIR)/sysc
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julius |
BENCH_SYSC_SRC_DIR=$(BENCH_SYSC_DIR)/src
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BENCH_SYSC_INCLUDE_DIR=$(BENCH_SYSC_DIR)/include
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julius |
RTL_VERILOG_DIR=$(PROJECT_ROOT)/rtl/verilog
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SW_DIR=$(PROJECT_ROOT)/sw
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ICARUS=iverilog
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ICARUS_VVP=vvp
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ICARUS_COMMAND_FILE=icarus.scr
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julius |
VLT_COMMAND_FILE=verilator.scr
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julius |
SIM_SUCCESS_MESSAGE=deaddead
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julius |
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julius |
ARCH_SIM_EXE=or32-elf-sim
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ARCH_SIM_CFG_FILE=or1ksim-orpsocv2.cfg
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julius |
# If USE_SDRAM is defined we'll add it to the simulator's defines on the
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# command line becuase it's used by many different modules and it's easier
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# to do it this way than make them all include a file.
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ifdef USE_SDRAM
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RTL_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)"
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endif
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SIM_FLASH_MEM_FILE="flash.in"
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FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"
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SIM_SRAM_MEM_FILE="sram.vmem"
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julius |
TESTS_PASSED=0
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TESTS_PERFORMED=0;
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################################################################################
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# Event-driven simulator build rules (Icarus, NCSim)
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################################################################################
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julius |
.PHONY: prepare_rtl
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prepare_rtl:
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julius |
@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
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julius |
@cd $(RTL_VERILOG_DIR) && sed '/defparam/!s/\([a-zA-Z0-9_]\)\.//g' intercon.vm > intercon.v
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julius |
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julius |
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ifdef UART_PRINTF
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TEST_SW_MAKE_OPTS=UART_PRINTF=1
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endif
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julius |
.PHONY: prepare_sw
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prepare_sw:
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julius |
@$(MAKE) -C $(SW_DIR)/support all $(TEST_SW_MAKE_OPTS)
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@$(MAKE) -C $(SW_DIR)/utils all
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julius |
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julius |
# A rule with UART_PRINTF hard defined ... used by verilator make sw
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julius |
prepare_sw_uart_printf:
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@$(MAKE) -C $(SW_DIR)/support all UART_PRINTF=1 $(TEST_SW_MAKE_OPTS)
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@$(MAKE) -C $(SW_DIR)/utils all
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julius |
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julius |
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julius |
# Rough guide to how these tests work:
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# First, the couple of custom, required, software tools under sw/utils are
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# compiled, and then the software library files.
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# Next the few verilog files that need preperation are taken care of.
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# The test begins by starting a loop in bash using on the strings defined in
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# TESTS. Each one corresponds to a certain module of software for the OpenRISC
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# that is included in this test suite. Under the sw/ path is a set of paths,
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julius |
# and all except the support/ and utils/ paths contain code which is run to
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# test the OR1k used in this test suite. For each of these software modules,
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# it is possible that different tests are done using the same module. These
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# tests can vary by either using different levels of optimisation during
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# compilation, and/or by having the OR1k's caches enabled or disabled.
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julius |
# Each test has a unique name, and under the $(SIM_RESULTS_DIR), which is
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# usually just ../results, log files, and optionally VCD files, are created for
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# inspection later and are named according to the test. Inspect the file
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julius |
# bench/verilog/or1200_monitor.v to find out in detail what each log consists
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# of.
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julius |
# For each test, a few things occur. First the software that will run inside
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julius |
# the simulated OR1k system is compiled, converted to a format which can be
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# read
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julius |
# into the flash memory model via $readmemh() and linked to the sim/run
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julius |
# directory as $(SIM_FLASH_MEM_FILE), which currently is flash.in. Next a
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# compilation script for icarus is generated, containing a list of all the
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# RTL files and include directories. Next, an include file for the verilog
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# testbench is generated, containing a string of the name of the current
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# test, path to the results directory (for VCD generation) and any other
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# things which might vary from test to test. This is not done by +define
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# lines in the icarus script because of string handling incosistencies
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# between different simulators and shells.
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# Once all the files are generated, icarus is called to compile the rtl
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# design, and then run it. Each of the tested software modules have code which
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# will trigger the simulation to be stopped by use of the l.nop instruction
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# with an immediate value of 1. When the simulation finishes, the simulation
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# executable exits and the log of the simulation is inspected for the expected
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# output. Currently, the string "deaddead" indicates that the software
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# completed successfully. This is counted as the ORPSoC "passing" the test. In
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# fact, whether the system did the right thing or not requires more
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# inspection, but roughly this is a good indicator that nothing major went
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# wrong.
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julius |
# Once the current test is finished, the next begins with the compilation of its
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# software and linking of the resulting hex file to the run path, etc.
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julius |
# Main RAM setup - (RTL simulation with Icarus/NCSim only!):
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# Define USE_SDRAM to enable the external SDRAM, otherwise the simulation
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# defaults to an internal SRAM. Eg. $ make rtl-tests USE_SDRAM=1 VCD=1
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# Verilator defaults to internal memories
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julius |
rtl-tests: prepare_sw prepare_rtl
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julius |
@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
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julius |
@echo
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@echo "Beginning loop that will complete the following tests: $(TESTS)"
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@echo
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julius |
@for TEST in $(TESTS); do \
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julius |
echo "################################################################################"; \
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echo; \
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echo "\t#### Current test: $$TEST ####"; echo; \
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julius |
echo "\t#### Compiling software ####"; echo; \
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julius |
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
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julius |
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS); \
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julius |
rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
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rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
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ln -s $$CURRENT_TEST_SW_DIR/$$TEST$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
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ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
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julius |
sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
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-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
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-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
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-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
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-e \\!^//.*\$$!d -e \\!^\$$!d ; \
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julius |
echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
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julius |
if [ ! -z $$VCD ]; \
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then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
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fi; \
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julius |
if [ ! -z $$UART_PRINTF ]; \
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then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
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fi; \
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julius |
echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
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echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
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julius |
if [ -z $$NO_SIM_LOGGING ]; then \
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echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
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fi; \
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22 |
julius |
echo ; \
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julius |
echo "\t#### Compiling RTL ####"; \
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22 |
julius |
rm -f $(SIM_RUN_DIR)/a.out; \
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43 |
julius |
$(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(RTL_SIM_FLAGS); \
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julius |
echo; \
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32 |
julius |
echo "\t#### Beginning simulation ####"; \
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julius |
time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \
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julius |
if [ $$? -gt 0 ]; then exit $$?; fi; \
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TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
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julius |
echo; echo "\t####"; \
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34 |
julius |
if [ $$TEST_RESULT -gt 0 ]; then \
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julius |
echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
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julius |
else echo "\t#### Test $$TEST FAILED ####";\
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fi; \
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julius |
echo "\t####"; echo; \
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52 |
julius |
TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
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done; \
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echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
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33 |
julius |
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52 |
julius |
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39 |
julius |
# Use NCSIM instead of icarus
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rtl-nc-tests: prepare_sw prepare_rtl
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35 |
julius |
@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
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@echo
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@echo "Beginning loop that will complete the following tests: $(TESTS)"
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@echo
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@for TEST in $(TESTS); do \
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echo "################################################################################"; \
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echo; \
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|
|
echo "\t#### Current test: $$TEST ####"; echo; \
|
| 280 |
|
|
echo "\t#### Compiling software ####"; echo; \
|
| 281 |
|
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
| 282 |
|
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
|
| 283 |
45 |
julius |
rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
| 284 |
|
|
rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
| 285 |
|
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST_twobyte_sizefirst.hex $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
| 286 |
|
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST_fourbyte.hex $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
| 287 |
35 |
julius |
sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
|
| 288 |
|
|
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
|
| 289 |
|
|
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
|
| 290 |
|
|
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
| 291 |
|
|
-e \\!^//.*\$$!d -e \\!^\$$!d ; \
|
| 292 |
|
|
echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
| 293 |
|
|
if [ ! -z $$VCD ]; \
|
| 294 |
|
|
then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
| 295 |
|
|
echo "+access+r" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
| 296 |
|
|
fi; \
|
| 297 |
54 |
julius |
if [ ! -z $$UART_PRINTF ]; \
|
| 298 |
|
|
then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
| 299 |
|
|
fi; \
|
| 300 |
45 |
julius |
if [ ! -z $$USE_SDRAM ]; then \
|
| 301 |
|
|
echo "\`define USE_SDRAM" >> $(SIM_RUN_DIR)/test_define.v; \
|
| 302 |
|
|
fi; \
|
| 303 |
36 |
julius |
echo "+nocopyright" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
| 304 |
|
|
echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
|
| 305 |
35 |
julius |
echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
|
| 306 |
|
|
echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
|
| 307 |
39 |
julius |
if [ -z $$NO_SIM_LOGGING ]; then \
|
| 308 |
|
|
echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
|
| 309 |
|
|
fi; \
|
| 310 |
35 |
julius |
echo ; \
|
| 311 |
|
|
echo "\t#### Beginning simulation ####"; \
|
| 312 |
36 |
julius |
time -p ncverilog -f $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated -Q -l $(SIM_RESULTS_DIR)/$$TEST-ius-out.log $(RTL_SIM_FLAGS); \
|
| 313 |
|
|
if [ $$? -gt 0 ]; then exit $$?; fi; \
|
| 314 |
|
|
TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
|
| 315 |
35 |
julius |
echo; echo "\t####"; \
|
| 316 |
|
|
if [ $$TEST_RESULT -gt 0 ]; then \
|
| 317 |
54 |
julius |
echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
|
| 318 |
35 |
julius |
else echo "\t#### Test $$TEST FAILED ####";\
|
| 319 |
|
|
fi; \
|
| 320 |
|
|
echo "\t####"; echo; \
|
| 321 |
54 |
julius |
TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
|
| 322 |
|
|
done; \
|
| 323 |
|
|
echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
|
| 324 |
33 |
julius |
|
| 325 |
52 |
julius |
################################################################################
|
| 326 |
|
|
# Verilator model build rules
|
| 327 |
|
|
################################################################################
|
| 328 |
48 |
julius |
|
| 329 |
52 |
julius |
|
| 330 |
|
|
|
| 331 |
|
|
|
| 332 |
|
|
# List of System C models - use this list to link the sources into the Verilator
|
| 333 |
50 |
julius |
# build directory
|
| 334 |
48 |
julius |
SYSC_MODELS=OrpsocAccess TraceSC
|
| 335 |
|
|
|
| 336 |
55 |
julius |
ifdef VCD
|
| 337 |
|
|
VLT_FLAGS +=-trace
|
| 338 |
|
|
endif
|
| 339 |
|
|
|
| 340 |
52 |
julius |
# Only need the trace target if we are tracing
|
| 341 |
|
|
ifneq (,$(findstring -trace, $(VLT_FLAGS)))
|
| 342 |
|
|
VLT_TRACEOBJ = SpTraceVcdC
|
| 343 |
|
|
endif
|
| 344 |
|
|
|
| 345 |
50 |
julius |
# This is the list of extra models we'll issue make commands for
|
| 346 |
|
|
# Included is the SystemPerl trace model
|
| 347 |
52 |
julius |
SYSC_MODELS_BUILD=$(SYSC_MODELS) $(VLT_TRACEOBJ)
|
| 348 |
50 |
julius |
|
| 349 |
52 |
julius |
prepare_vlt: prepare_rtl vlt_model_links $(SIM_VLT_DIR)/Vorpsoc_top
|
| 350 |
|
|
|
| 351 |
|
|
$(SIM_VLT_DIR)/Vorpsoc_top: $(SIM_VLT_DIR)/libVorpsoc_top.a $(SIM_VLT_DIR)/OrpsocMain.o
|
| 352 |
|
|
# Final linking of the simulation executable. Order of libraries here is important!
|
| 353 |
|
|
@echo; echo "\tGenerating simulation executable"; echo
|
| 354 |
|
|
cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o Vorpsoc_top -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/lib-linux64 OrpsocMain.o -lVorpsoc_top -lmodules -lsystemc
|
| 355 |
|
|
|
| 356 |
|
|
$(SIM_VLT_DIR)/OrpsocMain.o:
|
| 357 |
|
|
# Now compile the top level systemC "testbench" module
|
| 358 |
|
|
@echo; echo "\tCompiling top level SystemC testbench"; echo
|
| 359 |
48 |
julius |
cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
|
| 360 |
52 |
julius |
|
| 361 |
|
|
$(SIM_VLT_DIR)/libVorpsoc_top.a: $(SIM_VLT_DIR)/Vorpsoc_top__ALL.a vlt_modules_compile $(SIM_VLT_DIR)/verilated.o
|
| 362 |
48 |
julius |
# Now archive all of the libraries from verilator witht he other modules we might have
|
| 363 |
52 |
julius |
@echo; echo "\tArchiving libraries into libVorpsoc_top.a"; echo
|
| 364 |
|
|
@cd $(SIM_VLT_DIR) && \
|
| 365 |
48 |
julius |
cp Vorpsoc_top__ALL.a libVorpsoc_top.a && \
|
| 366 |
|
|
ar rcs libVorpsoc_top.a verilated.o; \
|
| 367 |
50 |
julius |
for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
|
| 368 |
48 |
julius |
ar rcs libVorpsoc_top.a $$SYSCMODEL.o; \
|
| 369 |
|
|
done
|
| 370 |
41 |
julius |
|
| 371 |
52 |
julius |
$(SIM_VLT_DIR)/verilated.o:
|
| 372 |
|
|
@echo; echo "\tCompiling verilated.o"; echo
|
| 373 |
|
|
@cd $(SIM_VLT_DIR) && \
|
| 374 |
|
|
$(MAKE) -f Vorpsoc_top.mk verilated.o
|
| 375 |
41 |
julius |
|
| 376 |
52 |
julius |
.PHONY: vlt_modules_compile
|
| 377 |
|
|
vlt_modules_compile:
|
| 378 |
|
|
# Compile the module files
|
| 379 |
|
|
@echo; echo "\tCompiling SystemC models"
|
| 380 |
|
|
@cd $(SIM_VLT_DIR) && \
|
| 381 |
|
|
for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
|
| 382 |
|
|
echo;echo "\t$$SYSCMODEL"; echo; \
|
| 383 |
|
|
$(MAKE) -f Vorpsoc_top.mk $$SYSCMODEL.o; \
|
| 384 |
|
|
done
|
| 385 |
|
|
|
| 386 |
|
|
$(SIM_VLT_DIR)/Vorpsoc_top__ALL.a: $(SIM_VLT_DIR)/Vorpsoc_top.mk
|
| 387 |
|
|
@echo; echo "\tCompiling main design"; echo
|
| 388 |
|
|
@cd $(SIM_VLT_DIR) && \
|
| 389 |
|
|
$(MAKE) -f Vorpsoc_top.mk Vorpsoc_top__ALL.a
|
| 390 |
|
|
|
| 391 |
|
|
$(SIM_VLT_DIR)/Vorpsoc_top.mk: $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated $(SIM_VLT_DIR)/libmodules.a
|
| 392 |
|
|
# Now call verilator to generate the .mk files
|
| 393 |
53 |
julius |
@echo; echo "\tGenerating makefiles with Verilator"; echo
|
| 394 |
52 |
julius |
cd $(SIM_VLT_DIR) && \
|
| 395 |
|
|
verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(VLT_COMMAND_FILE).generated
|
| 396 |
|
|
|
| 397 |
47 |
julius |
# SystemC modules library
|
| 398 |
|
|
$(SIM_VLT_DIR)/libmodules.a:
|
| 399 |
52 |
julius |
@echo; echo "\tCompiling SystemC modules"; echo
|
| 400 |
|
|
@$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make
|
| 401 |
47 |
julius |
|
| 402 |
52 |
julius |
|
| 403 |
|
|
# Verilator command script
|
| 404 |
|
|
# Generate the compile script to give Verilator
|
| 405 |
|
|
$(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated:
|
| 406 |
|
|
@echo; echo "\tGenerating verilator compile script"; echo
|
| 407 |
|
|
@sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated \
|
| 408 |
|
|
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
|
| 409 |
|
|
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
|
| 410 |
|
|
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
| 411 |
|
|
-e \\!^//.*\$$!d -e \\!^\$$!d;
|
| 412 |
|
|
|
| 413 |
|
|
.PHONY: vlt_model_links
|
| 414 |
|
|
vlt_model_links:
|
| 415 |
|
|
# Link all the required system C model files into the verilator work dir
|
| 416 |
|
|
@echo; echo "\tLinking SystemC model source to verilator build path"; echo
|
| 417 |
|
|
@if [ ! -d $(SIM_VLT_DIR) ]; then mkdir $(SIM_VLT_DIR); fi
|
| 418 |
|
|
@cd $(SIM_VLT_DIR) && \
|
| 419 |
|
|
for SYSCMODEL in $(SYSC_MODELS); do \
|
| 420 |
|
|
if [ ! -e $$SYSCMODEL.cpp ]; then \
|
| 421 |
|
|
ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp .; \
|
| 422 |
|
|
ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h .; \
|
| 423 |
|
|
fi; \
|
| 424 |
|
|
done
|
| 425 |
|
|
|
| 426 |
53 |
julius |
|
| 427 |
52 |
julius |
################################################################################
|
| 428 |
53 |
julius |
# Verilator test loop
|
| 429 |
|
|
################################################################################
|
| 430 |
|
|
|
| 431 |
|
|
# Verilator defaults to internal memories
|
| 432 |
|
|
vlt-tests: prepare_sw_uart_printf prepare_rtl prepare_vlt
|
| 433 |
56 |
julius |
@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
|
| 434 |
53 |
julius |
@echo
|
| 435 |
|
|
@echo "Beginning loop that will complete the following tests: $(TESTS)"
|
| 436 |
|
|
@echo
|
| 437 |
|
|
@for TEST in $(TESTS); do \
|
| 438 |
|
|
echo "################################################################################"; \
|
| 439 |
|
|
echo; \
|
| 440 |
|
|
echo "\t#### Current test: $$TEST ####"; echo; \
|
| 441 |
|
|
echo "\t#### Compiling software ####"; echo; \
|
| 442 |
|
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
| 443 |
|
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \
|
| 444 |
|
|
rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
| 445 |
|
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
| 446 |
|
|
echo "\t#### Beginning simulation ####"; \
|
| 447 |
55 |
julius |
time -p $(SIM_VLT_DIR)/Vorpsoc_top $$TEST; \
|
| 448 |
53 |
julius |
if [ $$? -gt 0 ]; then exit $$?; fi; \
|
| 449 |
|
|
TEST_RESULT=1; \
|
| 450 |
|
|
echo; echo "\t####"; \
|
| 451 |
|
|
if [ $$TEST_RESULT -gt 0 ]; then \
|
| 452 |
|
|
echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
|
| 453 |
|
|
else echo "\t#### Test $$TEST FAILED ####";\
|
| 454 |
|
|
fi; \
|
| 455 |
|
|
echo "\t####"; echo; \
|
| 456 |
|
|
TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
|
| 457 |
|
|
done; \
|
| 458 |
|
|
echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
|
| 459 |
|
|
|
| 460 |
|
|
|
| 461 |
56 |
julius |
|
| 462 |
53 |
julius |
################################################################################
|
| 463 |
56 |
julius |
# Architectural simulator test loop
|
| 464 |
|
|
################################################################################
|
| 465 |
|
|
|
| 466 |
|
|
# Verilator defaults to internal memories
|
| 467 |
|
|
sim-tests: prepare_sw_uart_printf
|
| 468 |
|
|
@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
|
| 469 |
|
|
@echo
|
| 470 |
|
|
@echo "Beginning loop that will complete the following tests: $(TESTS)"
|
| 471 |
|
|
@echo
|
| 472 |
|
|
@for TEST in $(TESTS); do \
|
| 473 |
|
|
echo "################################################################################"; \
|
| 474 |
|
|
echo; \
|
| 475 |
|
|
echo "\t#### Current test: $$TEST ####"; echo; \
|
| 476 |
|
|
echo "\t#### Compiling software ####"; echo; \
|
| 477 |
|
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
| 478 |
|
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \
|
| 479 |
|
|
rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
| 480 |
|
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.or32 $(SIM_RUN_DIR)/.; \
|
| 481 |
|
|
echo;echo "\t#### Launching architectural simulator ####"; \
|
| 482 |
|
|
time -p $(ARCH_SIM_EXE) --nosrv -f $(SIM_BIN_DIR)/$(ARCH_SIM_CFG_FILE) $$TEST.or32 > $(SIM_RESULTS_DIR)/$$TEST-or1ksim.log 2>&1; \
|
| 483 |
|
|
if [ $$? -gt 0 ]; then exit $$?; fi; \
|
| 484 |
|
|
if [ `tail -n 10 $(SIM_RESULTS_DIR)/$$TEST-or1ksim.log | grep -c $(SIM_SUCCESS_MESSAGE)` -gt 0 ]; then \
|
| 485 |
|
|
TEST_RESULT=1; \
|
| 486 |
|
|
fi; \
|
| 487 |
|
|
echo; echo "\t####"; \
|
| 488 |
|
|
if [ $$TEST_RESULT -gt 0 ]; then \
|
| 489 |
|
|
echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
|
| 490 |
|
|
else echo "\t#### Test $$TEST FAILED ####";\
|
| 491 |
|
|
fi; \
|
| 492 |
|
|
echo "\t####"; echo; \
|
| 493 |
|
|
TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
|
| 494 |
|
|
unlink $(SIM_RUN_DIR)/$$TEST.or32; \
|
| 495 |
|
|
done; \
|
| 496 |
|
|
echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
|
| 497 |
|
|
|
| 498 |
|
|
|
| 499 |
|
|
|
| 500 |
|
|
################################################################################
|
| 501 |
52 |
julius |
# Cleaning rules
|
| 502 |
|
|
################################################################################
|
| 503 |
|
|
|
| 504 |
22 |
julius |
clean-sw:
|
| 505 |
|
|
@for TEST in $(TESTS); do \
|
| 506 |
|
|
echo "Current test: $$TEST"; \
|
| 507 |
|
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
| 508 |
|
|
echo "Current test sw directory: " $$CURRENT_TEST_SW_DIR; \
|
| 509 |
|
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR clean; \
|
| 510 |
|
|
done
|
| 511 |
31 |
julius |
$(MAKE) -C $(SW_DIR)/support clean
|
| 512 |
|
|
$(MAKE) -C $(SW_DIR)/utils clean
|
| 513 |
|
|
|
| 514 |
|
|
clean-sim:
|
| 515 |
52 |
julius |
rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.* $(SIM_VLT_DIR)
|
