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######################################################################
####                                                              ####
####  ORPSoCv2 Testbenches Makefile                               ####
####                                                              ####
####  Description                                                 ####
####  ORPSoCv2 Testbenches Makefile, containing rules for         ####
####  configuring and running different tests on the current      ####
####  ORPSoC(v2) design.                                          ####
####                                                              ####
####  To Do:                                                      ####
####    * Arrange verilator make rules so that the whole thing    ####
####      isn't recompiled when a single SystemC module is        ####
####      updated.                                                ####
####    * Test if each software test file gets made properly      ####
####    * Expand software test-suite (uClibc, ecos tests, LTP?)   ####
####                                                              ####
####  Author(s):                                                  ####
####      - jb, jb@orsoc.se                                       ####
####                                                              ####
####                                                              ####
######################################################################
####                                                              ####
#### Copyright (C) 2009 Authors and OPENCORES.ORG                 ####
####                                                              ####
#### This source file may be used and distributed without         ####
#### restriction provided that this copyright statement is not    ####
#### removed from the file and that any derivative work contains  ####
#### the original copyright notice and the associated disclaimer. ####
####                                                              ####
#### This source file is free software; you can redistribute it   ####
#### and/or modify it under the terms of the GNU Lesser General   ####
#### Public License as published by the Free Software Foundation; ####
#### either version 2.1 of the License, or (at your option) any   ####
#### later version.                                               ####
####                                                              ####
#### This source is distributed in the hope that it will be       ####
#### useful, but WITHOUT ANY WARRANTY; without even the implied   ####
#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ####
#### PURPOSE.  See the GNU Lesser General Public License for more ####
#### details.                                                     ####
####                                                              ####
#### You should have received a copy of the GNU Lesser General    ####
#### Public License along with this source; if not, download it   ####
#### from http://www.opencores.org/lgpl.shtml                     ####
####                                                              ####
######################################################################
 
# Usage:
#
#       make rtl-tests
#
#       Run the software tests in the RTL model of the ORPSoC being
#       simulated with an event-driven simulator like Icarus. Also
#       possible to use Cadence's Verilog simulators with the
#       "rtl-nc-tests" target.
#
#       make vlt-tests
#
#       Run all the software tests in the RTL model which has been
#       converted into a cycle-accurate SystemC model with Verilator.
#
#       make sim-tests
#
#       Run all the software tests in the architectural simulator
#
 
# Simulation results:
#
# The results and output of the event-driven simulations are in the
# results path, in parallel to the simulation run and bin paths.
 
# Specific tests:
#
# To run an individual test, specify it in the variable TESTS when
# calling make, eg:
#
#        make rtl-tests TESTS="mmu-nocache mul-idcd-O2"
 
# UART printf:
#
# It is possible to enable printf to the console via the UART when
# running the event-driven simulators. To do this define UART_PRINTF=1
# when calling make. The SystemC cycle-acccurate model uses this by
# default.
# Also note when switching between runs with and without UART printf
# enabled, run a clean-sw so the library files are recompiled when
# the tests are run - this is not done automatically.
 
# VCDs:
#
# VCD (value change dumps, usable in a waveform viewer, such as gtkwave
# to inspect the internals of the system graphically) files can be
# generated by defining a variable VCD, eg.
#
#       make rtl-tests VCD=1
#
# and a dump file will be created in the simulation results directory,
# and named according to the test run which generated it. This is
# possible for both event-driven and cycle-accurate simulations.
# However the cycle-accurate
 
# NO_SIM_LOGGING:
#
# It is possible to speed up the event-driven simulation slightly by
# disabling log output of the processor's state to files by defining
# NO_SIM_LOGGING, eg:
#
#       make rtl-tests TESTS=except-icdc NO_SIM_LOGGING=1
#
 
# Cleaning:
# A simple "make clean" cleans everything - software and all temporary
# simulation files and directories. To clean just the software run:
#
#       make clean-sw
#
# and to clean just the temporary simulation files (including VCDs,
# results logs - everything under, and including, sim/results/, run
#
#       make clean-sim
#
 
# Note:
#
# The way each of the test loops is written is probably a bit overly complex
# but this is to save maintaining and calling other files to get this done.
#
 
# Name of the directory we're currently in
CUR_DIR=$(shell pwd)
 
# The root path of the whole project
PROJECT_ROOT=$(CUR_DIR)/../..
 
# Tests is only defined if it wasn't already defined when make was called
# This is the default list of every test that is currently possible
TESTS ?= basic-nocache cbasic-nocache-O2 dhry-nocache-O2 except-nocache mmu-nocache mul-nocache-O2 syscall-nocache tick-nocache uart-nocache basic-icdc cbasic-icdc-O2 dhry-icdc-O2 except-icdc mmu-icdc mul-icdc-O2 syscall-icdc tick-icdc uart-icdc
 
# Paths to other important parts of this test suite
SIM_DIR=$(PROJECT_ROOT)/sim
SIM_RUN_DIR=$(SIM_DIR)/run
SIM_BIN_DIR=$(SIM_DIR)/bin
SIM_RESULTS_DIR=$(SIM_DIR)/results
SIM_VLT_DIR=$(SIM_DIR)/vlt
BENCH_DIR=$(PROJECT_ROOT)/bench
BACKEND_DIR=$(PROJECT_ROOT)/backend
BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
BENCH_SYSC_DIR=$(BENCH_DIR)/sysc
BENCH_SYSC_SRC_DIR=$(BENCH_SYSC_DIR)/src
BENCH_SYSC_INCLUDE_DIR=$(BENCH_SYSC_DIR)/include
RTL_VERILOG_DIR=$(PROJECT_ROOT)/rtl/verilog
SW_DIR=$(PROJECT_ROOT)/sw
 
ICARUS=iverilog
ICARUS_VVP=vvp
ICARUS_COMMAND_FILE=icarus.scr
VLT_COMMAND_FILE=verilator.scr
SIM_SUCCESS_MESSAGE=deaddead
 
ARCH_SIM_EXE=or32-elf-sim
ARCH_SIM_CFG_FILE=or1ksim-orpsocv2.cfg
 
# If USE_SDRAM is defined we'll add it to the simulator's defines on the
# command line becuase it's used by many different modules and it's easier
# to do it this way than make them all include a file.
ifdef USE_SDRAM
RTL_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)"
endif
SIM_FLASH_MEM_FILE="flash.in"
FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"
SIM_SRAM_MEM_FILE="sram.vmem"
 
TESTS_PASSED=0
TESTS_PERFORMED=0;
 
################################################################################
# Event-driven simulator build rules (Icarus, NCSim)
################################################################################
 
.PHONY: prepare_rtl
prepare_rtl:
        @cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
        @cd $(RTL_VERILOG_DIR) && sed '/defparam/!s/\([a-zA-Z0-9_]\)\.//g' intercon.vm > intercon.v
 
 
ifdef UART_PRINTF
TEST_SW_MAKE_OPTS=UART_PRINTF=1
endif
 
.PHONY: prepare_sw
prepare_sw:
        @$(MAKE) -C $(SW_DIR)/support all $(TEST_SW_MAKE_OPTS)
        @$(MAKE) -C $(SW_DIR)/utils all
 
# A rule with UART_PRINTF hard defined ... used by verilator make sw
prepare_sw_uart_printf:
        @$(MAKE) -C $(SW_DIR)/support all UART_PRINTF=1 $(TEST_SW_MAKE_OPTS)
        @$(MAKE) -C $(SW_DIR)/utils all
 
 
# Rough guide to how these tests work:
# First, the couple of custom, required, software tools under sw/utils are
# compiled, and then the software library files.
# Next the few verilog files that need preperation are taken care of.
# The test begins by starting a loop in bash using on the strings defined in
# TESTS. Each one corresponds to a certain module of software for the OpenRISC
# that is included in this test suite. Under the sw/ path is a set of paths,
# and all except the support/ and utils/ paths contain code which is run to
# test the OR1k used in this test suite. For each of these software modules,
# it is possible that different tests are done using the same module. These
# tests can vary by either using different levels of optimisation during
# compilation, and/or by having the OR1k's caches enabled or disabled.
# Each test has a unique name, and under the $(SIM_RESULTS_DIR), which is
# usually just ../results, log files, and optionally VCD files, are created for
# inspection later and are named according to the test. Inspect the file
# bench/verilog/or1200_monitor.v to find out in detail what each log consists
# of.
# For each test, a few things occur. First the software that will run inside
# the simulated OR1k system is compiled, converted to a format which can be
# read
# into the flash memory model via $readmemh() and linked to the sim/run
# directory as $(SIM_FLASH_MEM_FILE), which currently is flash.in. Next a
# compilation script for icarus is generated, containing a list of all the
# RTL files and include directories. Next, an include file for the verilog
# testbench is generated, containing a string of the name of the current
# test, path to the results directory (for VCD generation) and any other
# things which might vary from test to test. This is not done by +define
# lines in the icarus script because of string handling incosistencies
# between different simulators and shells.
# Once all the files are generated, icarus is called to compile the rtl
# design, and then run it. Each of the tested software modules have code which
# will trigger the simulation to be stopped by use of the l.nop instruction
# with an immediate value of 1. When the simulation finishes, the simulation
# executable exits and the log of the simulation is inspected for the expected
# output. Currently, the string "deaddead" indicates that the software
# completed successfully. This is counted as the ORPSoC "passing" the test. In
# fact, whether the system did the right thing or not requires more
# inspection, but roughly this is a good indicator that nothing major went
# wrong.
# Once the current test is finished, the next begins with the compilation of its
# software and linking of the resulting hex file to the run path, etc.
# Main RAM setup - (RTL simulation with Icarus/NCSim only!):
# Define USE_SDRAM to enable the external SDRAM, otherwise the simulation
# defaults to an internal SRAM. Eg. $ make rtl-tests USE_SDRAM=1 VCD=1
# Verilator defaults to internal memories
rtl-tests: prepare_sw prepare_rtl
        @if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
        @echo
        @echo "Beginning loop that will complete the following tests: $(TESTS)"
        @echo
        @for TEST in $(TESTS); do \
                echo "################################################################################"; \
                echo; \
                echo "\t#### Current test: $$TEST ####"; echo; \
                echo "\t#### Compiling software ####"; echo; \
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS); \
                rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
                rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
                sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
                        -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
                        -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
                        -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
                        -e \\!^//.*\$$!d -e \\!^\$$!d ; \
                echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                if [ ! -z $$VCD ]; \
                        then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                fi; \
                if [ ! -z $$UART_PRINTF ]; \
                        then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                fi; \
                echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
                echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
                if [ -z $$NO_SIM_LOGGING ]; then \
                        echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
                fi; \
                echo ; \
                echo "\t#### Compiling RTL ####"; \
                rm -f $(SIM_RUN_DIR)/a.out; \
                $(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(RTL_SIM_FLAGS); \
                echo; \
                echo "\t#### Beginning simulation ####"; \
                time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \
                if [ $$? -gt 0 ]; then exit $$?; fi; \
                TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
                echo; echo "\t####"; \
                if [ $$TEST_RESULT -gt 0 ]; then \
                        echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
                else    echo "\t#### Test $$TEST FAILED ####";\
                fi; \
                echo "\t####"; echo; \
                TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
        done; \
        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
 
 
 
# Use NCSIM instead of icarus
rtl-nc-tests: prepare_sw prepare_rtl
        @if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
        @echo
        @echo "Beginning loop that will complete the following tests: $(TESTS)"
        @echo
        @for TEST in $(TESTS); do \
                echo "################################################################################"; \
                echo; \
                echo "\t#### Current test: $$TEST ####"; echo; \
                echo "\t#### Compiling software ####"; echo; \
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
                rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
                rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST_twobyte_sizefirst.hex $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST_fourbyte.hex $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
                sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
                        -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
                        -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
                        -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
                        -e \\!^//.*\$$!d -e \\!^\$$!d ; \
                echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                if [ ! -z $$VCD ]; \
                        then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                        echo "+access+r" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                fi; \
                if [ ! -z $$UART_PRINTF ]; \
                        then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                fi; \
                if [ ! -z $$USE_SDRAM ]; then \
                        echo "\`define USE_SDRAM" >> $(SIM_RUN_DIR)/test_define.v; \
                fi; \
                echo "+nocopyright" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
                echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
                echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
                if [ -z $$NO_SIM_LOGGING ]; then \
                        echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
                fi; \
                echo ; \
                echo "\t#### Beginning simulation ####"; \
                time -p ncverilog -f $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated -Q -l $(SIM_RESULTS_DIR)/$$TEST-ius-out.log $(RTL_SIM_FLAGS); \
                if [ $$? -gt 0 ]; then exit $$?; fi; \
                TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
                echo; echo "\t####"; \
                if [ $$TEST_RESULT -gt 0 ]; then \
                        echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
                else    echo "\t#### Test $$TEST FAILED ####";\
                fi; \
                echo "\t####"; echo; \
                TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
        done; \
        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
 
################################################################################
# Verilator model build rules
################################################################################
 
 
 
 
# List of System C models - use this list to link the sources into the Verilator
# build directory
SYSC_MODELS=OrpsocAccess TraceSC
 
ifdef VCD
VLT_FLAGS +=-trace
endif
 
# Only need the trace target if we are tracing
ifneq (,$(findstring -trace, $(VLT_FLAGS)))
VLT_TRACEOBJ = SpTraceVcdC
endif
 
# This is the list of extra models we'll issue make commands for
# Included is the SystemPerl trace model
SYSC_MODELS_BUILD=$(SYSC_MODELS) $(VLT_TRACEOBJ)
 
prepare_vlt: prepare_rtl vlt_model_links $(SIM_VLT_DIR)/Vorpsoc_top
 
$(SIM_VLT_DIR)/Vorpsoc_top: $(SIM_VLT_DIR)/libVorpsoc_top.a $(SIM_VLT_DIR)/OrpsocMain.o
# Final linking of the simulation executable. Order of libraries here is important!
        @echo; echo "\tGenerating simulation executable"; echo
        cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o Vorpsoc_top -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/lib-linux64 OrpsocMain.o -lVorpsoc_top -lmodules -lsystemc
 
$(SIM_VLT_DIR)/OrpsocMain.o:
# Now compile the top level systemC "testbench" module
        @echo; echo "\tCompiling top level SystemC testbench"; echo
        cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
 
$(SIM_VLT_DIR)/libVorpsoc_top.a: $(SIM_VLT_DIR)/Vorpsoc_top__ALL.a vlt_modules_compile $(SIM_VLT_DIR)/verilated.o
# Now archive all of the libraries from verilator witht he other modules we might have
        @echo; echo "\tArchiving libraries into libVorpsoc_top.a"; echo
        @cd $(SIM_VLT_DIR) && \
        cp Vorpsoc_top__ALL.a libVorpsoc_top.a && \
        ar rcs libVorpsoc_top.a verilated.o; \
        for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
                ar rcs libVorpsoc_top.a $$SYSCMODEL.o; \
        done
 
$(SIM_VLT_DIR)/verilated.o:
        @echo; echo "\tCompiling verilated.o"; echo
        @cd $(SIM_VLT_DIR) && \
        $(MAKE) -f Vorpsoc_top.mk verilated.o
 
.PHONY: vlt_modules_compile
vlt_modules_compile:
# Compile the module files
        @echo; echo "\tCompiling SystemC models"
        @cd $(SIM_VLT_DIR) && \
        for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
                echo;echo "\t$$SYSCMODEL"; echo; \
                $(MAKE) -f Vorpsoc_top.mk $$SYSCMODEL.o; \
        done
 
$(SIM_VLT_DIR)/Vorpsoc_top__ALL.a: $(SIM_VLT_DIR)/Vorpsoc_top.mk
        @echo; echo "\tCompiling main design"; echo
        @cd $(SIM_VLT_DIR) && \
        $(MAKE) -f Vorpsoc_top.mk Vorpsoc_top__ALL.a
 
$(SIM_VLT_DIR)/Vorpsoc_top.mk: $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated $(SIM_VLT_DIR)/libmodules.a
# Now call verilator to generate the .mk files
        @echo; echo "\tGenerating makefiles with Verilator"; echo
        cd $(SIM_VLT_DIR) && \
        verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(VLT_COMMAND_FILE).generated
 
# SystemC modules library
$(SIM_VLT_DIR)/libmodules.a:
        @echo; echo "\tCompiling SystemC modules"; echo
        @$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make
 
 
# Verilator command script
# Generate the compile script to give Verilator
$(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated:
        @echo; echo "\tGenerating verilator compile script"; echo
        @sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated \
                -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
                -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
                -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
                -e \\!^//.*\$$!d -e \\!^\$$!d;
 
.PHONY: vlt_model_links
vlt_model_links:
# Link all the required system C model files into the verilator work dir
        @echo; echo "\tLinking SystemC model source to verilator build path"; echo
        @if [ ! -d $(SIM_VLT_DIR) ]; then mkdir $(SIM_VLT_DIR); fi
        @cd $(SIM_VLT_DIR) && \
        for SYSCMODEL in $(SYSC_MODELS); do \
                if [ ! -e $$SYSCMODEL.cpp ]; then \
                        ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp .; \
                        ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h .; \
                fi; \
        done
 
 
################################################################################
# Verilator test loop
################################################################################
 
# Verilator defaults to internal memories
vlt-tests: prepare_sw_uart_printf prepare_rtl prepare_vlt
        @if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
        @echo
        @echo "Beginning loop that will complete the following tests: $(TESTS)"
        @echo
        @for TEST in $(TESTS); do \
                echo "################################################################################"; \
                echo; \
                echo "\t#### Current test: $$TEST ####"; echo; \
                echo "\t#### Compiling software ####"; echo; \
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \
                rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
                echo "\t#### Beginning simulation ####"; \
                time -p $(SIM_VLT_DIR)/Vorpsoc_top $$TEST; \
                if [ $$? -gt 0 ]; then exit $$?; fi; \
                TEST_RESULT=1; \
                echo; echo "\t####"; \
                if [ $$TEST_RESULT -gt 0 ]; then \
                        echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
                else    echo "\t#### Test $$TEST FAILED ####";\
                fi; \
                echo "\t####"; echo; \
                TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
        done; \
        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
 
 
 
################################################################################
# Architectural simulator test loop
################################################################################
 
# Verilator defaults to internal memories
sim-tests: prepare_sw_uart_printf
        @if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
        @echo
        @echo "Beginning loop that will complete the following tests: $(TESTS)"
        @echo
        @for TEST in $(TESTS); do \
                echo "################################################################################"; \
                echo; \
                echo "\t#### Current test: $$TEST ####"; echo; \
                echo "\t#### Compiling software ####"; echo; \
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \
                rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST.or32 $(SIM_RUN_DIR)/.; \
                echo;echo "\t#### Launching architectural simulator ####"; \
                time -p $(ARCH_SIM_EXE) --nosrv -f $(SIM_BIN_DIR)/$(ARCH_SIM_CFG_FILE) $$TEST.or32 > $(SIM_RESULTS_DIR)/$$TEST-or1ksim.log 2>&1; \
                if [ $$? -gt 0 ]; then exit $$?; fi; \
                if [ `tail -n 10 $(SIM_RESULTS_DIR)/$$TEST-or1ksim.log | grep -c $(SIM_SUCCESS_MESSAGE)` -gt 0 ]; then \
                        TEST_RESULT=1; \
                fi; \
                echo; echo "\t####"; \
                if [ $$TEST_RESULT -gt 0 ]; then \
                        echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
                else    echo "\t#### Test $$TEST FAILED ####";\
                fi; \
                echo "\t####"; echo; \
                TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
                unlink $(SIM_RUN_DIR)/$$TEST.or32; \
        done; \
        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
 
 
 
################################################################################
# Cleaning rules
################################################################################
 
clean: clean-sw clean-sim
 
clean-sw:
        @for TEST in $(TESTS); do \
                echo "Current test: $$TEST"; \
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
                echo "Current test sw directory: " $$CURRENT_TEST_SW_DIR; \
                $(MAKE) -C $$CURRENT_TEST_SW_DIR clean; \
        done
        $(MAKE) -C $(SW_DIR)/support clean
        $(MAKE) -C $(SW_DIR)/utils clean
 
clean-sim:
        rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.* $(SIM_VLT_DIR)

Line No.	Rev	Author	Line
1	39	julius	`######################################################################`
2			`#### ####`
3			`#### ORPSoCv2 Testbenches Makefile ####`
4			`#### ####`
5			`#### Description ####`
6			`#### ORPSoCv2 Testbenches Makefile, containing rules for ####`
7			`#### configuring and running different tests on the current ####`
8	57	julius	`#### ORPSoC(v2) design. ####`
9	39	julius	`#### ####`
10			`#### To Do: ####`
11	57	julius	`#### * Arrange verilator make rules so that the whole thing ####`
12			`#### isn't recompiled when a single SystemC module is ####`
13			`#### updated. ####`
14			`#### * Test if each software test file gets made properly ####`
15			`#### * Expand software test-suite (uClibc, ecos tests, LTP?) ####`
16	39	julius	`#### ####`
17			`#### Author(s): ####`
18			`#### - jb, jb@orsoc.se ####`
19			`#### ####`
20			`#### ####`
21			`######################################################################`
22			`#### ####`
23			`#### Copyright (C) 2009 Authors and OPENCORES.ORG ####`
24			`#### ####`
25			`#### This source file may be used and distributed without ####`
26			`#### restriction provided that this copyright statement is not ####`
27			`#### removed from the file and that any derivative work contains ####`
28			`#### the original copyright notice and the associated disclaimer. ####`
29			`#### ####`
30			`#### This source file is free software; you can redistribute it ####`
31			`#### and/or modify it under the terms of the GNU Lesser General ####`
32			`#### Public License as published by the Free Software Foundation; ####`
33			`#### either version 2.1 of the License, or (at your option) any ####`
34			`#### later version. ####`
35			`#### ####`
36			`#### This source is distributed in the hope that it will be ####`
37			`#### useful, but WITHOUT ANY WARRANTY; without even the implied ####`
38			`#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####`
39			`#### PURPOSE. See the GNU Lesser General Public License for more ####`
40			`#### details. ####`
41			`#### ####`
42			`#### You should have received a copy of the GNU Lesser General ####`
43			`#### Public License along with this source; if not, download it ####`
44			`#### from http://www.opencores.org/lgpl.shtml ####`
45			`#### ####`
46			`######################################################################`
47	22	julius
48	55	julius	`# Usage:`
49			`#`
50			`# make rtl-tests`
51			`#`
52			`# Run the software tests in the RTL model of the ORPSoC being`
53			`# simulated with an event-driven simulator like Icarus. Also`
54			`# possible to use Cadence's Verilog simulators with the`
55			`# "rtl-nc-tests" target.`
56			`#`
57			`# make vlt-tests`
58			`#`
59			`# Run all the software tests in the RTL model which has been`
60			`# converted into a cycle-accurate SystemC model with Verilator.`
61			`#`
62	57	julius	`# make sim-tests`
63			`#`
64			`# Run all the software tests in the architectural simulator`
65			`#`
66	39	julius
67	55	julius	`# Simulation results:`
68			`#`
69			`# The results and output of the event-driven simulations are in the`
70			`# results path, in parallel to the simulation run and bin paths.`
71	39	julius
72	55	julius	`# Specific tests:`
73			`#`
74	39	julius	`# To run an individual test, specify it in the variable TESTS when`
75	55	julius	`# calling make, eg:`
76			`#`
77			`# make rtl-tests TESTS="mmu-nocache mul-idcd-O2"`
78	39	julius
79	55	julius	`# UART printf:`
80			`#`
81			`# It is possible to enable printf to the console via the UART when`
82			`# running the event-driven simulators. To do this define UART_PRINTF=1`
83			`# when calling make. The SystemC cycle-acccurate model uses this by`
84			`# default.`
85	57	julius	`# Also note when switching between runs with and without UART printf`
86			`# enabled, run a clean-sw so the library files are recompiled when`
87			`# the tests are run - this is not done automatically.`
88	55	julius
89			`# VCDs:`
90			`#`
91	39	julius	`# VCD (value change dumps, usable in a waveform viewer, such as gtkwave`
92			`# to inspect the internals of the system graphically) files can be`
93	55	julius	`# generated by defining a variable VCD, eg.`
94			`#`
95			`# make rtl-tests VCD=1`
96			`#`
97			`# and a dump file will be created in the simulation results directory,`
98			`# and named according to the test run which generated it. This is`
99			`# possible for both event-driven and cycle-accurate simulations.`
100			`# However the cycle-accurate`
101	39	julius
102	57	julius	`# NO_SIM_LOGGING:`
103			`#`
104			`# It is possible to speed up the event-driven simulation slightly by`
105			`# disabling log output of the processor's state to files by defining`
106			`# NO_SIM_LOGGING, eg:`
107			`#`
108			`# make rtl-tests TESTS=except-icdc NO_SIM_LOGGING=1`
109			`#`
110	39	julius
111	57	julius	`# Cleaning:`
112			`# A simple "make clean" cleans everything - software and all temporary`
113			`# simulation files and directories. To clean just the software run:`
114			`#`
115			`# make clean-sw`
116			`#`
117			`# and to clean just the temporary simulation files (including VCDs,`
118			`# results logs - everything under, and including, sim/results/, run`
119			`#`
120			`# make clean-sim`
121			`#`
122	39	julius
123	57	julius	`# Note:`
124			`#`
125			`# The way each of the test loops is written is probably a bit overly complex`
126			`# but this is to save maintaining and calling other files to get this done.`
127			`#`
128	39	julius
129			`# Name of the directory we're currently in`
130	22	julius	`CUR_DIR=$(shell pwd)`
131	39	julius
132			`# The root path of the whole project`
133	22	julius	`PROJECT_ROOT=$(CUR_DIR)/../..`
134
135	39	julius	`# Tests is only defined if it wasn't already defined when make was called`
136			`# This is the default list of every test that is currently possible`
137	33	julius	`TESTS ?= basic-nocache cbasic-nocache-O2 dhry-nocache-O2 except-nocache mmu-nocache mul-nocache-O2 syscall-nocache tick-nocache uart-nocache basic-icdc cbasic-icdc-O2 dhry-icdc-O2 except-icdc mmu-icdc mul-icdc-O2 syscall-icdc tick-icdc uart-icdc`
138	22	julius
139	39	julius	`# Paths to other important parts of this test suite`
140	22	julius	`SIM_DIR=$(PROJECT_ROOT)/sim`
141			`SIM_RUN_DIR=$(SIM_DIR)/run`
142			`SIM_BIN_DIR=$(SIM_DIR)/bin`
143			`SIM_RESULTS_DIR=$(SIM_DIR)/results`
144	44	julius	`SIM_VLT_DIR=$(SIM_DIR)/vlt`
145	22	julius	`BENCH_DIR=$(PROJECT_ROOT)/bench`
146			`BACKEND_DIR=$(PROJECT_ROOT)/backend`
147			`BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog`
148	44	julius	`BENCH_SYSC_DIR=$(BENCH_DIR)/sysc`
149	47	julius	`BENCH_SYSC_SRC_DIR=$(BENCH_SYSC_DIR)/src`
150			`BENCH_SYSC_INCLUDE_DIR=$(BENCH_SYSC_DIR)/include`
151	22	julius	`RTL_VERILOG_DIR=$(PROJECT_ROOT)/rtl/verilog`
152			`SW_DIR=$(PROJECT_ROOT)/sw`
153
154			`ICARUS=iverilog`
155			`ICARUS_VVP=vvp`
156			`ICARUS_COMMAND_FILE=icarus.scr`
157	41	julius	`VLT_COMMAND_FILE=verilator.scr`
158	32	julius	`SIM_SUCCESS_MESSAGE=deaddead`
159	22	julius
160	56	julius	`ARCH_SIM_EXE=or32-elf-sim`
161			`ARCH_SIM_CFG_FILE=or1ksim-orpsocv2.cfg`
162
163	45	julius	`# If USE_SDRAM is defined we'll add it to the simulator's defines on the`
164			`# command line becuase it's used by many different modules and it's easier`
165			`# to do it this way than make them all include a file.`
166			`ifdef USE_SDRAM`
167			`RTL_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)"`
168			`endif`
169			`SIM_FLASH_MEM_FILE="flash.in"`
170			`FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"`
171			`SIM_SRAM_MEM_FILE="sram.vmem"`
172
173	52	julius	`TESTS_PASSED=0`
174			`TESTS_PERFORMED=0;`
175
176			`################################################################################`
177			`# Event-driven simulator build rules (Icarus, NCSim)`
178			`################################################################################`
179
180	22	julius	`.PHONY: prepare_rtl`
181			`prepare_rtl:`
182	26	julius	`@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v`
183	43	julius	`@cd $(RTL_VERILOG_DIR) && sed '/defparam/!s/\([a-zA-Z0-9_]\)\.//g' intercon.vm > intercon.v`
184	22	julius
185	52	julius
186			`ifdef UART_PRINTF`
187			`TEST_SW_MAKE_OPTS=UART_PRINTF=1`
188			`endif`
189
190	26	julius	`.PHONY: prepare_sw`
191			`prepare_sw:`
192	52	julius	`@$(MAKE) -C $(SW_DIR)/support all $(TEST_SW_MAKE_OPTS)`
193			`@$(MAKE) -C $(SW_DIR)/utils all`
194	26	julius
195	54	julius	`# A rule with UART_PRINTF hard defined ... used by verilator make sw`
196	53	julius	`prepare_sw_uart_printf:`
197			`@$(MAKE) -C $(SW_DIR)/support all UART_PRINTF=1 $(TEST_SW_MAKE_OPTS)`
198			`@$(MAKE) -C $(SW_DIR)/utils all`
199	52	julius
200	53	julius
201	39	julius	`# Rough guide to how these tests work:`
202			`# First, the couple of custom, required, software tools under sw/utils are`
203			`# compiled, and then the software library files.`
204			`# Next the few verilog files that need preperation are taken care of.`
205			`# The test begins by starting a loop in bash using on the strings defined in`
206			`# TESTS. Each one corresponds to a certain module of software for the OpenRISC`
207			`# that is included in this test suite. Under the sw/ path is a set of paths,`
208	45	julius	`# and all except the support/ and utils/ paths contain code which is run to`
209			`# test the OR1k used in this test suite. For each of these software modules,`
210			`# it is possible that different tests are done using the same module. These`
211			`# tests can vary by either using different levels of optimisation during`
212			`# compilation, and/or by having the OR1k's caches enabled or disabled.`
213	39	julius	`# Each test has a unique name, and under the $(SIM_RESULTS_DIR), which is`
214			`# usually just ../results, log files, and optionally VCD files, are created for`
215			`# inspection later and are named according to the test. Inspect the file`
216	45	julius	`# bench/verilog/or1200_monitor.v to find out in detail what each log consists`
217			`# of.`
218	39	julius	`# For each test, a few things occur. First the software that will run inside`
219	45	julius	`# the simulated OR1k system is compiled, converted to a format which can be`
220			`# read`
221	39	julius	`# into the flash memory model via $readmemh() and linked to the sim/run`
222	45	julius	`# directory as $(SIM_FLASH_MEM_FILE), which currently is flash.in. Next a`
223			`# compilation script for icarus is generated, containing a list of all the`
224			`# RTL files and include directories. Next, an include file for the verilog`
225			`# testbench is generated, containing a string of the name of the current`
226			`# test, path to the results directory (for VCD generation) and any other`
227			`# things which might vary from test to test. This is not done by +define`
228			`# lines in the icarus script because of string handling incosistencies`
229			`# between different simulators and shells.`
230			`# Once all the files are generated, icarus is called to compile the rtl`
231			`# design, and then run it. Each of the tested software modules have code which`
232			`# will trigger the simulation to be stopped by use of the l.nop instruction`
233			`# with an immediate value of 1. When the simulation finishes, the simulation`
234			`# executable exits and the log of the simulation is inspected for the expected`
235			`# output. Currently, the string "deaddead" indicates that the software`
236			`# completed successfully. This is counted as the ORPSoC "passing" the test. In`
237			`# fact, whether the system did the right thing or not requires more`
238			`# inspection, but roughly this is a good indicator that nothing major went`
239			`# wrong.`
240	39	julius	`# Once the current test is finished, the next begins with the compilation of its`
241			`# software and linking of the resulting hex file to the run path, etc.`
242	45	julius	`# Main RAM setup - (RTL simulation with Icarus/NCSim only!):`
243			`# Define USE_SDRAM to enable the external SDRAM, otherwise the simulation`
244			`# defaults to an internal SRAM. Eg. $ make rtl-tests USE_SDRAM=1 VCD=1`
245			`# Verilator defaults to internal memories`
246	39	julius	`rtl-tests: prepare_sw prepare_rtl`
247	22	julius	`@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi`
248	33	julius	`@echo`
249			`@echo "Beginning loop that will complete the following tests: $(TESTS)"`
250			`@echo`
251	31	julius	`@for TEST in $(TESTS); do \`
252	33	julius	`echo "################################################################################"; \`
253			`echo; \`
254			`echo "\t#### Current test: $$TEST ####"; echo; \`
255	32	julius	`echo "\t#### Compiling software ####"; echo; \`
256	22	julius	CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST \| cut -d "-" -f 1`; \
257	52	julius	`$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS); \`
258	45	julius	`rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \`
259			`rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \`
260			`ln -s $$CURRENT_TEST_SW_DIR/$$TEST$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \`
261			`ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \`
262	22	julius	`sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \`
263			`-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \`
264			`-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \`
265			`-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \`
266			`-e \\!^//.*\$$!d -e \\!^\$$!d ; \`
267	34	julius	`echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
268	26	julius	`if [ ! -z $$VCD ]; \`
269			`then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
270			`fi; \`
271	54	julius	`if [ ! -z $$UART_PRINTF ]; \`
272			`then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
273			`fi; \`
274	34	julius	echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
275			echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
276	39	julius	`if [ -z $$NO_SIM_LOGGING ]; then \`
277			echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
278			`fi; \`
279	22	julius	`echo ; \`
280	32	julius	`echo "\t#### Compiling RTL ####"; \`
281	22	julius	`rm -f $(SIM_RUN_DIR)/a.out; \`
282	43	julius	`$(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(RTL_SIM_FLAGS); \`
283	22	julius	`echo; \`
284	32	julius	`echo "\t#### Beginning simulation ####"; \`
285	33	julius	`time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \`
286	36	julius	`if [ $$? -gt 0 ]; then exit $$?; fi; \`
287			TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log \| grep report \| grep $(SIM_SUCCESS_MESSAGE) -c`; \
288	33	julius	`echo; echo "\t####"; \`
289	34	julius	`if [ $$TEST_RESULT -gt 0 ]; then \`
290	52	julius	echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
291	32	julius	`else echo "\t#### Test $$TEST FAILED ####";\`
292			`fi; \`
293	33	julius	`echo "\t####"; echo; \`
294	52	julius	TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
295			`done; \`
296			`echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo`
297	33	julius
298
299	52	julius
300	39	julius	`# Use NCSIM instead of icarus`
301			`rtl-nc-tests: prepare_sw prepare_rtl`
302	35	julius	`@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi`
303			`@echo`
304			`@echo "Beginning loop that will complete the following tests: $(TESTS)"`
305			`@echo`
306			`@for TEST in $(TESTS); do \`
307			`echo "################################################################################"; \`
308			`echo; \`
309			`echo "\t#### Current test: $$TEST ####"; echo; \`
310			`echo "\t#### Compiling software ####"; echo; \`
311			CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST \| cut -d "-" -f 1`; \
312			`$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \`
313	45	julius	`rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \`
314			`rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \`
315			`ln -s $$CURRENT_TEST_SW_DIR/$$TEST_twobyte_sizefirst.hex $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \`
316			`ln -s $$CURRENT_TEST_SW_DIR/$$TEST_fourbyte.hex $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \`
317	35	julius	`sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \`
318			`-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \`
319			`-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \`
320			`-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \`
321			`-e \\!^//.*\$$!d -e \\!^\$$!d ; \`
322			`echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
323			`if [ ! -z $$VCD ]; \`
324			`then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
325			`echo "+access+r" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
326			`fi; \`
327	54	julius	`if [ ! -z $$UART_PRINTF ]; \`
328			`then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
329			`fi; \`
330	45	julius	`if [ ! -z $$USE_SDRAM ]; then \`
331			echo "\`define USE_SDRAM" >> $(SIM_RUN_DIR)/test_define.v; \
332			`fi; \`
333	36	julius	`echo "+nocopyright" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
334			`echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \`
335	35	julius	echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
336			echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
337	39	julius	`if [ -z $$NO_SIM_LOGGING ]; then \`
338			echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
339			`fi; \`
340	35	julius	`echo ; \`
341			`echo "\t#### Beginning simulation ####"; \`
342	36	julius	`time -p ncverilog -f $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated -Q -l $(SIM_RESULTS_DIR)/$$TEST-ius-out.log $(RTL_SIM_FLAGS); \`
343			`if [ $$? -gt 0 ]; then exit $$?; fi; \`
344			TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log \| grep report \| grep $(SIM_SUCCESS_MESSAGE) -c`; \
345	35	julius	`echo; echo "\t####"; \`
346			`if [ $$TEST_RESULT -gt 0 ]; then \`
347	54	julius	echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
348	35	julius	`else echo "\t#### Test $$TEST FAILED ####";\`
349			`fi; \`
350			`echo "\t####"; echo; \`
351	54	julius	TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
352			`done; \`
353			`echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo`
354	33	julius
355	52	julius	`################################################################################`
356			`# Verilator model build rules`
357			`################################################################################`
358	48	julius
359	52	julius
360
361
362			`# List of System C models - use this list to link the sources into the Verilator`
363	50	julius	`# build directory`
364	48	julius	`SYSC_MODELS=OrpsocAccess TraceSC`
365
366	55	julius	`ifdef VCD`
367			`VLT_FLAGS +=-trace`
368			`endif`
369
370	52	julius	`# Only need the trace target if we are tracing`
371			`ifneq (,$(findstring -trace, $(VLT_FLAGS)))`
372			`VLT_TRACEOBJ = SpTraceVcdC`
373			`endif`
374
375	50	julius	`# This is the list of extra models we'll issue make commands for`
376			`# Included is the SystemPerl trace model`
377	52	julius	`SYSC_MODELS_BUILD=$(SYSC_MODELS) $(VLT_TRACEOBJ)`
378	50	julius
379	52	julius	`prepare_vlt: prepare_rtl vlt_model_links $(SIM_VLT_DIR)/Vorpsoc_top`
380
381			`$(SIM_VLT_DIR)/Vorpsoc_top: $(SIM_VLT_DIR)/libVorpsoc_top.a $(SIM_VLT_DIR)/OrpsocMain.o`
382			`# Final linking of the simulation executable. Order of libraries here is important!`
383			`@echo; echo "\tGenerating simulation executable"; echo`
384			`cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o Vorpsoc_top -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/lib-linux64 OrpsocMain.o -lVorpsoc_top -lmodules -lsystemc`
385
386			`$(SIM_VLT_DIR)/OrpsocMain.o:`
387			`# Now compile the top level systemC "testbench" module`
388			`@echo; echo "\tCompiling top level SystemC testbench"; echo`
389	48	julius	`cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp`
390	52	julius
391			`$(SIM_VLT_DIR)/libVorpsoc_top.a: $(SIM_VLT_DIR)/Vorpsoc_top__ALL.a vlt_modules_compile $(SIM_VLT_DIR)/verilated.o`
392	48	julius	`# Now archive all of the libraries from verilator witht he other modules we might have`
393	52	julius	`@echo; echo "\tArchiving libraries into libVorpsoc_top.a"; echo`
394			`@cd $(SIM_VLT_DIR) && \`
395	48	julius	`cp Vorpsoc_top__ALL.a libVorpsoc_top.a && \`
396			`ar rcs libVorpsoc_top.a verilated.o; \`
397	50	julius	`for SYSCMODEL in $(SYSC_MODELS_BUILD); do \`
398	48	julius	`ar rcs libVorpsoc_top.a $$SYSCMODEL.o; \`
399			`done`
400	41	julius
401	52	julius	`$(SIM_VLT_DIR)/verilated.o:`
402			`@echo; echo "\tCompiling verilated.o"; echo`
403			`@cd $(SIM_VLT_DIR) && \`
404			`$(MAKE) -f Vorpsoc_top.mk verilated.o`
405	41	julius
406	52	julius	`.PHONY: vlt_modules_compile`
407			`vlt_modules_compile:`
408			`# Compile the module files`
409			`@echo; echo "\tCompiling SystemC models"`
410			`@cd $(SIM_VLT_DIR) && \`
411			`for SYSCMODEL in $(SYSC_MODELS_BUILD); do \`
412			`echo;echo "\t$$SYSCMODEL"; echo; \`
413			`$(MAKE) -f Vorpsoc_top.mk $$SYSCMODEL.o; \`
414			`done`
415
416			`$(SIM_VLT_DIR)/Vorpsoc_top__ALL.a: $(SIM_VLT_DIR)/Vorpsoc_top.mk`
417			`@echo; echo "\tCompiling main design"; echo`
418			`@cd $(SIM_VLT_DIR) && \`
419			`$(MAKE) -f Vorpsoc_top.mk Vorpsoc_top__ALL.a`
420
421			`$(SIM_VLT_DIR)/Vorpsoc_top.mk: $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated $(SIM_VLT_DIR)/libmodules.a`
422			`# Now call verilator to generate the .mk files`
423	53	julius	`@echo; echo "\tGenerating makefiles with Verilator"; echo`
424	52	julius	`cd $(SIM_VLT_DIR) && \`
425			`verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(VLT_COMMAND_FILE).generated`
426
427	47	julius	`# SystemC modules library`
428			`$(SIM_VLT_DIR)/libmodules.a:`
429	52	julius	`@echo; echo "\tCompiling SystemC modules"; echo`
430			`@$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make`
431	47	julius
432	52	julius
433			`# Verilator command script`
434			`# Generate the compile script to give Verilator`
435			`$(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated:`
436			`@echo; echo "\tGenerating verilator compile script"; echo`
437			`@sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated \`
438			`-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \`
439			`-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \`
440			`-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \`
441			`-e \\!^//.*\$$!d -e \\!^\$$!d;`
442
443			`.PHONY: vlt_model_links`
444			`vlt_model_links:`
445			`# Link all the required system C model files into the verilator work dir`
446			`@echo; echo "\tLinking SystemC model source to verilator build path"; echo`
447			`@if [ ! -d $(SIM_VLT_DIR) ]; then mkdir $(SIM_VLT_DIR); fi`
448			`@cd $(SIM_VLT_DIR) && \`
449			`for SYSCMODEL in $(SYSC_MODELS); do \`
450			`if [ ! -e $$SYSCMODEL.cpp ]; then \`
451			`ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp .; \`
452			`ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h .; \`
453			`fi; \`
454			`done`
455
456	53	julius
457	52	julius	`################################################################################`
458	53	julius	`# Verilator test loop`
459			`################################################################################`
460
461			`# Verilator defaults to internal memories`
462			`vlt-tests: prepare_sw_uart_printf prepare_rtl prepare_vlt`
463	56	julius	`@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi`
464	53	julius	`@echo`
465			`@echo "Beginning loop that will complete the following tests: $(TESTS)"`
466			`@echo`
467			`@for TEST in $(TESTS); do \`
468			`echo "################################################################################"; \`
469			`echo; \`
470			`echo "\t#### Current test: $$TEST ####"; echo; \`
471			`echo "\t#### Compiling software ####"; echo; \`
472			CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST \| cut -d "-" -f 1`; \
473			`$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \`
474			`rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \`
475			`ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \`
476			`echo "\t#### Beginning simulation ####"; \`
477	55	julius	`time -p $(SIM_VLT_DIR)/Vorpsoc_top $$TEST; \`
478	53	julius	`if [ $$? -gt 0 ]; then exit $$?; fi; \`
479			`TEST_RESULT=1; \`
480			`echo; echo "\t####"; \`
481			`if [ $$TEST_RESULT -gt 0 ]; then \`
482			echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
483			`else echo "\t#### Test $$TEST FAILED ####";\`
484			`fi; \`
485			`echo "\t####"; echo; \`
486			TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
487			`done; \`
488			`echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo`
489
490
491	56	julius
492	53	julius	`################################################################################`
493	56	julius	`# Architectural simulator test loop`
494			`################################################################################`
495
496			`# Verilator defaults to internal memories`
497			`sim-tests: prepare_sw_uart_printf`
498			`@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi`
499			`@echo`
500			`@echo "Beginning loop that will complete the following tests: $(TESTS)"`

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