| 1 |
22 |
julius |
+incdir+$BENCH_DIR
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| 2 |
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+incdir+$BACKEND_DIR
|
| 3 |
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+incdir+$RTL_DIR
|
| 4 |
|
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+incdir+$RTL_DIR/components/uart16550
|
| 5 |
|
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+incdir+$RTL_DIR/components/ethernet
|
| 6 |
|
|
+incdir+$RTL_DIR/components/or1k_startup
|
| 7 |
|
|
+incdir+$RTL_DIR/components/or1k_top
|
| 8 |
|
|
+incdir+$RTL_DIR/components/tap
|
| 9 |
|
|
+incdir+$RTL_DIR/components/smii
|
| 10 |
|
|
+incdir+$RTL_DIR/components/debug_if
|
| 11 |
|
|
+incdir+$RTL_DIR/components/wb_sdram_ctrl
|
| 12 |
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|
| 13 |
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|
| 14 |
|
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// Testbench files
|
| 15 |
|
|
$BENCH_DIR/orpsoc_testbench.v
|
| 16 |
31 |
julius |
$BENCH_DIR/or1200_monitor.v
|
| 17 |
22 |
julius |
$BENCH_DIR/AT26DFxxx.v
|
| 18 |
|
|
$BENCH_DIR/mt48lc16m16a2.v
|
| 19 |
|
|
$BENCH_DIR/clk_gen.v
|
| 20 |
|
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|
| 21 |
|
|
// Simulation library file
|
| 22 |
|
|
$BACKEND_DIR/sim_lib.v
|
| 23 |
|
|
|
| 24 |
|
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// RTL files (top)
|
| 25 |
|
|
$RTL_DIR/orp_soc.v
|
| 26 |
|
|
|
| 27 |
|
|
// Interconnect top level file
|
| 28 |
|
|
$RTL_DIR/intercon.vm
|
| 29 |
|
|
$RTL_DIR/dummy_slave.v
|
| 30 |
|
|
|
| 31 |
|
|
// UART
|
| 32 |
|
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$RTL_DIR/uart_defines.v
|
| 33 |
|
|
$RTL_DIR/components/uart16550/uart_tfifo.v
|
| 34 |
|
|
$RTL_DIR/components/uart16550/uart_debug_if.v
|
| 35 |
|
|
$RTL_DIR/components/uart16550/uart_defines.v
|
| 36 |
|
|
$RTL_DIR/components/uart16550/raminfr.v
|
| 37 |
|
|
$RTL_DIR/components/uart16550/uart_regs.v
|
| 38 |
|
|
$RTL_DIR/components/uart16550/uart_rfifo.v
|
| 39 |
|
|
$RTL_DIR/components/uart16550/uart_top.v
|
| 40 |
|
|
$RTL_DIR/components/uart16550/uart_transmitter.v
|
| 41 |
|
|
$RTL_DIR/components/uart16550/uart_sync_flops.v
|
| 42 |
|
|
$RTL_DIR/components/uart16550/uart_receiver.v
|
| 43 |
|
|
$RTL_DIR/components/uart16550/uart_wb.v
|
| 44 |
|
|
$RTL_DIR/components/uart16550/timescale.v
|
| 45 |
|
|
|
| 46 |
|
|
// Ethernet MAC
|
| 47 |
|
|
$RTL_DIR/eth_defines.v
|
| 48 |
|
|
$RTL_DIR/components/ethernet/eth_registers.v
|
| 49 |
|
|
$RTL_DIR/components/ethernet/eth_maccontrol.v
|
| 50 |
|
|
$RTL_DIR/components/ethernet/eth_rxcounters.v
|
| 51 |
|
|
$RTL_DIR/components/ethernet/eth_outputcontrol.v
|
| 52 |
|
|
$RTL_DIR/components/ethernet/eth_rxethmac.v
|
| 53 |
|
|
//$RTL_DIR/components/ethernet/xilinx_dist_ram_16x32.v
|
| 54 |
|
|
$RTL_DIR/components/ethernet/eth_transmitcontrol.v
|
| 55 |
|
|
$RTL_DIR/components/ethernet/eth_defines.v
|
| 56 |
|
|
$RTL_DIR/components/ethernet/eth_txstatem.v
|
| 57 |
|
|
$RTL_DIR/components/ethernet/eth_cop.v
|
| 58 |
|
|
$RTL_DIR/components/ethernet/eth_txcounters.v
|
| 59 |
|
|
$RTL_DIR/components/ethernet/eth_rxaddrcheck.v
|
| 60 |
|
|
$RTL_DIR/components/ethernet/eth_spram_256x32.v
|
| 61 |
|
|
$RTL_DIR/components/ethernet/eth_crc.v
|
| 62 |
|
|
$RTL_DIR/components/ethernet/eth_wishbone.v
|
| 63 |
|
|
$RTL_DIR/components/ethernet/eth_miim.v
|
| 64 |
|
|
$RTL_DIR/components/ethernet/eth_macstatus.v
|
| 65 |
|
|
$RTL_DIR/components/ethernet/eth_clockgen.v
|
| 66 |
|
|
$RTL_DIR/components/ethernet/eth_fifo.v
|
| 67 |
|
|
$RTL_DIR/components/ethernet/eth_rxstatem.v
|
| 68 |
|
|
$RTL_DIR/components/ethernet/eth_top.v
|
| 69 |
|
|
$RTL_DIR/components/ethernet/eth_shiftreg.v
|
| 70 |
|
|
$RTL_DIR/components/ethernet/eth_receivecontrol.v
|
| 71 |
|
|
$RTL_DIR/components/ethernet/eth_txethmac.v
|
| 72 |
|
|
$RTL_DIR/components/ethernet/eth_random.v
|
| 73 |
|
|
$RTL_DIR/components/ethernet/eth_register.v
|
| 74 |
|
|
$RTL_DIR/components/ethernet/timescale.v
|
| 75 |
|
|
|
| 76 |
|
|
// SDRAM controller
|
| 77 |
|
|
$RTL_DIR/components/wb_sdram_ctrl/wb_sdram_ctrl_defines.v
|
| 78 |
|
|
$RTL_DIR/components/wb_sdram_ctrl/delay.v
|
| 79 |
|
|
$RTL_DIR/components/wb_sdram_ctrl/wb_sdram_ctrl_top.v
|
| 80 |
|
|
$RTL_DIR/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v
|
| 81 |
|
|
$RTL_DIR/components/wb_sdram_ctrl/fifo.v
|
| 82 |
|
|
|
| 83 |
|
|
// OR1200
|
| 84 |
|
|
$RTL_DIR/or1200_defines.v
|
| 85 |
|
|
$RTL_DIR/components/or1200r2/or1200_spram_256x21.v
|
| 86 |
|
|
$RTL_DIR/components/or1200r2/or1200_dpram_256x32.v
|
| 87 |
|
|
$RTL_DIR/components/or1200r2/or1200_xcv_ram32x8d.v
|
| 88 |
|
|
$RTL_DIR/components/or1200r2/or1200_ic_top.v
|
| 89 |
|
|
$RTL_DIR/components/or1200r2/or1200_ic_fsm.v
|
| 90 |
|
|
$RTL_DIR/components/or1200r2/or1200_spram.v
|
| 91 |
|
|
$RTL_DIR/components/or1200r2/or1200_spram_64x24.v
|
| 92 |
|
|
$RTL_DIR/components/or1200r2/or1200_qmem_top.v
|
| 93 |
|
|
$RTL_DIR/components/or1200r2/or1200_tpram_32x32.v
|
| 94 |
|
|
$RTL_DIR/components/or1200r2/or1200_freeze.v
|
| 95 |
|
|
$RTL_DIR/components/or1200r2/or1200_spram_512x20.v
|
| 96 |
|
|
$RTL_DIR/components/or1200r2/or1200_immu_tlb.v
|
| 97 |
|
|
$RTL_DIR/components/or1200r2/or1200_du.v
|
| 98 |
|
|
$RTL_DIR/components/or1200r2/or1200_cfgr.v
|
| 99 |
|
|
$RTL_DIR/components/or1200r2/or1200_spram_1024x32_bw.v
|
| 100 |
|
|
$RTL_DIR/components/or1200r2/or1200_amultp2_32x32.v
|
| 101 |
|
|
$RTL_DIR/components/or1200r2/or1200_dc_tag.v
|
| 102 |
|
|
$RTL_DIR/components/or1200r2/or1200_sb.v
|
| 103 |
|
|
$RTL_DIR/components/or1200r2/or1200_dc_ram.v
|
| 104 |
|
|
$RTL_DIR/components/or1200r2/or1200_mult_mac.v
|
| 105 |
|
|
$RTL_DIR/components/or1200r2/or1200_wb_biu.v
|
| 106 |
|
|
$RTL_DIR/components/or1200r2/or1200_lsu.v
|
| 107 |
|
|
$RTL_DIR/components/or1200r2/or1200_iwb_biu.v
|
| 108 |
|
|
$RTL_DIR/components/or1200r2/or1200_gmultp2_32x32.v
|
| 109 |
|
|
$RTL_DIR/components/or1200r2/or1200_alu.v
|
| 110 |
|
|
$RTL_DIR/components/or1200r2/or1200_reg2mem.v
|
| 111 |
|
|
$RTL_DIR/components/or1200r2/or1200_ctrl.v
|
| 112 |
|
|
$RTL_DIR/components/or1200r2/or1200_dmmu_top.v
|
| 113 |
|
|
$RTL_DIR/components/or1200r2/or1200_cpu.v
|
| 114 |
|
|
$RTL_DIR/components/or1200r2/or1200_dc_top.v
|
| 115 |
|
|
$RTL_DIR/components/or1200r2/or1200_sprs.v
|
| 116 |
|
|
//$RTL_DIR/components/or1200r2/or1200_dpram.v
|
| 117 |
|
|
$RTL_DIR/components/or1200r2/or1200_wbmux.v
|
| 118 |
|
|
$RTL_DIR/components/or1200r2/or1200_spram_32x24.v
|
| 119 |
|
|
$RTL_DIR/components/or1200r2/or1200_if.v
|
| 120 |
|
|
$RTL_DIR/components/or1200r2/or1200_rf.v
|
| 121 |
|
|
$RTL_DIR/components/or1200r2/or1200_spram_2048x32.v
|
| 122 |
|
|
$RTL_DIR/components/or1200r2/or1200_genpc.v
|
| 123 |
|
|
$RTL_DIR/components/or1200r2/or1200_spram_128x32.v
|
| 124 |
|
|
$RTL_DIR/components/or1200r2/or1200_spram_2048x8.v
|
| 125 |
|
|
$RTL_DIR/components/or1200r2/or1200_spram_64x14.v
|
| 126 |
|
|
$RTL_DIR/components/or1200r2/or1200_defines.v
|
| 127 |
|
|
$RTL_DIR/components/or1200r2/or1200_top.v
|
| 128 |
|
|
$RTL_DIR/components/or1200r2/or1200_spram_1024x32.v
|
| 129 |
|
|
$RTL_DIR/components/or1200r2/or1200_rfram_generic.v
|
| 130 |
|
|
$RTL_DIR/components/or1200r2/or1200_except.v
|
| 131 |
|
|
$RTL_DIR/components/or1200r2/or1200_operandmuxes.v
|
| 132 |
|
|
$RTL_DIR/components/or1200r2/or1200_ic_ram.v
|
| 133 |
|
|
$RTL_DIR/components/or1200r2/or1200_dc_fsm.v
|
| 134 |
|
|
$RTL_DIR/components/or1200r2/or1200_sb_fifo.v
|
| 135 |
|
|
$RTL_DIR/components/or1200r2/or1200_ic_tag.v
|
| 136 |
|
|
$RTL_DIR/components/or1200r2/or1200_pic.v
|
| 137 |
|
|
$RTL_DIR/components/or1200r2/or1200_dmmu_tlb.v
|
| 138 |
|
|
$RTL_DIR/components/or1200r2/or1200_immu_top.v
|
| 139 |
|
|
$RTL_DIR/components/or1200r2/or1200_pm.v
|
| 140 |
|
|
$RTL_DIR/components/or1200r2/or1200_mem2reg.v
|
| 141 |
|
|
$RTL_DIR/components/or1200r2/or1200_dpram_32x32.v
|
| 142 |
|
|
$RTL_DIR/components/or1200r2/or1200_tt.v
|
| 143 |
|
|
$RTL_DIR/components/or1200r2/or1200_spram_2048x32_bw.v
|
| 144 |
|
|
$RTL_DIR/components/or1200r2/or1200_spram_64x22.v
|
| 145 |
|
|
$RTL_DIR/components/or1200r2/or1200_spram_1024x8.v
|
| 146 |
|
|
$RTL_DIR/components/or1200r2/timescale.v
|
| 147 |
|
|
$RTL_DIR/components/or1k_startup/copyright_OR1K_startup.v
|
| 148 |
|
|
$RTL_DIR/components/or1k_startup/spi_shift.v
|
| 149 |
|
|
$RTL_DIR/components/or1k_startup/OR1K_startup_generic.v
|
| 150 |
|
|
$RTL_DIR/components/or1k_startup/copyright_spi.v
|
| 151 |
|
|
//$RTL_DIR/components/or1k_startup/OR1K_startup.v
|
| 152 |
|
|
$RTL_DIR/components/or1k_startup/spi_defines.v
|
| 153 |
|
|
//$RTL_DIR/components/or1k_startup/OR1K_startup_rom.v
|
| 154 |
|
|
//$RTL_DIR/components/or1k_startup/spi_flash.v
|
| 155 |
|
|
//$RTL_DIR/components/or1k_startup/flash_wb_32x32.v
|
| 156 |
|
|
$RTL_DIR/components/or1k_startup/spi_top.v
|
| 157 |
|
|
$RTL_DIR/components/or1k_startup/spi_clgen.v
|
| 158 |
|
|
//$RTL_DIR/components/or1k_startup/OR1K_startup_ACTEL.v
|
| 159 |
|
|
//$RTL_DIR/components/or1k_startup/OR1K_startup_ACTEL_IP.v
|
| 160 |
|
|
$RTL_DIR/components/or1k_startup/timescale.v
|
| 161 |
|
|
$RTL_DIR/components/or1k_top/or1k_top.v
|
| 162 |
|
|
|
| 163 |
|
|
|
| 164 |
|
|
// JTAG TAP
|
| 165 |
|
|
$RTL_DIR/components/tap/tap_defines.v
|
| 166 |
|
|
//$RTL_DIR/components/tap/tap.v
|
| 167 |
|
|
$RTL_DIR/components/tap/tap_top.v
|
| 168 |
|
|
$RTL_DIR/components/tap/timescale.v
|
| 169 |
|
|
|
| 170 |
|
|
|
| 171 |
|
|
$RTL_DIR/components/smii/smii_sync.v
|
| 172 |
|
|
$RTL_DIR/components/smii/copyright.v
|
| 173 |
|
|
$RTL_DIR/components/smii/generic_buffers.v
|
| 174 |
|
|
$RTL_DIR/components/smii/generic_gbuf.v
|
| 175 |
|
|
//$RTL_DIR/components/smii/smii.v
|
| 176 |
|
|
//$RTL_DIR/components/smii/smii_ACTEL.v
|
| 177 |
|
|
$RTL_DIR/components/smii/smii_txrx.v
|
| 178 |
|
|
|
| 179 |
|
|
// Debug module
|
| 180 |
|
|
$RTL_DIR/components/debug_if/dbg_cpu_defines.v
|
| 181 |
|
|
$RTL_DIR/components/debug_if/dbg_cpu.v
|
| 182 |
|
|
$RTL_DIR/components/debug_if/dbg_cpu_registers.v
|
| 183 |
|
|
$RTL_DIR/components/debug_if/dbg_register.v
|
| 184 |
|
|
$RTL_DIR/components/debug_if/dbg_wb.v
|
| 185 |
|
|
$RTL_DIR/components/debug_if/dbg_top.v
|
| 186 |
|
|
$RTL_DIR/components/debug_if/dbg_crc32_d1.v
|
| 187 |
|
|
$RTL_DIR/components/debug_if/dbg_defines_old.v
|
| 188 |
|
|
$RTL_DIR/components/debug_if/dbg_wb_defines.v
|
| 189 |
|
|
$RTL_DIR/components/debug_if/dbg_defines.v
|
| 190 |
|
|
$RTL_DIR/components/debug_if/timescale.v
|
