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[/] [test_project/] [trunk/] [sim/] [bin/] [verilator.scr] - Blame information for rev 45

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Line No. Rev Author Line
1 44 julius 
// This file should be processed by the Makefile before being used
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+incdir+$BENCH_DIR
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+incdir+$BACKEND_DIR
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+incdir+$RTL_DIR
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+incdir+$RTL_DIR/components/uart16550
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+incdir+$RTL_DIR/components/ethernet
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+incdir+$RTL_DIR/components/or1k_startup
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+incdir+$RTL_DIR/components/or1k_top
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+incdir+$RTL_DIR/components/or1200r2
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+incdir+$RTL_DIR/components/tap
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+incdir+$RTL_DIR/components/smii
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+incdir+$RTL_DIR/components/debug_if
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+incdir+$RTL_DIR/components/wb_sdram_ctrl
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-y $BENCH_DIR
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-y $BACKEND_DIR
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-y $RTL_DIR
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-y $RTL_DIR/components/uart16550
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-y $RTL_DIR/components/ethernet
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-y $RTL_DIR/components/or1k_startup
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-y $RTL_DIR/components/or1k_top
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-y $RTL_DIR/components/or1200r2
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-y $RTL_DIR/components/tap
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-y $RTL_DIR/components/smii
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-y $RTL_DIR/components/debug_if
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-y $RTL_DIR/components/wb_sdram_ctrl
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// RTL files (top)
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$RTL_DIR/orpsoc_top.v
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-v $RTL_DIR/components/smii/generic_buffers.v
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-v $BACKEND_DIR/sim_lib.v
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