OpenCores
URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [sw/] [basic/] [basic.S] - Blame information for rev 87

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 25 julius
/* Basic instruction set test */
2
#include "../support/spr_defs.h"
3
 
4
.global _main
5
.global _buserr_except
6
.global _dpf_except
7
.global _ipf_except
8
.global _lpint_except
9
.global _align_except
10
.global _illegal_except
11
.global _hpint_except
12
.global _dtlbmiss_except
13
.global _itlbmiss_except
14
.global _range_except
15
.global _syscall_except
16
.global _res1_except
17
.global _trap_except
18
.global _res2_except
19
 
20
 
21
        .section .stack
22
        .space 0x1000
23
_tmp_stack:
24
 
25
 
26
 
27
  .section .text
28
 
29
_buserr_except:
30
_dpf_except:
31
_ipf_except:
32
_lpint_except:
33
_align_except:
34
_illegal_except:
35
_hpint_except:
36
_dtlbmiss_except:
37
_itlbmiss_except:
38
_range_except:
39
_syscall_except:
40
_res1_except:
41
_trap_except:
42
_res2_except:
43
 
44
_main:
45
        l.nop
46
        l.j     _regs
47
        l.nop
48
 
49
_regs:
50
        l.addi  r1,r0,0x1
51
        l.addi  r2,r1,0x2
52
        l.addi  r3,r2,0x4
53
        l.addi  r4,r3,0x8
54
        l.addi  r5,r4,0x10
55
        l.addi  r6,r5,0x20
56
        l.addi  r7,r6,0x40
57
        l.addi  r8,r7,0x80
58
        l.addi  r9,r8,0x100
59
        l.addi  r10,r9,0x200
60
        l.addi  r11,r10,0x400
61
        l.addi  r12,r11,0x800
62
        l.addi  r13,r12,0x1000
63
        l.addi  r14,r13,0x2000
64
        l.addi  r15,r14,0x4000
65
        l.addi  r16,r15,0x8000
66
 
67
        l.sub   r31,r0,r1
68
        l.sub   r30,r31,r2
69
        l.sub   r29,r30,r3
70
        l.sub   r28,r29,r4
71
        l.sub   r27,r28,r5
72
        l.sub   r26,r27,r6
73
        l.sub   r25,r26,r7
74
        l.sub   r24,r25,r8
75
        l.sub   r23,r24,r9
76
        l.sub   r22,r23,r10
77
        l.sub   r21,r22,r11
78
        l.sub   r20,r21,r12
79
        l.sub   r19,r20,r13
80
        l.sub   r18,r19,r14
81
        l.sub   r17,r18,r15
82
        l.sub   r16,r17,r16
83
        l.movhi r31,0x0000
84
        l.ori   r31,r31,0x0040
85
 
86
        l.mtspr r0,r16,0x1234   /* Should be 0xffff0012 */
87
 
88
        l.sw    0(r31),r16
89
 
90
_mem:   l.movhi r3,0x1234
91
        l.ori   r3,r3,0x5678
92
 
93
        l.sw    4(r31),r3
94
 
95
        l.lbz   r4,4(r31)
96
        l.add   r8,r8,r4
97
        l.sb    11(r31),r4
98
        l.lbz   r4,5(r31)
99
        l.add   r8,r8,r4
100
        l.sb    10(r31),r4
101
        l.lbz   r4,6(r31)
102
        l.add   r8,r8,r4
103
        l.sb    9(r31),r4
104
        l.lbz   r4,7(r31)
105
        l.add   r8,r8,r4
106
        l.sb    8(r31),r4
107
 
108
        l.lbs   r4,8(r31)
109
        l.add   r8,r8,r4
110
        l.sb    7(r31),r4
111
        l.lbs   r4,9(r31)
112
        l.add   r8,r8,r4
113
        l.sb    6(r31),r4
114
        l.lbs   r4,10(r31)
115
        l.add   r8,r8,r4
116
        l.sb    5(r31),r4
117
        l.lbs   r4,11(r31)
118
        l.add   r8,r8,r4
119
        l.sb    4(r31),r4
120
 
121
        l.lhz   r4,4(r31)
122
        l.add   r8,r8,r4
123
        l.sh    10(r31),r4
124
        l.lhz   r4,6(r31)
125
        l.add   r8,r8,r4
126
        l.sh    8(r31),r4
127
 
128
        l.lhs   r4,8(r31)
129
        l.add   r8,r8,r4
130
        l.sh    6(r31),r4
131
        l.lhs   r4,10(r31)
132
        l.add   r8,r8,r4
133
        l.sh    4(r31),r4
134
 
135
        l.lwz   r4,4(r31)
136
        l.add   r8,r8,r4
137
 
138
        l.mtspr r0,r8,0x1234   /* Should be 0x12352af7 */
139
 
140
        l.lwz   r9,0(r31)
141
        l.add   r8,r9,r8
142
        l.sw    0(r31),r8
143
 
144
_arith:
145
        l.addi  r3,r0,1
146
        l.addi  r4,r0,2
147
        l.addi  r5,r0,-1
148
        l.addi  r6,r0,-1
149
        l.addi  r8,r0,0
150
 
151
        l.sub   r7,r5,r3
152
        l.sub   r8,r3,r5
153
        l.add   r8,r8,r7
154
 
155
#       l.div   r7,r7,r4
156
        l.add   r9,r3,r4
157
        l.mul   r7,r9,r7
158
#       l.divu  r7,r7,r4
159
        l.add   r8,r8,r7
160
 
161
        l.mtspr r0,r8,0x1234   /* Should be 0x7ffffffe */
162
 
163
        l.lwz   r9,0(r31)
164
        l.add   r8,r9,r8
165
        l.sw    0(r31),r8
166
 
167
_log:
168
        l.addi  r3,r0,1
169
        l.addi  r4,r0,2
170
        l.addi  r5,r0,-1
171
        l.addi  r6,r0,-1
172
        l.addi  r8,r0,0
173
 
174
        l.andi  r8,r8,1
175
        l.and   r8,r8,r3
176
 
177
        l.xori  r8,r5,0xa5a5
178
        l.xor   r8,r8,r5
179
 
180
        l.ori   r8,r8,2
181
        l.or    r8,r8,r4
182
 
183
        l.mtspr r0,r8,0x1234   /* Should be 0xffffa5a7 */
184
 
185
        l.lwz   r9,0(r31)
186
        l.add   r8,r9,r8
187
        l.sw    0(r31),r8
188
 
189
_shift:
190
        l.addi  r3,r0,1
191
        l.addi  r4,r0,2
192
        l.addi  r5,r0,-1
193
        l.addi  r6,r0,-1
194
        l.addi  r8,r0,0
195
 
196
        l.slli  r8,r5,6
197
        l.sll   r8,r8,r4
198
 
199
        l.srli  r8,r8,6
200
        l.srl   r8,r8,r4
201
 
202
        l.srai  r8,r8,2
203
        l.sra   r8,r8,r4
204
 
205
        l.mtspr r0,r8,0x1234   /* Should be 0x000fffff */
206
 
207
        l.lwz   r9,0(r31)
208
        l.add   r8,r9,r8
209
        l.sw    0(r31),r8
210
 
211
_flag:
212
        l.addi  r3,r0,1
213
        l.addi  r4,r0,-2
214
        l.addi  r8,r0,0
215
 
216
        l.sfeq  r3,r3
217
        l.mfspr r5,r0,17
218
        l.andi  r4,r5,0x200
219
        l.add   r8,r8,r4
220
 
221
        l.sfeq  r3,r4
222
        l.mfspr r5,r0,17
223
        l.andi  r4,r5,0x200
224
        l.add   r8,r8,r4
225
 
226
        l.sfeqi r3,1
227
        l.mfspr r5,r0,17
228
        l.andi  r4,r5,0x200
229
        l.add   r8,r8,r4
230
 
231
        l.sfeqi r3,-2
232
        l.mfspr r5,r0,17
233
        l.andi  r4,r5,0x200
234
        l.add   r8,r8,r4
235
 
236
        l.sfne  r3,r3
237
        l.mfspr r5,r0,17
238
        l.andi  r4,r5,0x200
239
        l.add   r8,r8,r4
240
 
241
        l.sfne  r3,r4
242
        l.mfspr r5,r0,17
243
        l.andi  r4,r5,0x200
244
        l.add   r8,r8,r4
245
 
246
        l.sfnei r3,1
247
        l.mfspr r5,r0,17
248
        l.andi  r4,r5,0x200
249
        l.add   r8,r8,r4
250
 
251
        l.sfnei r3,-2
252
        l.mfspr r5,r0,17
253
        l.andi  r4,r5,0x200
254
        l.add   r8,r8,r4
255
 
256
        l.sfgtu r3,r3
257
        l.mfspr r5,r0,17
258
        l.andi  r4,r5,0x200
259
        l.add   r8,r8,r4
260
 
261
        l.sfgtu r3,r4
262
        l.mfspr r5,r0,17
263
        l.andi  r4,r5,0x200
264
        l.add   r8,r8,r4
265
 
266
        l.sfgtui        r3,1
267
        l.mfspr r5,r0,17
268
        l.andi  r4,r5,0x200
269
        l.add   r8,r8,r4
270
 
271
        l.sfgtui        r3,-2
272
        l.mfspr r5,r0,17
273
        l.andi  r4,r5,0x200
274
        l.add   r8,r8,r4
275
 
276
        l.sfgeu r3,r3
277
        l.mfspr r5,r0,17
278
        l.andi  r4,r5,0x200
279
        l.add   r8,r8,r4
280
 
281
        l.sfgeu r3,r4
282
        l.mfspr r5,r0,17
283
        l.andi  r4,r5,0x200
284
        l.add   r8,r8,r4
285
 
286
        l.sfgeui        r3,1
287
        l.mfspr r5,r0,17
288
        l.andi  r4,r5,0x200
289
        l.add   r8,r8,r4
290
 
291
        l.sfgeui        r3,-2
292
        l.mfspr r5,r0,17
293
        l.andi  r4,r5,0x200
294
        l.add   r8,r8,r4
295
 
296
        l.sfltu r3,r3
297
        l.mfspr r5,r0,17
298
        l.andi  r4,r5,0x200
299
        l.add   r8,r8,r4
300
 
301
        l.sfltu r3,r4
302
        l.mfspr r5,r0,17
303
        l.andi  r4,r5,0x200
304
        l.add   r8,r8,r4
305
 
306
        l.sfltui        r3,1
307
        l.mfspr r5,r0,17
308
        l.andi  r4,r5,0x200
309
        l.add   r8,r8,r4
310
 
311
        l.sfltui        r3,-2
312
        l.mfspr r5,r0,17
313
        l.andi  r4,r5,0x200
314
        l.add   r8,r8,r4
315
 
316
        l.sfleu r3,r3
317
        l.mfspr r5,r0,17
318
        l.andi  r4,r5,0x200
319
        l.add   r8,r8,r4
320
 
321
        l.sfleu r3,r4
322
        l.mfspr r5,r0,17
323
        l.andi  r4,r5,0x200
324
        l.add   r8,r8,r4
325
 
326
        l.sfleui        r3,1
327
        l.mfspr r5,r0,17
328
        l.andi  r4,r5,0x200
329
        l.add   r8,r8,r4
330
 
331
        l.sfleui        r3,-2
332
        l.mfspr r5,r0,17
333
        l.andi  r4,r5,0x200
334
        l.add   r8,r8,r4
335
 
336
        l.sfgts r3,r3
337
        l.mfspr r5,r0,17
338
        l.andi  r4,r5,0x200
339
        l.add   r8,r8,r4
340
 
341
        l.sfgts r3,r4
342
        l.mfspr r5,r0,17
343
        l.andi  r4,r5,0x200
344
        l.add   r8,r8,r4
345
 
346
        l.sfgtsi        r3,1
347
        l.mfspr r5,r0,17
348
        l.andi  r4,r5,0x200
349
        l.add   r8,r8,r4
350
 
351
        l.sfgtsi        r3,-2
352
        l.mfspr r5,r0,17
353
        l.andi  r4,r5,0x200
354
        l.add   r8,r8,r4
355
 
356
        l.sfges r3,r3
357
        l.mfspr r5,r0,17
358
        l.andi  r4,r5,0x200
359
        l.add   r8,r8,r4
360
 
361
        l.sfges r3,r4
362
        l.mfspr r5,r0,17
363
        l.andi  r4,r5,0x200
364
        l.add   r8,r8,r4
365
 
366
        l.sfgesi        r3,1
367
        l.mfspr r5,r0,17
368
        l.andi  r4,r5,0x200
369
        l.add   r8,r8,r4
370
 
371
        l.sfgesi        r3,-2
372
        l.mfspr r5,r0,17
373
        l.andi  r4,r5,0x200
374
        l.add   r8,r8,r4
375
 
376
        l.sflts r3,r3
377
        l.mfspr r5,r0,17
378
        l.andi  r4,r5,0x200
379
        l.add   r8,r8,r4
380
 
381
        l.sflts r3,r4
382
        l.mfspr r5,r0,17
383
        l.andi  r4,r5,0x200
384
        l.add   r8,r8,r4
385
 
386
        l.sfltsi        r3,1
387
        l.mfspr r5,r0,17
388
        l.andi  r4,r5,0x200
389
        l.add   r8,r8,r4
390
 
391
        l.sfltsi        r3,-2
392
        l.mfspr r5,r0,17
393
        l.andi  r4,r5,0x200
394
        l.add   r8,r8,r4
395
 
396
        l.sfles r3,r3
397
        l.mfspr r5,r0,17
398
        l.andi  r4,r5,0x200
399
        l.add   r8,r8,r4
400
 
401
        l.sfles r3,r4
402
        l.mfspr r5,r0,17
403
        l.andi  r4,r5,0x200
404
        l.add   r8,r8,r4
405
 
406
        l.sflesi        r3,1
407
        l.mfspr r5,r0,17
408
        l.andi  r4,r5,0x200
409
        l.add   r8,r8,r4
410
 
411
        l.sflesi        r3,-2
412
        l.mfspr r5,r0,17
413
        l.andi  r4,r5,0x200
414
        l.add   r8,r8,r4
415
 
416
        l.mtspr r0,r8,0x1234   /* Should be 0x00002800 */
417
 
418
        l.lwz   r9,0(r31)
419
        l.add   r8,r9,r8
420
        l.sw    0(r31),r8
421
 
422
_jump:
423
        l.addi  r8,r0,0
424
 
425
        l.j     _T1
426
        l.addi  r8,r8,1
427
 
428
_T2:    l.or    r10,r0,r9
429
        l.jalr  r10
430
        l.addi  r8,r8,1
431
 
432
_T1:    l.jal   _T2
433
        l.addi  r8,r8,1
434
 
435
        l.sfeqi r0,0
436
        l.bf    _T3
437
        l.addi  r8,r8,1
438
 
439
_T3:    l.sfeqi r0,1
440
        l.bf    _T4
441
        l.addi  r8,r8,1
442
 
443
        l.addi  r8,r8,1
444
 
445
_T4:    l.sfeqi r0,0
446
        l.bnf    _T5
447
        l.addi  r8,r8,1
448
 
449
        l.addi  r8,r8,1
450
 
451
_T5:    l.sfeqi r0,1
452
        l.bnf    _T6
453
        l.addi  r8,r8,1
454
 
455
        l.addi  r8,r8,1
456
 
457
_T6:    l.movhi r3,hi(_T7)
458
        l.ori  r3,r3,lo(_T7)
459
        l.mtspr r0,r3,32
460
        l.mfspr r5,r0,17
461
        l.mtspr r0,r5,64
462
        l.rfe
463
        l.addi  r8,r8,1
464
 
465
        l.addi  r8,r8,1
466
 
467
_T7:    l.mtspr r0,r8,0x1234   /* Should be 0x00000000a */
468
 
469
        l.lwz   r9,0(r31)
470
        l.add   r8,r9,r8
471
        l.sw    0(r31),r8
472
 
473
        l.lwz   r9,0(r31)
474
        l.movhi r3,0xcc69
475
        l.ori   r3,r3,0xe5fb
476
        l.add   r3,r8,r3        /* Should be 0xdeaddead */
477
 
478
        /* and where is stack supposed to be ??? */
479
        l.movhi r1,hi(_tmp_stack)
480
        l.ori   r1,r1,lo(_tmp_stack)
481
        l.jal   _report
482
 
483
        l.nop
484 52 julius
        l.jal   _or32_exit
485 25 julius
        l.nop
486
        l.nop
487
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.