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[/] [test_project/] [trunk/] [sw/] [except/] [except_test_s.S] - Blame information for rev 27

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/* Support file for c based tests */
 
#include "spr_defs.h"
#include "board.h"
#include "mc.h"
 
        .global _except_basic
        .global _lo_dmmu_en
        .global _lo_immu_en
        .global _call
        .global _call_with_int
        .global _load_acc_32
        .global _load_acc_16
        .global _store_acc_32
        .global _store_acc_16
        .global _load_b_acc_32
        .global _trap
        .global _b_trap
        .global _range
        .global _b_range
        .global _int_trigger
        .global _int_loop
        .global _jump_back
 
        .section .vectors, "ax"
        .extern _reset_support
        .extern _c_reset
        .extern _excpt_buserr
        .extern _excpt_dpfault
        .extern _excpt_ipfault
        .extern _excpt_tick
        .extern _excpt_align
        .extern _excpt_illinsn
        .extern _excpt_int
        .extern _excpt_dtlbmiss
        .extern _excpt_itlbmiss
        .extern _excpt_range
        .extern _excpt_syscall
        .extern _excpt_break
        .extern _excpt_trap
 
        .org    0x200
_buserr_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_buserr)
        l.ori   r10,r10,lo(_excpt_buserr)
        l.lwz   r10,0x0(r10)
        l.jr    r10
        l.nop
 
        .org    0x300
_dpfault_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_dpfault)
        l.ori   r10,r10,lo(_excpt_dpfault)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x400
_ipfault_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_ipfault)
        l.ori   r10,r10,lo(_excpt_ipfault)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x500
_tick_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_tick)
        l.ori   r10,r10,lo(_excpt_tick)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x600
_align_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_align)
        l.ori   r10,r10,lo(_excpt_align)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x700
_illinsn_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_illinsn)
        l.ori   r10,r10,lo(_excpt_illinsn)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x800
_int_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_int)
        l.ori   r10,r10,lo(_excpt_int)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x900
_dtlbmiss_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_dtlbmiss)
        l.ori   r10,r10,lo(_excpt_dtlbmiss)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xa00
_itlbmiss_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_itlbmiss)
        l.ori   r10,r10,lo(_excpt_itlbmiss)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xb00
_range_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_range)
        l.ori   r10,r10,lo(_excpt_range)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xc00
_syscall_vector:
        l.nop
        l.addi  r3,r3,4
 
        l.mfspr r4,r0,SPR_SR
        l.andi  r4,r4,7
        l.add   r6,r0,r4
 
        l.mfspr r4,r0,SPR_EPCR_BASE
        l.movhi r5,hi(_sys1)
        l.ori r5,r5,lo(_sys1)
        l.sub r5,r4,r5
 
        l.mfspr r4,r0,SPR_ESR_BASE  /* ESR - set supvisor mode */
        l.ori r4,r4,SPR_SR_SM
        l.mtspr r0,r4,SPR_ESR_BASE
 
        l.movhi r4,hi(_sys2)
        l.ori r4,r4,lo(_sys2)
        l.mtspr r0,r4,SPR_EPCR_BASE
 
        l.rfe
        l.addi  r3,r3,8
 
        .org    0xd00
_break_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_break)
        l.ori   r10,r10,lo(_excpt_break)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xe00
_trap_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_trap)
        l.ori   r10,r10,lo(_excpt_trap)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
store_regs:
        l.sw    0x00(r1),r3
        l.sw    0x04(r1),r4
        l.sw    0x08(r1),r5
        l.sw    0x0c(r1),r6
        l.sw    0x10(r1),r7
        l.sw    0x14(r1),r8
        l.sw    0x1c(r1),r10
        l.sw    0x20(r1),r11
        l.sw    0x24(r1),r12
        l.sw    0x28(r1),r13
        l.sw    0x2c(r1),r14
        l.sw    0x30(r1),r15
        l.sw    0x34(r1),r16
        l.sw    0x38(r1),r17
        l.sw    0x3c(r1),r18
        l.sw    0x40(r1),r19
        l.sw    0x44(r1),r20
        l.sw    0x48(r1),r21
        l.sw    0x4c(r1),r22
        l.sw    0x50(r1),r23
        l.sw    0x54(r1),r24
        l.sw    0x58(r1),r25
        l.sw    0x5c(r1),r26
        l.sw    0x60(r1),r27
        l.sw    0x64(r1),r28
        l.sw    0x68(r1),r29
        l.sw    0x6c(r1),r30
        l.sw    0x70(r1),r31
        l.jr    r9
        l.nop
 
end_except:
        l.lwz   r3,0x00(r1)
        l.lwz   r4,0x04(r1)
        l.lwz   r5,0x08(r1)
        l.lwz   r6,0x0c(r1)
        l.lwz   r7,0x10(r1)
        l.lwz   r8,0x14(r1)
        l.lwz   r9,0x18(r1)
        l.lwz   r10,0x1c(r1)
        l.lwz   r11,0x20(r1)
        l.lwz   r12,0x24(r1)
        l.lwz   r13,0x28(r1)
        l.lwz   r14,0x2c(r1)
        l.lwz   r15,0x30(r1)
        l.lwz   r16,0x34(r1)
        l.lwz   r17,0x38(r1)
        l.lwz   r18,0x3c(r1)
        l.lwz   r19,0x40(r1)
        l.lwz   r20,0x44(r1)
        l.lwz   r21,0x48(r1)
        l.lwz   r22,0x4c(r1)
        l.lwz   r23,0x50(r1)
        l.lwz   r24,0x54(r1)
        l.lwz   r25,0x58(r1)
        l.lwz   r26,0x5c(r1)
        l.lwz   r27,0x60(r1)
        l.lwz   r28,0x64(r1)
        l.lwz   r29,0x68(r1)
        l.lwz   r30,0x6c(r1)
        l.lwz   r31,0x70(r1)
        l.addi  r1,r1,116
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
  .section .text
 
_except_basic:
_sys1:
        l.addi  r3,r0,-2  /* Enable exceptiom recognition and external interrupt,set user mode */
        l.mfspr r4,r0,SPR_SR
        l.and   r4,r4,r3
        l.ori   r4,r4,(SPR_SR_IEE|SPR_SR_TEE)
        l.mtspr r0,r4,SPR_SR
 
        l.addi  r3,r0,0
        l.sys   1
        l.addi  r3,r3,2
 
_sys2:
        l.addi  r11,r0,0
 
        l.mfspr r4,r0,SPR_SR  /* Check SR */
        l.andi  r4,r4,(SPR_SR_IEE|SPR_SR_TEE|SPR_SR_SM)
        l.sfeqi r4,(SPR_SR_IEE|SPR_SR_TEE|SPR_SR_SM)
        l.bf    1f
        l.nop
        l.addi  r11,r11,1
1:
        l.sfeqi r3,4          /* Check if l.sys or l.rfe has delay slot */
        l.bf    1f
        l.nop
        l.addi  r11,r11,2
1:
        l.sfeqi r5,0x1c       /* Check the EPCR */
        l.bf    1f
        l.nop
        l.addi  r11,r11,4
1:
        l.sfeqi r6,SPR_SR_SM  /* Check the SR when exception is taken */
        l.bf    1f
        l.nop
        l.addi  r11,r11,8
1:
        l.jr    r9
        l.nop
 
_lo_dmmu_en:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_DME
        l.mtspr r0,r3,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
_lo_immu_en:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_IME
        l.mtspr r0,r3,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
_call:
        l.addi  r11,r0,0
        l.jr    r3
        l.nop
 
_call_with_int:
        l.mfspr r8,r0,SPR_SR
        l.ori   r8,r8,SPR_SR_TEE
        l.mtspr r0,r8,SPR_ESR_BASE
        l.mtspr r0,r3,SPR_EPCR_BASE
        l.rfe
 
_load_acc_32:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.lwz   r11,0(r4)
        l.jr    r9
        l.nop
 
_load_acc_16:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.lhz   r11,0(r4)
        l.jr    r9
        l.nop
 
_store_acc_32:
        l.movhi r3,hi(0x12345678)
        l.ori   r3,r3,lo(0x12345678)
        l.sw    0(r4),r3
        l.jr    r9
        l.nop
 
_store_acc_16:
        l.movhi r3,hi(0x12345678)
        l.ori   r3,r3,lo(0x12345678)
        l.sh    0(r4),r3
        l.jr    r9
        l.nop
 
_load_b_acc_32:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.jr    r9
        l.lwz   r11,0(r4)
 
_b_trap:
        l.jr    r9
_trap:
        l.trap  1
        l.jr    r9
        l.nop
 
_b_range:
        l.jr    r9
_range:
        l.addi  r3,r0,-1
        l.jr    r9
        l.nop
 
_int_trigger:
        l.addi  r11,r0,0
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_TEE
        l.mtspr r0,r3,SPR_SR
        l.addi  r11,r11,1
 
_int_loop:
        l.j     _int_loop
        l.lwz   r5,0(r4);
 
_jump_back:
        l.addi  r11,r0,0
        l.jr    r9
        l.addi  r11,r11,1
 

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[/] [test_project/] [trunk/] [sw/] [except/] [except_test_s.S] - Blame information for rev 27

Line No.	Rev	Author	Line
1	25	julius	`/* Support file for c based tests */`
2
3			`#include "spr_defs.h"`
4			`#include "board.h"`
5			`#include "mc.h"`
6
7			`.global _except_basic`
8			`.global _lo_dmmu_en`
9			`.global _lo_immu_en`
10			`.global _call`
11			`.global _call_with_int`
12			`.global _load_acc_32`
13			`.global _load_acc_16`
14			`.global _store_acc_32`
15			`.global _store_acc_16`
16			`.global _load_b_acc_32`
17			`.global _trap`
18			`.global _b_trap`
19			`.global _range`
20			`.global _b_range`
21			`.global _int_trigger`
22			`.global _int_loop`
23			`.global _jump_back`
24
25			`.section .vectors, "ax"`
26			`.extern _reset_support`
27			`.extern _c_reset`
28			`.extern _excpt_buserr`
29			`.extern _excpt_dpfault`
30			`.extern _excpt_ipfault`
31			`.extern _excpt_tick`
32			`.extern _excpt_align`
33			`.extern _excpt_illinsn`
34			`.extern _excpt_int`
35			`.extern _excpt_dtlbmiss`
36			`.extern _excpt_itlbmiss`
37			`.extern _excpt_range`
38			`.extern _excpt_syscall`
39			`.extern _excpt_break`
40			`.extern _excpt_trap`
41
42			`.org 0x200`
43			`_buserr_vector:`
44			`l.nop`
45			`l.addi r1,r1,-116`
46			`l.sw 0x18(r1),r9`
47			`l.jal store_regs`
48			`l.nop`
49
50			`l.mfspr r3,r0,SPR_EPCR_BASE`
51			`l.movhi r4,hi(_except_pc)`
52			`l.ori r4,r4,lo(_except_pc)`
53			`l.sw 0(r4),r3`
54
55			`l.mfspr r3,r0,SPR_EEAR_BASE`
56			`l.movhi r4,hi(_except_ea)`
57			`l.ori r4,r4,lo(_except_ea)`
58			`l.sw 0(r4),r3`
59
60			`l.movhi r9,hi(end_except)`
61			`l.ori r9,r9,lo(end_except)`
62			`l.movhi r10,hi(_excpt_buserr)`
63			`l.ori r10,r10,lo(_excpt_buserr)`
64			`l.lwz r10,0x0(r10)`
65			`l.jr r10`
66			`l.nop`
67
68			`.org 0x300`
69			`_dpfault_vector:`
70			`l.nop`
71			`l.addi r1,r1,-116`
72			`l.sw 0x18(r1),r9`
73			`l.jal store_regs`
74			`l.nop`
75
76			`l.mfspr r3,r0,SPR_EPCR_BASE`
77			`l.movhi r4,hi(_except_pc)`
78			`l.ori r4,r4,lo(_except_pc)`
79			`l.sw 0(r4),r3`
80
81			`l.mfspr r3,r0,SPR_EEAR_BASE`
82			`l.movhi r4,hi(_except_ea)`
83			`l.ori r4,r4,lo(_except_ea)`
84			`l.sw 0(r4),r3`
85
86			`l.movhi r9,hi(end_except)`
87			`l.ori r9,r9,lo(end_except)`
88			`l.movhi r10,hi(_excpt_dpfault)`
89			`l.ori r10,r10,lo(_excpt_dpfault)`
90			`l.lwz r10,0(r10)`
91			`l.jr r10`
92			`l.nop`
93
94			`.org 0x400`
95			`_ipfault_vector:`
96			`l.nop`
97			`l.addi r1,r1,-116`
98			`l.sw 0x18(r1),r9`
99			`l.jal store_regs`
100			`l.nop`
101
102			`l.mfspr r3,r0,SPR_EPCR_BASE`
103			`l.movhi r4,hi(_except_pc)`
104			`l.ori r4,r4,lo(_except_pc)`
105			`l.sw 0(r4),r3`
106
107			`l.mfspr r3,r0,SPR_EEAR_BASE`
108			`l.movhi r4,hi(_except_ea)`
109			`l.ori r4,r4,lo(_except_ea)`
110			`l.sw 0(r4),r3`
111
112			`l.movhi r9,hi(end_except)`
113			`l.ori r9,r9,lo(end_except)`
114			`l.movhi r10,hi(_excpt_ipfault)`
115			`l.ori r10,r10,lo(_excpt_ipfault)`
116			`l.lwz r10,0(r10)`
117			`l.jr r10`
118			`l.nop`
119
120			`.org 0x500`
121			`_tick_vector:`
122			`l.nop`
123			`l.addi r1,r1,-116`
124			`l.sw 0x18(r1),r9`
125			`l.jal store_regs`
126			`l.nop`
127
128			`l.mfspr r3,r0,SPR_EPCR_BASE`
129			`l.movhi r4,hi(_except_pc)`
130			`l.ori r4,r4,lo(_except_pc)`
131			`l.sw 0(r4),r3`
132
133			`l.mfspr r3,r0,SPR_EEAR_BASE`
134			`l.movhi r4,hi(_except_ea)`
135			`l.ori r4,r4,lo(_except_ea)`
136			`l.sw 0(r4),r3`
137
138			`l.movhi r9,hi(end_except)`
139			`l.ori r9,r9,lo(end_except)`
140			`l.movhi r10,hi(_excpt_tick)`
141			`l.ori r10,r10,lo(_excpt_tick)`
142			`l.lwz r10,0(r10)`
143			`l.jr r10`
144			`l.nop`
145
146			`.org 0x600`
147			`_align_vector:`
148			`l.nop`
149			`l.addi r1,r1,-116`
150			`l.sw 0x18(r1),r9`
151			`l.jal store_regs`
152			`l.nop`
153
154			`l.mfspr r3,r0,SPR_EPCR_BASE`
155			`l.movhi r4,hi(_except_pc)`
156			`l.ori r4,r4,lo(_except_pc)`
157			`l.sw 0(r4),r3`
158
159			`l.mfspr r3,r0,SPR_EEAR_BASE`
160			`l.movhi r4,hi(_except_ea)`
161			`l.ori r4,r4,lo(_except_ea)`
162			`l.sw 0(r4),r3`
163
164			`l.movhi r9,hi(end_except)`
165			`l.ori r9,r9,lo(end_except)`
166			`l.movhi r10,hi(_excpt_align)`
167			`l.ori r10,r10,lo(_excpt_align)`
168			`l.lwz r10,0(r10)`
169			`l.jr r10`
170			`l.nop`
171
172			`.org 0x700`
173			`_illinsn_vector:`
174			`l.nop`
175			`l.addi r1,r1,-116`
176			`l.sw 0x18(r1),r9`
177			`l.jal store_regs`
178			`l.nop`
179
180			`l.mfspr r3,r0,SPR_EPCR_BASE`
181			`l.movhi r4,hi(_except_pc)`
182			`l.ori r4,r4,lo(_except_pc)`
183			`l.sw 0(r4),r3`
184
185			`l.mfspr r3,r0,SPR_EEAR_BASE`
186			`l.movhi r4,hi(_except_ea)`
187			`l.ori r4,r4,lo(_except_ea)`
188			`l.sw 0(r4),r3`
189
190			`l.movhi r9,hi(end_except)`
191			`l.ori r9,r9,lo(end_except)`
192			`l.movhi r10,hi(_excpt_illinsn)`
193			`l.ori r10,r10,lo(_excpt_illinsn)`
194			`l.lwz r10,0(r10)`
195			`l.jr r10`
196			`l.nop`
197
198			`.org 0x800`
199			`_int_vector:`
200			`l.nop`
201			`l.addi r1,r1,-116`
202			`l.sw 0x18(r1),r9`
203			`l.jal store_regs`
204			`l.nop`
205
206			`l.mfspr r3,r0,SPR_EPCR_BASE`
207			`l.movhi r4,hi(_except_pc)`
208			`l.ori r4,r4,lo(_except_pc)`
209			`l.sw 0(r4),r3`
210
211			`l.mfspr r3,r0,SPR_EEAR_BASE`
212			`l.movhi r4,hi(_except_ea)`
213			`l.ori r4,r4,lo(_except_ea)`
214			`l.sw 0(r4),r3`
215
216			`l.movhi r9,hi(end_except)`
217			`l.ori r9,r9,lo(end_except)`
218			`l.movhi r10,hi(_excpt_int)`
219			`l.ori r10,r10,lo(_excpt_int)`
220			`l.lwz r10,0(r10)`
221			`l.jr r10`
222			`l.nop`
223
224			`.org 0x900`
225			`_dtlbmiss_vector:`
226			`l.nop`
227			`l.addi r1,r1,-116`
228			`l.sw 0x18(r1),r9`
229			`l.jal store_regs`
230			`l.nop`
231
232			`l.mfspr r3,r0,SPR_EPCR_BASE`
233			`l.movhi r4,hi(_except_pc)`
234			`l.ori r4,r4,lo(_except_pc)`
235			`l.sw 0(r4),r3`
236
237			`l.mfspr r3,r0,SPR_EEAR_BASE`
238			`l.movhi r4,hi(_except_ea)`
239			`l.ori r4,r4,lo(_except_ea)`
240			`l.sw 0(r4),r3`
241
242			`l.movhi r9,hi(end_except)`
243			`l.ori r9,r9,lo(end_except)`
244			`l.movhi r10,hi(_excpt_dtlbmiss)`
245			`l.ori r10,r10,lo(_excpt_dtlbmiss)`
246			`l.lwz r10,0(r10)`
247			`l.jr r10`
248			`l.nop`
249
250			`.org 0xa00`
251			`_itlbmiss_vector:`
252			`l.nop`
253			`l.addi r1,r1,-116`
254			`l.sw 0x18(r1),r9`
255			`l.jal store_regs`
256			`l.nop`
257
258			`l.mfspr r3,r0,SPR_EPCR_BASE`
259			`l.movhi r4,hi(_except_pc)`
260			`l.ori r4,r4,lo(_except_pc)`
261			`l.sw 0(r4),r3`
262
263			`l.mfspr r3,r0,SPR_EEAR_BASE`
264			`l.movhi r4,hi(_except_ea)`
265			`l.ori r4,r4,lo(_except_ea)`
266			`l.sw 0(r4),r3`
267
268			`l.movhi r9,hi(end_except)`
269			`l.ori r9,r9,lo(end_except)`
270			`l.movhi r10,hi(_excpt_itlbmiss)`
271			`l.ori r10,r10,lo(_excpt_itlbmiss)`
272			`l.lwz r10,0(r10)`
273			`l.jr r10`
274			`l.nop`
275
276			`.org 0xb00`
277			`_range_vector:`
278			`l.nop`
279			`l.addi r1,r1,-116`
280			`l.sw 0x18(r1),r9`
281			`l.jal store_regs`
282			`l.nop`
283
284			`l.mfspr r3,r0,SPR_EPCR_BASE`
285			`l.movhi r4,hi(_except_pc)`
286			`l.ori r4,r4,lo(_except_pc)`
287			`l.sw 0(r4),r3`
288
289			`l.mfspr r3,r0,SPR_EEAR_BASE`
290			`l.movhi r4,hi(_except_ea)`
291			`l.ori r4,r4,lo(_except_ea)`
292			`l.sw 0(r4),r3`
293
294			`l.movhi r9,hi(end_except)`
295			`l.ori r9,r9,lo(end_except)`
296			`l.movhi r10,hi(_excpt_range)`
297			`l.ori r10,r10,lo(_excpt_range)`
298			`l.lwz r10,0(r10)`
299			`l.jr r10`
300			`l.nop`
301
302			`.org 0xc00`
303			`_syscall_vector:`
304			`l.nop`
305			`l.addi r3,r3,4`
306
307			`l.mfspr r4,r0,SPR_SR`
308			`l.andi r4,r4,7`
309			`l.add r6,r0,r4`
310
311			`l.mfspr r4,r0,SPR_EPCR_BASE`
312			`l.movhi r5,hi(_sys1)`
313			`l.ori r5,r5,lo(_sys1)`
314			`l.sub r5,r4,r5`
315
316			`l.mfspr r4,r0,SPR_ESR_BASE /* ESR - set supvisor mode */`
317			`l.ori r4,r4,SPR_SR_SM`
318			`l.mtspr r0,r4,SPR_ESR_BASE`
319
320			`l.movhi r4,hi(_sys2)`
321			`l.ori r4,r4,lo(_sys2)`
322			`l.mtspr r0,r4,SPR_EPCR_BASE`
323
324			`l.rfe`
325			`l.addi r3,r3,8`
326
327			`.org 0xd00`
328			`_break_vector:`
329			`l.nop`
330			`l.addi r1,r1,-116`
331			`l.sw 0x18(r1),r9`
332			`l.jal store_regs`
333			`l.nop`
334
335			`l.mfspr r3,r0,SPR_EPCR_BASE`
336			`l.movhi r4,hi(_except_pc)`
337			`l.ori r4,r4,lo(_except_pc)`
338			`l.sw 0(r4),r3`
339
340			`l.mfspr r3,r0,SPR_EEAR_BASE`
341			`l.movhi r4,hi(_except_ea)`
342			`l.ori r4,r4,lo(_except_ea)`
343			`l.sw 0(r4),r3`
344
345			`l.movhi r9,hi(end_except)`
346			`l.ori r9,r9,lo(end_except)`
347			`l.movhi r10,hi(_excpt_break)`
348			`l.ori r10,r10,lo(_excpt_break)`
349			`l.lwz r10,0(r10)`
350			`l.jr r10`
351			`l.nop`
352
353			`.org 0xe00`
354			`_trap_vector:`
355			`l.nop`
356			`l.addi r1,r1,-116`
357			`l.sw 0x18(r1),r9`
358			`l.jal store_regs`
359			`l.nop`
360
361			`l.mfspr r3,r0,SPR_EPCR_BASE`
362			`l.movhi r4,hi(_except_pc)`
363			`l.ori r4,r4,lo(_except_pc)`
364			`l.sw 0(r4),r3`
365
366			`l.mfspr r3,r0,SPR_EEAR_BASE`
367			`l.movhi r4,hi(_except_ea)`
368			`l.ori r4,r4,lo(_except_ea)`
369			`l.sw 0(r4),r3`
370
371			`l.movhi r9,hi(end_except)`
372			`l.ori r9,r9,lo(end_except)`
373			`l.movhi r10,hi(_excpt_trap)`
374			`l.ori r10,r10,lo(_excpt_trap)`
375			`l.lwz r10,0(r10)`
376			`l.jr r10`
377			`l.nop`
378
379			`store_regs:`
380			`l.sw 0x00(r1),r3`
381			`l.sw 0x04(r1),r4`
382			`l.sw 0x08(r1),r5`
383			`l.sw 0x0c(r1),r6`
384			`l.sw 0x10(r1),r7`
385			`l.sw 0x14(r1),r8`
386			`l.sw 0x1c(r1),r10`
387			`l.sw 0x20(r1),r11`
388			`l.sw 0x24(r1),r12`
389			`l.sw 0x28(r1),r13`
390			`l.sw 0x2c(r1),r14`
391			`l.sw 0x30(r1),r15`
392			`l.sw 0x34(r1),r16`
393			`l.sw 0x38(r1),r17`
394			`l.sw 0x3c(r1),r18`
395			`l.sw 0x40(r1),r19`
396			`l.sw 0x44(r1),r20`
397			`l.sw 0x48(r1),r21`
398			`l.sw 0x4c(r1),r22`
399			`l.sw 0x50(r1),r23`
400			`l.sw 0x54(r1),r24`
401			`l.sw 0x58(r1),r25`
402			`l.sw 0x5c(r1),r26`
403			`l.sw 0x60(r1),r27`
404			`l.sw 0x64(r1),r28`
405			`l.sw 0x68(r1),r29`
406			`l.sw 0x6c(r1),r30`
407			`l.sw 0x70(r1),r31`
408			`l.jr r9`
409			`l.nop`
410
411			`end_except:`
412			`l.lwz r3,0x00(r1)`
413			`l.lwz r4,0x04(r1)`
414			`l.lwz r5,0x08(r1)`
415			`l.lwz r6,0x0c(r1)`
416			`l.lwz r7,0x10(r1)`
417			`l.lwz r8,0x14(r1)`
418			`l.lwz r9,0x18(r1)`
419			`l.lwz r10,0x1c(r1)`
420			`l.lwz r11,0x20(r1)`
421			`l.lwz r12,0x24(r1)`
422			`l.lwz r13,0x28(r1)`
423			`l.lwz r14,0x2c(r1)`
424			`l.lwz r15,0x30(r1)`
425			`l.lwz r16,0x34(r1)`
426			`l.lwz r17,0x38(r1)`
427			`l.lwz r18,0x3c(r1)`
428			`l.lwz r19,0x40(r1)`
429			`l.lwz r20,0x44(r1)`
430			`l.lwz r21,0x48(r1)`
431			`l.lwz r22,0x4c(r1)`
432			`l.lwz r23,0x50(r1)`
433			`l.lwz r24,0x54(r1)`
434			`l.lwz r25,0x58(r1)`
435			`l.lwz r26,0x5c(r1)`
436			`l.lwz r27,0x60(r1)`
437			`l.lwz r28,0x64(r1)`
438			`l.lwz r29,0x68(r1)`
439			`l.lwz r30,0x6c(r1)`
440			`l.lwz r31,0x70(r1)`
441			`l.addi r1,r1,116`
442			`l.mtspr r0,r9,SPR_EPCR_BASE`
443			`l.rfe`
444			`l.nop`
445
446			`.section .text`
447
448			`_except_basic:`
449			`_sys1:`
450			`l.addi r3,r0,-2 /* Enable exceptiom recognition and external interrupt,set user mode */`
451			`l.mfspr r4,r0,SPR_SR`
452			`l.and r4,r4,r3`
453			`l.ori r4,r4,(SPR_SR_IEE\|SPR_SR_TEE)`
454			`l.mtspr r0,r4,SPR_SR`
455
456			`l.addi r3,r0,0`
457			`l.sys 1`
458			`l.addi r3,r3,2`
459
460			`_sys2:`
461			`l.addi r11,r0,0`
462
463			`l.mfspr r4,r0,SPR_SR /* Check SR */`
464			`l.andi r4,r4,(SPR_SR_IEE\|SPR_SR_TEE\|SPR_SR_SM)`
465			`l.sfeqi r4,(SPR_SR_IEE\|SPR_SR_TEE\|SPR_SR_SM)`
466			`l.bf 1f`
467			`l.nop`
468			`l.addi r11,r11,1`
469			`1:`
470			`l.sfeqi r3,4 /* Check if l.sys or l.rfe has delay slot */`
471			`l.bf 1f`
472			`l.nop`
473			`l.addi r11,r11,2`
474			`1:`
475			`l.sfeqi r5,0x1c /* Check the EPCR */`
476			`l.bf 1f`
477			`l.nop`
478			`l.addi r11,r11,4`
479			`1:`
480			`l.sfeqi r6,SPR_SR_SM /* Check the SR when exception is taken */`
481			`l.bf 1f`
482			`l.nop`
483			`l.addi r11,r11,8`
484			`1:`
485			`l.jr r9`
486			`l.nop`
487
488			`_lo_dmmu_en:`
489			`l.mfspr r3,r0,SPR_SR`
490			`l.ori r3,r3,SPR_SR_DME`
491			`l.mtspr r0,r3,SPR_ESR_BASE`
492			`l.mtspr r0,r9,SPR_EPCR_BASE`
493			`l.rfe`
494			`l.nop`
495
496			`_lo_immu_en:`
497			`l.mfspr r3,r0,SPR_SR`
498			`l.ori r3,r3,SPR_SR_IME`
499			`l.mtspr r0,r3,SPR_ESR_BASE`
500			`l.mtspr r0,r9,SPR_EPCR_BASE`
501			`l.rfe`
502			`l.nop`
503
504			`_call:`
505			`l.addi r11,r0,0`
506			`l.jr r3`
507			`l.nop`
508
509			`_call_with_int:`
510			`l.mfspr r8,r0,SPR_SR`
511			`l.ori r8,r8,SPR_SR_TEE`
512			`l.mtspr r0,r8,SPR_ESR_BASE`
513			`l.mtspr r0,r3,SPR_EPCR_BASE`
514			`l.rfe`
515
516			`_load_acc_32:`
517			`l.movhi r11,hi(0x12345678)`
518			`l.ori r11,r11,lo(0x12345678)`
519			`l.lwz r11,0(r4)`
520			`l.jr r9`
521			`l.nop`
522
523			`_load_acc_16:`
524			`l.movhi r11,hi(0x12345678)`
525			`l.ori r11,r11,lo(0x12345678)`
526			`l.lhz r11,0(r4)`
527			`l.jr r9`
528			`l.nop`
529
530			`_store_acc_32:`
531			`l.movhi r3,hi(0x12345678)`
532			`l.ori r3,r3,lo(0x12345678)`
533			`l.sw 0(r4),r3`
534			`l.jr r9`
535			`l.nop`
536
537			`_store_acc_16:`
538			`l.movhi r3,hi(0x12345678)`
539			`l.ori r3,r3,lo(0x12345678)`
540			`l.sh 0(r4),r3`
541			`l.jr r9`
542			`l.nop`
543
544			`_load_b_acc_32:`
545			`l.movhi r11,hi(0x12345678)`
546			`l.ori r11,r11,lo(0x12345678)`
547			`l.jr r9`
548			`l.lwz r11,0(r4)`
549
550			`_b_trap:`
551			`l.jr r9`
552			`_trap:`
553			`l.trap 1`
554			`l.jr r9`
555			`l.nop`
556
557			`_b_range:`
558			`l.jr r9`
559			`_range:`
560			`l.addi r3,r0,-1`
561			`l.jr r9`
562			`l.nop`
563
564			`_int_trigger:`
565			`l.addi r11,r0,0`
566			`l.mfspr r3,r0,SPR_SR`
567			`l.ori r3,r3,SPR_SR_TEE`
568			`l.mtspr r0,r3,SPR_SR`
569			`l.addi r11,r11,1`
570
571			`_int_loop:`
572			`l.j _int_loop`
573			`l.lwz r5,0(r4);`
574
575			`_jump_back:`
576			`l.addi r11,r0,0`
577			`l.jr r9`
578			`l.addi r11,r11,1`
579