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[/] [test_project/] [trunk/] [sw/] [except/] [except_test_s.S] - Blame information for rev 34

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/* Support file for c based tests */
 
#include "spr_defs.h"
#include "board.h"
#include "mc.h"
 
        .global _except_basic
        .global _lo_dmmu_en
        .global _lo_immu_en
        .global _call
        .global _call_with_int
        .global _load_acc_32
        .global _load_acc_16
        .global _store_acc_32
        .global _store_acc_16
        .global _load_b_acc_32
        .global _trap
        .global _b_trap
        .global _range
        .global _b_range
        .global _int_trigger
        .global _int_loop
        .global _jump_back
 
        .section .vectors, "ax"
        .extern _reset_support
        .extern _c_reset
        .extern _excpt_buserr
        .extern _excpt_dpfault
        .extern _excpt_ipfault
        .extern _excpt_tick
        .extern _excpt_align
        .extern _excpt_illinsn
        .extern _excpt_int
        .extern _excpt_dtlbmiss
        .extern _excpt_itlbmiss
        .extern _excpt_range
        .extern _excpt_syscall
        .extern _excpt_break
        .extern _excpt_trap
 
        // Assuming .vectors is defined from 0x200 in the linker script
        .org    0x000
_buserr_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_buserr)
        l.ori   r10,r10,lo(_excpt_buserr)
        l.lwz   r10,0x0(r10)
        l.jr    r10
        l.nop
 
        .org    0x100
_dpfault_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_dpfault)
        l.ori   r10,r10,lo(_excpt_dpfault)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x200
_ipfault_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_ipfault)
        l.ori   r10,r10,lo(_excpt_ipfault)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x300
_tick_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_tick)
        l.ori   r10,r10,lo(_excpt_tick)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x400
_align_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_align)
        l.ori   r10,r10,lo(_excpt_align)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x500
_illinsn_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_illinsn)
        l.ori   r10,r10,lo(_excpt_illinsn)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x600
_int_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_int)
        l.ori   r10,r10,lo(_excpt_int)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x700
_dtlbmiss_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_dtlbmiss)
        l.ori   r10,r10,lo(_excpt_dtlbmiss)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x800
_itlbmiss_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_itlbmiss)
        l.ori   r10,r10,lo(_excpt_itlbmiss)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x900
_range_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_range)
        l.ori   r10,r10,lo(_excpt_range)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xa00
_syscall_vector:
        l.nop
        l.addi  r3,r3,4
 
        l.mfspr r4,r0,SPR_SR
        l.andi  r4,r4,7
        l.add   r6,r0,r4
 
        l.mfspr r4,r0,SPR_EPCR_BASE
        l.movhi r5,hi(_sys1)
        l.ori r5,r5,lo(_sys1)
        l.sub r5,r4,r5
 
        l.mfspr r4,r0,SPR_ESR_BASE  /* ESR - set supvisor mode */
        l.ori r4,r4,SPR_SR_SM
        l.mtspr r0,r4,SPR_ESR_BASE
 
        l.movhi r4,hi(_sys2)
        l.ori r4,r4,lo(_sys2)
        l.mtspr r0,r4,SPR_EPCR_BASE
 
        l.rfe
        l.addi  r3,r3,8
 
        .org    0xb00
_break_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_break)
        l.ori   r10,r10,lo(_excpt_break)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xc00
_trap_vector:
        l.nop
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_trap)
        l.ori   r10,r10,lo(_excpt_trap)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
store_regs:
        l.sw    0x00(r1),r3
        l.sw    0x04(r1),r4
        l.sw    0x08(r1),r5
        l.sw    0x0c(r1),r6
        l.sw    0x10(r1),r7
        l.sw    0x14(r1),r8
        l.sw    0x1c(r1),r10
        l.sw    0x20(r1),r11
        l.sw    0x24(r1),r12
        l.sw    0x28(r1),r13
        l.sw    0x2c(r1),r14
        l.sw    0x30(r1),r15
        l.sw    0x34(r1),r16
        l.sw    0x38(r1),r17
        l.sw    0x3c(r1),r18
        l.sw    0x40(r1),r19
        l.sw    0x44(r1),r20
        l.sw    0x48(r1),r21
        l.sw    0x4c(r1),r22
        l.sw    0x50(r1),r23
        l.sw    0x54(r1),r24
        l.sw    0x58(r1),r25
        l.sw    0x5c(r1),r26
        l.sw    0x60(r1),r27
        l.sw    0x64(r1),r28
        l.sw    0x68(r1),r29
        l.sw    0x6c(r1),r30
        l.sw    0x70(r1),r31
        l.jr    r9
        l.nop
 
end_except:
        l.lwz   r3,0x00(r1)
        l.lwz   r4,0x04(r1)
        l.lwz   r5,0x08(r1)
        l.lwz   r6,0x0c(r1)
        l.lwz   r7,0x10(r1)
        l.lwz   r8,0x14(r1)
        l.lwz   r9,0x18(r1)
        l.lwz   r10,0x1c(r1)
        l.lwz   r11,0x20(r1)
        l.lwz   r12,0x24(r1)
        l.lwz   r13,0x28(r1)
        l.lwz   r14,0x2c(r1)
        l.lwz   r15,0x30(r1)
        l.lwz   r16,0x34(r1)
        l.lwz   r17,0x38(r1)
        l.lwz   r18,0x3c(r1)
        l.lwz   r19,0x40(r1)
        l.lwz   r20,0x44(r1)
        l.lwz   r21,0x48(r1)
        l.lwz   r22,0x4c(r1)
        l.lwz   r23,0x50(r1)
        l.lwz   r24,0x54(r1)
        l.lwz   r25,0x58(r1)
        l.lwz   r26,0x5c(r1)
        l.lwz   r27,0x60(r1)
        l.lwz   r28,0x64(r1)
        l.lwz   r29,0x68(r1)
        l.lwz   r30,0x6c(r1)
        l.lwz   r31,0x70(r1)
        l.addi  r1,r1,116
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
  .section .text
 
_except_basic:
_sys1:
        l.addi  r3,r0,-2  /* Enable exceptiom recognition and external interrupt,set user mode */
        l.mfspr r4,r0,SPR_SR
        l.and   r4,r4,r3
        l.ori   r4,r4,(SPR_SR_IEE|SPR_SR_TEE)
        l.mtspr r0,r4,SPR_SR
 
        l.addi  r3,r0,0
        l.sys   1
        l.addi  r3,r3,2
 
_sys2:
        l.addi  r11,r0,0
 
        l.mfspr r4,r0,SPR_SR  /* Check SR */
        l.andi  r4,r4,(SPR_SR_IEE|SPR_SR_TEE|SPR_SR_SM)
        l.sfeqi r4,(SPR_SR_IEE|SPR_SR_TEE|SPR_SR_SM)
        l.bf    1f
        l.nop
        l.addi  r11,r11,1
1:
        l.sfeqi r3,4          /* Check if l.sys or l.rfe has delay slot */
        l.bf    1f
        l.nop
        l.addi  r11,r11,2
1:
        l.sfeqi r5,0x1c       /* Check the EPCR */
        l.bf    1f
        l.nop
        l.addi  r11,r11,4
1:
        l.sfeqi r6,SPR_SR_SM  /* Check the SR when exception is taken */
        l.bf    1f
        l.nop
        l.addi  r11,r11,8
1:
        l.jr    r9
        l.nop
 
_lo_dmmu_en:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_DME
        l.mtspr r0,r3,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
_lo_immu_en:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_IME
        l.mtspr r0,r3,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
_call:
        l.addi  r11,r0,0
        l.jr    r3
        l.nop
 
_call_with_int:
        l.mfspr r8,r0,SPR_SR
        l.ori   r8,r8,SPR_SR_TEE
        l.mtspr r0,r8,SPR_ESR_BASE
        l.mtspr r0,r3,SPR_EPCR_BASE
        l.rfe
 
_load_acc_32:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.lwz   r11,0(r4)
        l.jr    r9
        l.nop
 
_load_acc_16:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.lhz   r11,0(r4)
        l.jr    r9
        l.nop
 
_store_acc_32:
        l.movhi r3,hi(0x12345678)
        l.ori   r3,r3,lo(0x12345678)
        l.sw    0(r4),r3
        l.jr    r9
        l.nop
 
_store_acc_16:
        l.movhi r3,hi(0x12345678)
        l.ori   r3,r3,lo(0x12345678)
        l.sh    0(r4),r3
        l.jr    r9
        l.nop
 
_load_b_acc_32:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.jr    r9
        l.lwz   r11,0(r4)
 
_b_trap:
        l.jr    r9
_trap:
        l.trap  1
        l.jr    r9
        l.nop
 
_b_range:
        l.jr    r9
_range:
        l.addi  r3,r0,-1
        l.jr    r9
        l.nop
 
_int_trigger:
        l.addi  r11,r0,0
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_TEE
        l.mtspr r0,r3,SPR_SR
        l.addi  r11,r11,1
 
_int_loop:
        l.j     _int_loop
        l.lwz   r5,0(r4);
 
_jump_back:
        l.addi  r11,r0,0
        l.jr    r9
        l.addi  r11,r11,1
 

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[/] [test_project/] [trunk/] [sw/] [except/] [except_test_s.S] - Blame information for rev 34

Line No.	Rev	Author	Line
1	25	julius	`/* Support file for c based tests */`
2
3			`#include "spr_defs.h"`
4			`#include "board.h"`
5			`#include "mc.h"`
6
7			`.global _except_basic`
8			`.global _lo_dmmu_en`
9			`.global _lo_immu_en`
10			`.global _call`
11			`.global _call_with_int`
12			`.global _load_acc_32`
13			`.global _load_acc_16`
14			`.global _store_acc_32`
15			`.global _store_acc_16`
16			`.global _load_b_acc_32`
17			`.global _trap`
18			`.global _b_trap`
19			`.global _range`
20			`.global _b_range`
21			`.global _int_trigger`
22			`.global _int_loop`
23			`.global _jump_back`
24
25			`.section .vectors, "ax"`
26			`.extern _reset_support`
27			`.extern _c_reset`
28			`.extern _excpt_buserr`
29			`.extern _excpt_dpfault`
30			`.extern _excpt_ipfault`
31			`.extern _excpt_tick`
32			`.extern _excpt_align`
33			`.extern _excpt_illinsn`
34			`.extern _excpt_int`
35			`.extern _excpt_dtlbmiss`
36			`.extern _excpt_itlbmiss`
37			`.extern _excpt_range`
38			`.extern _excpt_syscall`
39			`.extern _excpt_break`
40			`.extern _excpt_trap`
41
42	33	julius	`// Assuming .vectors is defined from 0x200 in the linker script`
43			`.org 0x000`
44	25	julius	`_buserr_vector:`
45			`l.nop`
46			`l.addi r1,r1,-116`
47			`l.sw 0x18(r1),r9`
48			`l.jal store_regs`
49			`l.nop`
50
51			`l.mfspr r3,r0,SPR_EPCR_BASE`
52			`l.movhi r4,hi(_except_pc)`
53			`l.ori r4,r4,lo(_except_pc)`
54			`l.sw 0(r4),r3`
55
56			`l.mfspr r3,r0,SPR_EEAR_BASE`
57			`l.movhi r4,hi(_except_ea)`
58			`l.ori r4,r4,lo(_except_ea)`
59			`l.sw 0(r4),r3`
60
61			`l.movhi r9,hi(end_except)`
62			`l.ori r9,r9,lo(end_except)`
63			`l.movhi r10,hi(_excpt_buserr)`
64			`l.ori r10,r10,lo(_excpt_buserr)`
65			`l.lwz r10,0x0(r10)`
66			`l.jr r10`
67			`l.nop`
68
69	33	julius	`.org 0x100`
70	25	julius	`_dpfault_vector:`
71			`l.nop`
72			`l.addi r1,r1,-116`
73			`l.sw 0x18(r1),r9`
74			`l.jal store_regs`
75			`l.nop`
76
77			`l.mfspr r3,r0,SPR_EPCR_BASE`
78			`l.movhi r4,hi(_except_pc)`
79			`l.ori r4,r4,lo(_except_pc)`
80			`l.sw 0(r4),r3`
81
82			`l.mfspr r3,r0,SPR_EEAR_BASE`
83			`l.movhi r4,hi(_except_ea)`
84			`l.ori r4,r4,lo(_except_ea)`
85			`l.sw 0(r4),r3`
86
87			`l.movhi r9,hi(end_except)`
88			`l.ori r9,r9,lo(end_except)`
89			`l.movhi r10,hi(_excpt_dpfault)`
90			`l.ori r10,r10,lo(_excpt_dpfault)`
91			`l.lwz r10,0(r10)`
92			`l.jr r10`
93			`l.nop`
94
95	33	julius	`.org 0x200`
96	25	julius	`_ipfault_vector:`
97			`l.nop`
98			`l.addi r1,r1,-116`
99			`l.sw 0x18(r1),r9`
100			`l.jal store_regs`
101			`l.nop`
102
103			`l.mfspr r3,r0,SPR_EPCR_BASE`
104			`l.movhi r4,hi(_except_pc)`
105			`l.ori r4,r4,lo(_except_pc)`
106			`l.sw 0(r4),r3`
107
108			`l.mfspr r3,r0,SPR_EEAR_BASE`
109			`l.movhi r4,hi(_except_ea)`
110			`l.ori r4,r4,lo(_except_ea)`
111			`l.sw 0(r4),r3`
112
113			`l.movhi r9,hi(end_except)`
114			`l.ori r9,r9,lo(end_except)`
115			`l.movhi r10,hi(_excpt_ipfault)`
116			`l.ori r10,r10,lo(_excpt_ipfault)`
117			`l.lwz r10,0(r10)`
118			`l.jr r10`
119			`l.nop`
120
121	33	julius	`.org 0x300`
122	25	julius	`_tick_vector:`
123			`l.nop`
124			`l.addi r1,r1,-116`
125			`l.sw 0x18(r1),r9`
126			`l.jal store_regs`
127			`l.nop`
128
129			`l.mfspr r3,r0,SPR_EPCR_BASE`
130			`l.movhi r4,hi(_except_pc)`
131			`l.ori r4,r4,lo(_except_pc)`
132			`l.sw 0(r4),r3`
133
134			`l.mfspr r3,r0,SPR_EEAR_BASE`
135			`l.movhi r4,hi(_except_ea)`
136			`l.ori r4,r4,lo(_except_ea)`
137			`l.sw 0(r4),r3`
138
139			`l.movhi r9,hi(end_except)`
140			`l.ori r9,r9,lo(end_except)`
141			`l.movhi r10,hi(_excpt_tick)`
142			`l.ori r10,r10,lo(_excpt_tick)`
143			`l.lwz r10,0(r10)`
144			`l.jr r10`
145			`l.nop`
146
147	33	julius	`.org 0x400`
148	25	julius	`_align_vector:`
149			`l.nop`
150			`l.addi r1,r1,-116`
151			`l.sw 0x18(r1),r9`
152			`l.jal store_regs`
153			`l.nop`
154
155			`l.mfspr r3,r0,SPR_EPCR_BASE`
156			`l.movhi r4,hi(_except_pc)`
157			`l.ori r4,r4,lo(_except_pc)`
158			`l.sw 0(r4),r3`
159
160			`l.mfspr r3,r0,SPR_EEAR_BASE`
161			`l.movhi r4,hi(_except_ea)`
162			`l.ori r4,r4,lo(_except_ea)`
163			`l.sw 0(r4),r3`
164
165			`l.movhi r9,hi(end_except)`
166			`l.ori r9,r9,lo(end_except)`
167			`l.movhi r10,hi(_excpt_align)`
168			`l.ori r10,r10,lo(_excpt_align)`
169			`l.lwz r10,0(r10)`
170			`l.jr r10`
171			`l.nop`
172
173	33	julius	`.org 0x500`
174	25	julius	`_illinsn_vector:`
175			`l.nop`
176			`l.addi r1,r1,-116`
177			`l.sw 0x18(r1),r9`
178			`l.jal store_regs`
179			`l.nop`
180
181			`l.mfspr r3,r0,SPR_EPCR_BASE`
182			`l.movhi r4,hi(_except_pc)`
183			`l.ori r4,r4,lo(_except_pc)`
184			`l.sw 0(r4),r3`
185
186			`l.mfspr r3,r0,SPR_EEAR_BASE`
187			`l.movhi r4,hi(_except_ea)`
188			`l.ori r4,r4,lo(_except_ea)`
189			`l.sw 0(r4),r3`
190
191			`l.movhi r9,hi(end_except)`
192			`l.ori r9,r9,lo(end_except)`
193			`l.movhi r10,hi(_excpt_illinsn)`
194			`l.ori r10,r10,lo(_excpt_illinsn)`
195			`l.lwz r10,0(r10)`
196			`l.jr r10`
197			`l.nop`
198
199	33	julius	`.org 0x600`
200	25	julius	`_int_vector:`
201			`l.nop`
202			`l.addi r1,r1,-116`
203			`l.sw 0x18(r1),r9`
204			`l.jal store_regs`
205			`l.nop`
206
207			`l.mfspr r3,r0,SPR_EPCR_BASE`
208			`l.movhi r4,hi(_except_pc)`
209			`l.ori r4,r4,lo(_except_pc)`
210			`l.sw 0(r4),r3`
211
212			`l.mfspr r3,r0,SPR_EEAR_BASE`
213			`l.movhi r4,hi(_except_ea)`
214			`l.ori r4,r4,lo(_except_ea)`
215			`l.sw 0(r4),r3`
216
217			`l.movhi r9,hi(end_except)`
218			`l.ori r9,r9,lo(end_except)`
219			`l.movhi r10,hi(_excpt_int)`
220			`l.ori r10,r10,lo(_excpt_int)`
221			`l.lwz r10,0(r10)`
222			`l.jr r10`
223			`l.nop`
224
225	33	julius	`.org 0x700`
226	25	julius	`_dtlbmiss_vector:`
227			`l.nop`
228			`l.addi r1,r1,-116`
229			`l.sw 0x18(r1),r9`
230			`l.jal store_regs`
231			`l.nop`
232
233			`l.mfspr r3,r0,SPR_EPCR_BASE`
234			`l.movhi r4,hi(_except_pc)`
235			`l.ori r4,r4,lo(_except_pc)`
236			`l.sw 0(r4),r3`
237
238			`l.mfspr r3,r0,SPR_EEAR_BASE`
239			`l.movhi r4,hi(_except_ea)`
240			`l.ori r4,r4,lo(_except_ea)`
241			`l.sw 0(r4),r3`
242
243			`l.movhi r9,hi(end_except)`
244			`l.ori r9,r9,lo(end_except)`
245			`l.movhi r10,hi(_excpt_dtlbmiss)`
246			`l.ori r10,r10,lo(_excpt_dtlbmiss)`
247			`l.lwz r10,0(r10)`
248			`l.jr r10`
249			`l.nop`
250
251	33	julius	`.org 0x800`
252	25	julius	`_itlbmiss_vector:`
253			`l.nop`
254			`l.addi r1,r1,-116`
255			`l.sw 0x18(r1),r9`
256			`l.jal store_regs`
257			`l.nop`
258
259			`l.mfspr r3,r0,SPR_EPCR_BASE`
260			`l.movhi r4,hi(_except_pc)`
261			`l.ori r4,r4,lo(_except_pc)`
262			`l.sw 0(r4),r3`
263
264			`l.mfspr r3,r0,SPR_EEAR_BASE`
265			`l.movhi r4,hi(_except_ea)`
266			`l.ori r4,r4,lo(_except_ea)`
267			`l.sw 0(r4),r3`
268
269			`l.movhi r9,hi(end_except)`
270			`l.ori r9,r9,lo(end_except)`
271			`l.movhi r10,hi(_excpt_itlbmiss)`
272			`l.ori r10,r10,lo(_excpt_itlbmiss)`
273			`l.lwz r10,0(r10)`
274			`l.jr r10`
275			`l.nop`
276
277	33	julius	`.org 0x900`
278	25	julius	`_range_vector:`
279			`l.nop`
280			`l.addi r1,r1,-116`
281			`l.sw 0x18(r1),r9`
282			`l.jal store_regs`
283			`l.nop`
284
285			`l.mfspr r3,r0,SPR_EPCR_BASE`
286			`l.movhi r4,hi(_except_pc)`
287			`l.ori r4,r4,lo(_except_pc)`
288			`l.sw 0(r4),r3`
289
290			`l.mfspr r3,r0,SPR_EEAR_BASE`
291			`l.movhi r4,hi(_except_ea)`
292			`l.ori r4,r4,lo(_except_ea)`
293			`l.sw 0(r4),r3`
294
295			`l.movhi r9,hi(end_except)`
296			`l.ori r9,r9,lo(end_except)`
297			`l.movhi r10,hi(_excpt_range)`
298			`l.ori r10,r10,lo(_excpt_range)`
299			`l.lwz r10,0(r10)`
300			`l.jr r10`
301			`l.nop`
302
303	33	julius	`.org 0xa00`
304	25	julius	`_syscall_vector:`
305			`l.nop`
306			`l.addi r3,r3,4`
307
308			`l.mfspr r4,r0,SPR_SR`
309			`l.andi r4,r4,7`
310			`l.add r6,r0,r4`
311
312			`l.mfspr r4,r0,SPR_EPCR_BASE`
313			`l.movhi r5,hi(_sys1)`
314			`l.ori r5,r5,lo(_sys1)`
315			`l.sub r5,r4,r5`
316
317			`l.mfspr r4,r0,SPR_ESR_BASE /* ESR - set supvisor mode */`
318			`l.ori r4,r4,SPR_SR_SM`
319			`l.mtspr r0,r4,SPR_ESR_BASE`
320
321			`l.movhi r4,hi(_sys2)`
322			`l.ori r4,r4,lo(_sys2)`
323			`l.mtspr r0,r4,SPR_EPCR_BASE`
324
325			`l.rfe`
326			`l.addi r3,r3,8`
327
328	33	julius	`.org 0xb00`
329	25	julius	`_break_vector:`
330			`l.nop`
331			`l.addi r1,r1,-116`
332			`l.sw 0x18(r1),r9`
333			`l.jal store_regs`
334			`l.nop`
335
336			`l.mfspr r3,r0,SPR_EPCR_BASE`
337			`l.movhi r4,hi(_except_pc)`
338			`l.ori r4,r4,lo(_except_pc)`
339			`l.sw 0(r4),r3`
340
341			`l.mfspr r3,r0,SPR_EEAR_BASE`
342			`l.movhi r4,hi(_except_ea)`
343			`l.ori r4,r4,lo(_except_ea)`
344			`l.sw 0(r4),r3`
345
346			`l.movhi r9,hi(end_except)`
347			`l.ori r9,r9,lo(end_except)`
348			`l.movhi r10,hi(_excpt_break)`
349			`l.ori r10,r10,lo(_excpt_break)`
350			`l.lwz r10,0(r10)`
351			`l.jr r10`
352			`l.nop`
353
354	33	julius	`.org 0xc00`
355	25	julius	`_trap_vector:`
356			`l.nop`
357			`l.addi r1,r1,-116`
358			`l.sw 0x18(r1),r9`
359			`l.jal store_regs`
360			`l.nop`
361
362			`l.mfspr r3,r0,SPR_EPCR_BASE`
363			`l.movhi r4,hi(_except_pc)`
364			`l.ori r4,r4,lo(_except_pc)`
365			`l.sw 0(r4),r3`
366
367			`l.mfspr r3,r0,SPR_EEAR_BASE`
368			`l.movhi r4,hi(_except_ea)`
369			`l.ori r4,r4,lo(_except_ea)`
370			`l.sw 0(r4),r3`
371
372			`l.movhi r9,hi(end_except)`
373			`l.ori r9,r9,lo(end_except)`
374			`l.movhi r10,hi(_excpt_trap)`
375			`l.ori r10,r10,lo(_excpt_trap)`
376			`l.lwz r10,0(r10)`
377			`l.jr r10`
378			`l.nop`
379
380			`store_regs:`
381			`l.sw 0x00(r1),r3`
382			`l.sw 0x04(r1),r4`
383			`l.sw 0x08(r1),r5`
384			`l.sw 0x0c(r1),r6`
385			`l.sw 0x10(r1),r7`
386			`l.sw 0x14(r1),r8`
387			`l.sw 0x1c(r1),r10`
388			`l.sw 0x20(r1),r11`
389			`l.sw 0x24(r1),r12`
390			`l.sw 0x28(r1),r13`
391			`l.sw 0x2c(r1),r14`
392			`l.sw 0x30(r1),r15`
393			`l.sw 0x34(r1),r16`
394			`l.sw 0x38(r1),r17`
395			`l.sw 0x3c(r1),r18`
396			`l.sw 0x40(r1),r19`
397			`l.sw 0x44(r1),r20`
398			`l.sw 0x48(r1),r21`
399			`l.sw 0x4c(r1),r22`
400			`l.sw 0x50(r1),r23`
401			`l.sw 0x54(r1),r24`
402			`l.sw 0x58(r1),r25`
403			`l.sw 0x5c(r1),r26`
404			`l.sw 0x60(r1),r27`
405			`l.sw 0x64(r1),r28`
406			`l.sw 0x68(r1),r29`
407			`l.sw 0x6c(r1),r30`
408			`l.sw 0x70(r1),r31`
409			`l.jr r9`
410			`l.nop`
411
412			`end_except:`
413			`l.lwz r3,0x00(r1)`
414			`l.lwz r4,0x04(r1)`
415			`l.lwz r5,0x08(r1)`
416			`l.lwz r6,0x0c(r1)`
417			`l.lwz r7,0x10(r1)`
418			`l.lwz r8,0x14(r1)`
419			`l.lwz r9,0x18(r1)`
420			`l.lwz r10,0x1c(r1)`
421			`l.lwz r11,0x20(r1)`
422			`l.lwz r12,0x24(r1)`
423			`l.lwz r13,0x28(r1)`
424			`l.lwz r14,0x2c(r1)`
425			`l.lwz r15,0x30(r1)`
426			`l.lwz r16,0x34(r1)`
427			`l.lwz r17,0x38(r1)`
428			`l.lwz r18,0x3c(r1)`
429			`l.lwz r19,0x40(r1)`
430			`l.lwz r20,0x44(r1)`
431			`l.lwz r21,0x48(r1)`
432			`l.lwz r22,0x4c(r1)`
433			`l.lwz r23,0x50(r1)`
434			`l.lwz r24,0x54(r1)`
435			`l.lwz r25,0x58(r1)`
436			`l.lwz r26,0x5c(r1)`
437			`l.lwz r27,0x60(r1)`
438			`l.lwz r28,0x64(r1)`
439			`l.lwz r29,0x68(r1)`
440			`l.lwz r30,0x6c(r1)`
441			`l.lwz r31,0x70(r1)`
442			`l.addi r1,r1,116`
443			`l.mtspr r0,r9,SPR_EPCR_BASE`
444			`l.rfe`
445			`l.nop`
446
447			`.section .text`
448
449			`_except_basic:`
450			`_sys1:`
451			`l.addi r3,r0,-2 /* Enable exceptiom recognition and external interrupt,set user mode */`
452			`l.mfspr r4,r0,SPR_SR`
453			`l.and r4,r4,r3`
454			`l.ori r4,r4,(SPR_SR_IEE\|SPR_SR_TEE)`
455			`l.mtspr r0,r4,SPR_SR`
456
457			`l.addi r3,r0,0`
458			`l.sys 1`
459			`l.addi r3,r3,2`
460
461			`_sys2:`
462			`l.addi r11,r0,0`
463
464			`l.mfspr r4,r0,SPR_SR /* Check SR */`
465			`l.andi r4,r4,(SPR_SR_IEE\|SPR_SR_TEE\|SPR_SR_SM)`
466			`l.sfeqi r4,(SPR_SR_IEE\|SPR_SR_TEE\|SPR_SR_SM)`
467			`l.bf 1f`
468			`l.nop`
469			`l.addi r11,r11,1`
470			`1:`
471			`l.sfeqi r3,4 /* Check if l.sys or l.rfe has delay slot */`
472			`l.bf 1f`
473			`l.nop`
474			`l.addi r11,r11,2`
475			`1:`
476			`l.sfeqi r5,0x1c /* Check the EPCR */`
477			`l.bf 1f`
478			`l.nop`
479			`l.addi r11,r11,4`
480			`1:`
481			`l.sfeqi r6,SPR_SR_SM /* Check the SR when exception is taken */`
482			`l.bf 1f`
483			`l.nop`
484			`l.addi r11,r11,8`
485			`1:`
486			`l.jr r9`
487			`l.nop`
488
489			`_lo_dmmu_en:`
490			`l.mfspr r3,r0,SPR_SR`
491			`l.ori r3,r3,SPR_SR_DME`
492			`l.mtspr r0,r3,SPR_ESR_BASE`
493			`l.mtspr r0,r9,SPR_EPCR_BASE`
494			`l.rfe`
495			`l.nop`
496
497			`_lo_immu_en:`
498			`l.mfspr r3,r0,SPR_SR`
499			`l.ori r3,r3,SPR_SR_IME`
500			`l.mtspr r0,r3,SPR_ESR_BASE`
501			`l.mtspr r0,r9,SPR_EPCR_BASE`
502			`l.rfe`
503			`l.nop`
504
505			`_call:`
506			`l.addi r11,r0,0`
507			`l.jr r3`
508			`l.nop`
509
510			`_call_with_int:`
511			`l.mfspr r8,r0,SPR_SR`
512			`l.ori r8,r8,SPR_SR_TEE`
513			`l.mtspr r0,r8,SPR_ESR_BASE`
514			`l.mtspr r0,r3,SPR_EPCR_BASE`
515			`l.rfe`
516
517			`_load_acc_32:`
518			`l.movhi r11,hi(0x12345678)`
519			`l.ori r11,r11,lo(0x12345678)`
520			`l.lwz r11,0(r4)`
521			`l.jr r9`
522			`l.nop`
523
524			`_load_acc_16:`
525			`l.movhi r11,hi(0x12345678)`
526			`l.ori r11,r11,lo(0x12345678)`
527			`l.lhz r11,0(r4)`
528			`l.jr r9`
529			`l.nop`
530
531			`_store_acc_32:`
532			`l.movhi r3,hi(0x12345678)`
533			`l.ori r3,r3,lo(0x12345678)`
534			`l.sw 0(r4),r3`
535			`l.jr r9`
536			`l.nop`
537
538			`_store_acc_16:`
539			`l.movhi r3,hi(0x12345678)`
540			`l.ori r3,r3,lo(0x12345678)`
541			`l.sh 0(r4),r3`
542			`l.jr r9`
543			`l.nop`
544
545			`_load_b_acc_32:`
546			`l.movhi r11,hi(0x12345678)`
547			`l.ori r11,r11,lo(0x12345678)`
548			`l.jr r9`
549			`l.lwz r11,0(r4)`
550
551			`_b_trap:`
552			`l.jr r9`
553			`_trap:`
554			`l.trap 1`
555			`l.jr r9`
556			`l.nop`
557
558			`_b_range:`
559			`l.jr r9`
560			`_range:`
561			`l.addi r3,r0,-1`
562			`l.jr r9`
563			`l.nop`
564
565			`_int_trigger:`
566			`l.addi r11,r0,0`
567			`l.mfspr r3,r0,SPR_SR`
568			`l.ori r3,r3,SPR_SR_TEE`
569			`l.mtspr r0,r3,SPR_SR`
570			`l.addi r11,r11,1`
571
572			`_int_loop:`
573			`l.j _int_loop`
574			`l.lwz r5,0(r4);`
575
576			`_jump_back:`
577			`l.addi r11,r0,0`
578			`l.jr r9`
579			`l.addi r11,r11,1`
580