OpenCores
URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [sw/] [icm/] [icm.S] - Blame information for rev 54

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 25 julius
/* Basic instruction set test */
2
#include "../support/spr_defs.h"
3
 
4
.global _main
5
.global _buserr_except
6
.global _dpf_except
7
.global _ipf_except
8
.global _lpint_except
9
.global _align_except
10
.global _illegal_except
11
.global _hpint_except
12
.global _dtlbmiss_except
13
.global _itlbmiss_except
14
.global _range_except
15
.global _syscall_except
16
.global _res1_except
17
.global _trap_except
18
.global _res2_except
19
.global _icm_test
20
 
21
.section .text
22
 
23
_buserr_except:
24
_dpf_except:
25
_ipf_except:
26
_lpint_except:
27
_align_except:
28
_illegal_except:
29
_hpint_except:
30
_dtlbmiss_except:
31
_itlbmiss_except:
32
_range_except:
33
_syscall_except:
34
_res1_except:
35
_trap_except:
36
_res2_except:
37
 
38
_main:
39
        l.nop
40
        l.addi  r6,r0,0
41
 
42
        /* Store array */
43
        /* r4 pointer */
44
        /* r5 loop counter */
45
        l.movhi r4,hi(_icm_var)
46
        l.ori   r4,r4,lo(_icm_var)
47
        l.addi  r5,r0,6
48
loop1:  l.sw    0(r4),r4
49
        l.addi  r4,r4,4
50
        l.sfeq  r5,r0
51
        l.bnf   loop1
52
        l.addi  r5,r5,-1
53
 
54
        /* Check array */
55
        /* r4 pointer */
56
        /* r5 loop counter */
57
        /* r6 chksum */
58
        /* r7 tmp loaded value */
59
        l.movhi r4,hi(_icm_var)
60
        l.ori   r4,r4,lo(_icm_var)
61
        l.addi  r5,r0,6
62
loop2:  l.lwz   r7,0(r4)
63
        l.addi  r4,r4,4
64
        l.add   r6,r6,r7
65
        l.sfeq  r5,r0
66
        l.bnf   loop2
67
        l.addi  r5,r5,-1
68
 
69
        /* Run from ICM */
70
        l.jal   _icm_test
71
        l.addi  r6,r6,50
72
 
73
        l.add   r3,r0,r6
74
        l.jal   _report
75
 
76
        l.nop
77 52 julius
        l.jal   _or32_exit
78 25 julius
        l.nop
79
        l.nop
80
 
81
.section .data,"ax"
82
 
83
_ram_var:
84
.space 100
85
 
86
.section .icm,"ax"
87
 
88
_icm_var:
89
.space 100
90
 
91
_icm_test:
92
        l.addi  r6,r6,1
93
        l.movhi r4,hi(_ram_var)
94
        l.ori   r4,r4,lo(_ram_var)
95
        l.lwz   r5,0(r4)
96
        l.sw    0(r4),r5
97
        l.j     _icm_test_jmptest
98
        l.addi  r6,r6,5
99
 
100
_icm_test_jmptest:
101
        l.nop
102
        l.sw    4(r4),r5
103
        l.sw    8(r4),r5
104
        l.sw    12(r4),r5
105
        l.sw    16(r4),r5
106
 
107
        /* Store array */
108
        /* r4 pointer */
109
        /* r5 loop counter */
110
        l.movhi r4,hi(_icm_var)
111
        l.ori   r4,r4,lo(_icm_var)
112
        l.movhi r4,hi(0x00100000)
113
        l.ori   r4,r4,lo(0x00100000)
114
        l.addi  r5,r0,6
115
loop3:  l.sw    0(r4),r4
116
        l.addi  r4,r4,4
117
        l.sfeq  r5,r0
118
        l.bnf   loop3
119
        l.addi  r5,r5,-1
120
 
121
        /* Check array */
122
        /* r4 pointer */
123
        /* r5 loop counter */
124
        /* r6 chksum */
125
        /* r7 tmp loaded value */
126
        l.movhi r4,hi(_icm_var)
127
        l.ori   r4,r4,lo(_icm_var)
128
        l.addi  r5,r0,6
129
loop4:
130
/*      l.lwz   r7,0(r4)*/
131
        l.add   r7,r0,r0
132
        l.addi  r4,r4,4
133
        l.add   r6,r6,r7
134
        l.sfeq  r5,r0
135
        l.bnf   loop4
136
        l.addi  r5,r5,-1
137
 
138
        l.nop
139
        l.jr    r9
140
        l.addi  r6,r6,20
141
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.