OpenCores
URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [sw/] [mul/] [mul.c] - Blame information for rev 64

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 25 julius
/* ADDED BY ME */
2
#define OR1K 1
3
 
4
/* Test l.mul, l.mac and l.macrc instructions */
5
#include "support.h"
6
 
7
#define T1 0xa6312f33
8
#define T2 0x0d4de375
9
#define T3 0x61ab48dc
10
 
11
#ifndef __or32__
12
 
13
#include <stdlib.h>
14
#define LONGEST long long
15
 
16 52 julius
 
17 25 julius
LONGEST acc = 0;
18
#define MAC(x,y) {\
19
  printf ("[%08x,%08x]\t", (unsigned long)(x), (unsigned long)(y));\
20
  acc += (LONGEST)(x) * (LONGEST)(y);\
21
  printf ("(%08x,%08x)\n", (unsigned long)(acc >> 32), (unsigned long)(acc & 0xffffffff));\
22
}
23
#define MACRC    (macrc())
24
static inline long macrc() {
25
  long result = acc >> 28;
26 54 julius
  printf ("<%08x>\n", (unsigned long)result);
27 25 julius
  acc = 0;
28
  return result;
29
}
30
#else /* OR1K */
31
 
32
#define MAC(x,y) asm volatile ("l.mac\t%0,%1" : : "r" (x), "r" (y))
33
#define MACRC macrc()
34
static inline long macrc() {
35
  long x;
36
  asm volatile ("l.macrc\t%0" : "=r" (x));
37
  return x;
38
}
39
 
40
#endif /* SIM */
41
 
42 52 julius
// Define dummpy or32 trap vectors
43
void buserr_except(){}
44
void dpf_except(){}
45
void ipf_except(){}
46
void lpint_except(){}
47
void align_except(){}
48
void illegal_except(){}
49
void hpint_except(){}
50
void dtlbmiss_except(){}
51
void itlbmiss_except(){}
52
void range_except(){}
53
void syscall_except(){}
54
void res1_except(){}
55
void trap_except(){}
56
void res2_except(){}
57
 
58
 
59 25 julius
long test_mul (long a, long b) {
60
  long t;
61
  int i;
62
  for (i = 0; i < 100; i++) {
63
    t = a * b;
64
    t += 153;
65
    a = t - a * 17;
66
    b = t + b * 13333;
67
 
68
    /*printf ("(%08x,%08x)", a, b);*/
69
  }
70
  return a;
71
}
72
 
73
long test_mac (long a, long b) {
74
  long t = 1234567;
75
  int i;
76
  for (i = 0; i < 100; i++) {
77
    MAC (a, b);
78
    if (i & 3) {
79
      a = t - a;
80
      b = t + a;
81
    } else {
82
      a = MACRC;
83
      report(a);
84
    }
85
    MAC (a, 3);
86
    MAC (a, 5);
87
    MAC (a, 7);
88
    //printf ("(%08x,%08x)", a, b);
89
  }
90
  return a;
91
}
92
 
93
long test_mul_mac (long a, long b) {
94
  long t = 1;
95
  int i;
96
  for (i = 0; i < 100; i++) {
97
    a = a * 119;
98
    MAC (a, b);
99
    MAC (b, 423490431);
100
    MAC (b, 113);
101
    MAC (a, 997);
102
    b = 87 * a * t;
103
    if (i & 3) {
104
      t = a * b;
105
      a = t - a;
106
      b = t + a;
107
    } else {
108
      a = MACRC;
109
    }
110
 //   printf ("(%08x,%08x)", a, b);
111
  }
112
  return a;
113
}
114
 
115
int main () {
116
  unsigned t1;
117
  unsigned t2;
118
  unsigned t3;
119
/*
120
  report (MACRC);
121
  MAC ((unsigned long)888888887, (unsigned long)0x87654321);
122
  report (MACRC);
123
  MAC ((unsigned long)888888887, (unsigned long)0x87654321);
124
  MAC ((unsigned long)888888887, (unsigned long)0x87654321);
125
  report (MACRC);
126 52 julius
  or32_exit(0);
127 25 julius
*/
128
  printf ("%8x\n", MACRC);
129
  t1 = test_mul (888888887, 0x87654321);
130 54 julius
  //t2 = test_mac (888888887, 0x87654321);    
131
  //t3 = test_mul_mac (888888887, 0x87654321);
132 25 julius
  printf ("%08x, expected %08x\n", t1, T1);
133 54 julius
  //printf ("%08x, expected %08x\n", t2, T2);
134
  //printf ("%08x, expected %08x\n", t3, T3);
135
  report (t1 /*^ t2 ^ t3*/ ^ T1 /* ^ T2 ^ T3*/ ^ 0xdeaddead);
136
  if (t1 != T1 /* || t2 != T2 || t3 != T3*/) {
137 25 julius
    printf ("Test failed!\n");
138 52 julius
    if (t1 != T1) or32_exit (1);
139 54 julius
    //if (t2 != T2) or32_exit (2);
140
    //if (t3 != T3) or32_exit (3);
141 25 julius
  } else {
142
    printf ("Test succesful.\n");
143 52 julius
    or32_exit (0);
144 25 julius
  }
145 52 julius
  or32_exit (0);
146 25 julius
}

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.