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[/] [test_project/] [trunk/] [sw/] [support/] [reset.S] - Blame information for rev 27

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Line No. Rev Author Line
1 25 julius 
/* Support file for c based tests */
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#include "spr_defs.h"
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#include "board.h"
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#include "mc.h"
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        .section .stack
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        .space 0x10000
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_stack:
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        .section .reset, "ax"
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        .org    0x100
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_reset_vector:
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        l.nop
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        l.nop
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        l.addi  r2,r0,0x0
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        l.addi  r3,r0,0x0
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        l.addi  r4,r0,0x0
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        l.addi  r5,r0,0x0
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        l.addi  r6,r0,0x0
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        l.addi  r7,r0,0x0
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        l.addi  r8,r0,0x0
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        l.addi  r9,r0,0x0
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        l.addi  r10,r0,0x0
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        l.addi  r11,r0,0x0
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        l.addi  r12,r0,0x0
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        l.addi  r13,r0,0x0
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        l.addi  r14,r0,0x0
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        l.addi  r15,r0,0x0
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        l.addi  r16,r0,0x0
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        l.addi  r17,r0,0x0
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        l.addi  r18,r0,0x0
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        l.addi  r19,r0,0x0
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        l.addi  r20,r0,0x0
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        l.addi  r21,r0,0x0
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        l.addi  r22,r0,0x0
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        l.addi  r23,r0,0x0
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        l.addi  r24,r0,0x0
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        l.addi  r25,r0,0x0
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        l.addi  r26,r0,0x0
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        l.addi  r27,r0,0x0
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        l.addi  r28,r0,0x0
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        l.addi  r29,r0,0x0
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        l.addi  r30,r0,0x0
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        l.addi  r31,r0,0x0
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        l.movhi r3,hi(MC_BASE_ADDR)
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        l.ori   r3,r3,MC_BA_MASK
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        l.addi  r5,r0,0x00
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        l.sw    0(r3),r5
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        l.movhi r3,hi(_start)
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        l.ori   r3,r3,lo(_start)
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        l.jr    r3
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        l.nop
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        .section .text
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_start:
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        l.jal   _init_mc
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        l.nop
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.if IC | DC
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        /* Flush IC and/or DC */
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        l.addi  r10,r0,0
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        l.addi  r11,r0,0
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        l.addi  r12,r0,0
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.if IC
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        l.addi  r11,r0,IC_SIZE
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.endif
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.if DC
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        l.addi  r12,r0,DC_SIZE
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.endif
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        l.sfleu r12,r11
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        l.bf    loop
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        l.nop
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        l.add   r11,r0,r12
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loop:
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.if IC
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        l.mtspr r0,r10,SPR_ICBIR
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.endif
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.if DC
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        l.mtspr r0,r10,SPR_DCBIR
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.endif
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        l.sfne  r10,r11
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        l.bf    loop
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        l.addi  r10,r10,16
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        /* Enable IC and/or DC */
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        l.addi  r10,r0,(SPR_SR_SM)
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.if IC
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        l.ori   r10,r10,(SPR_SR_ICE)
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.endif
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.if DC
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        l.ori   r10,r10,(SPR_SR_DCE)
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.endif
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        l.mtspr r0,r10,SPR_SR
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        l.nop
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        l.nop
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        l.nop
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        l.nop
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        l.nop
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.endif
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        /* Wait for SDRAM */
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        l.addi  r3,r0,0x1       /* 0x1000 */
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1:      l.sfeqi r3,0
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        l.bnf   1b
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        l.addi  r3,r3,-1
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        /* Copy from flash to sram */
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        l.movhi r3,hi(_src_beg)
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        l.ori   r3,r3,lo(_src_beg)
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        l.movhi r4,hi(_icm_start)
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        l.ori   r4,r4,lo(_icm_start)
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        l.movhi r5,hi(_icm_end)
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        l.ori   r5,r5,lo(_icm_end)
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        l.sub   r5,r5,r4
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        l.sfeqi r5,0
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        l.bf    20f
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        l.nop
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10:     l.lwz   r6,0(r3)
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        l.sw    0(r4),r6
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        l.addi  r3,r3,4
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        l.addi  r4,r4,4
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        l.addi  r5,r5,-4
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        l.sfgtsi r5,0
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        l.bf    10b
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        l.nop
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20:
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        /* Copy from flash to sram */
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        l.movhi r3,hi(_src_beg)
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        l.ori   r3,r3,lo(_src_beg)
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        l.movhi r4,hi(_vec_start)
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        l.ori   r4,r4,lo(_vec_start)
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        l.movhi r5,hi(_vec_end)
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        l.ori   r5,r5,lo(_vec_end)
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        l.sub   r5,r5,r4
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        l.sfeqi r5,0
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        l.bf    2f
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        l.nop
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1:      l.lwz   r6,0(r3)
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        l.sw    0(r4),r6
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        l.addi  r3,r3,4
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        l.addi  r4,r4,4
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        l.addi  r5,r5,-4
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        l.sfgtsi r5,0
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        l.bf    1b
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        l.nop
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2:
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        l.movhi r4,hi(_dst_beg)
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        l.ori   r4,r4,lo(_dst_beg)
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        l.movhi r5,hi(_dst_end)
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        l.ori   r5,r5,lo(_dst_end)
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1:      l.sfgeu r4,r5
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        l.bf    1f
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        l.nop
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        l.lwz   r8,0(r3)
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        l.sw    0(r4),r8
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        l.addi  r3,r3,4
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        l.bnf   1b
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        l.addi  r4,r4,4
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1:
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        l.addi  r3,r0,0
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        l.addi  r4,r0,0
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3:
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        /* Set stack pointer */
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        l.movhi r1,hi(_stack)
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        l.ori   r1,r1,lo(_stack)
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        /* Jump to main */
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        l.movhi r2,hi(_reset)
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        l.ori   r2,r2,lo(_reset)
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        l.jr    r2
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        l.nop
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_init_mc:
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        l.movhi r3,hi(MC_BASE_ADDR)
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        l.ori   r3,r3,lo(MC_BASE_ADDR)
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        l.addi  r4,r3,MC_CSC(0)
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        l.movhi r5,hi(FLASH_BASE_ADDR)
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        l.srai  r5,r5,6
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        l.ori   r5,r5,0x0025
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        l.sw    0(r4),r5
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188 
        l.addi  r4,r3,MC_TMS(0)
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        l.movhi r5,hi(FLASH_TMS_VAL)
190 
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
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        l.sw    0(r4),r5
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193 
        l.addi  r4,r3,MC_BA_MASK
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        l.addi  r5,r0,MC_MASK_VAL
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        l.sw    0(r4),r5
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        l.addi  r4,r3,MC_CSR
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        l.movhi r5,hi(MC_CSR_VAL)
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        l.ori   r5,r5,lo(MC_CSR_VAL)
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        l.sw    0(r4),r5
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        l.addi  r4,r3,MC_TMS(1)
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        l.movhi r5,hi(SDRAM_TMS_VAL)
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        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
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        l.sw    0(r4),r5
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        l.addi  r4,r3,MC_CSC(1)
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        l.movhi r5,hi(SDRAM_BASE_ADDR)
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        l.srai  r5,r5,6
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        l.ori   r5,r5,0x0411
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        l.sw    0(r4),r5
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213 
        l.addi  r4,r3,MC_TMS(2)
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        l.movhi r5,hi(SDRAM_TMS_VAL)
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        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
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        l.sw    0(r4),r5
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218 
        l.addi  r4,r3,MC_CSC(2)
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        l.movhi r5,hi(0x00800000)
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        l.srai  r5,r5,6
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        l.ori   r5,r5,0x0411
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        l.sw    0(r4),r5
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224 
        l.jr    r9
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        l.nop
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