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[/] [test_project/] [trunk/] [sw/] [tick/] [tick.S] - Blame information for rev 52

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Line No. Rev Author Line
1 25 julius 
#include "spr_defs.h"
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3 
.global _main
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5 
/* Within the test we'll use following global variables:
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7 
   r16 interrupt counter
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   r17 current tick timer comparison counter
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   r18 sanity counter
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   r19 loop counter
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   r20 temp value of SR reg
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   r21 temp value of TTMR reg.
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   r23 RAM_START
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15 
   r25-r31 used by int handler
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17 
   The test do the following:
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   We set up the tick timer to trigger once and then we trigger interrupts incrementally
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   on every cycle in the specified test program; on interrupt handler we check if data computed
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   so far exactly matches precalculated values. If interrupt has returned incorreclty, we can
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   detect this using assertion routine at the end.
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*/
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#define  RAM_START 0x00010000
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26 52 julius 
.section .vectors, "ax" // section begins at 0x200 so the handler is installed at 0x500 (0x200+0x300)
27 25 julius 
 
28 33 julius 
.org 0x300
29 25 julius 
#
30 
# Interrupt handler
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#
32 
 
33 
  l.addi  r31,r3,0
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# get interrupted program pc
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  l.mfspr r25,r0,SPR_EPCR_BASE
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37 
# calculate instruction address
38 
  l.movhi r26,hi(_ie_start)
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  l.ori   r26,r26,lo(_ie_start)
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  l.addi  r3,r25,0    #print insn index
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  l.nop   2
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  l.sub   r25,r25,r26
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  l.addi  r3,r25,0    #print insn index
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  l.nop   2
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46 
  l.addi  r3,r31,0    # restore r3
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  l.sfeqi r25, 0x00
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  l.bf    _i00
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  l.sfeqi r25, 0x04
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  l.bf    _i04
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  l.sfeqi r25, 0x08
52 
  l.bf    _i08
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  l.sfeqi r25, 0x0c
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  l.bf    _i0c
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  l.sfeqi r25, 0x10
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  l.bf    _i10
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  l.sfeqi r25, 0x14
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  l.bf    _i14
59 
  l.sfeqi r25, 0x18
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  l.bf    _i18
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  l.sfeqi r25, 0x1c
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  l.bf    _i1c
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  l.sfeqi r25, 0x20
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  l.bf    _i20
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  l.sfeqi r25, 0x24
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  l.bf    _i24
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  l.sfeqi r25, 0x28
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  l.bf    _i28
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  l.sfeqi r25, 0x2c
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  l.bf    _i2c
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  l.sfeqi r25, 0x30
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  l.bf    _i30
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  l.sfeqi r25, 0x34
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  l.bf    _i34
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  l.sfeqi r25, 0x38
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  l.bf    _i38
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  l.nop
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79 
# value not defined
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_die:
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  l.nop   2             #print r3
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83 
  l.addi  r3,r0,0xeeee
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  l.nop   2
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  l.addi  r3,r0,1
86 52 julius 
  l.jal   _or32_exit
87 25 julius 
  l.nop
88 
1:
89 
  l.j     1b
90 
  l.nop
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92 
.section  .text
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_main:
94 
        l.nop
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        l.nop
96 
 
97 
#
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# set tick counter to initial 3 cycles
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#
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  l.addi r16,r0,0
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  l.addi r17,r0,1
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  l.addi r18,r0,0
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  l.addi r19,r0,0
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  l.addi r22,r0,0
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106 
  l.movhi r23,hi(RAM_START)
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  l.ori   r23,r23,lo(RAM_START)
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109 
#
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# unmask all ints
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#
112 
        l.movhi r5,0xffff
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        l.ori   r5,r5,0xffff
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        l.mtspr r0,r5,SPR_PICMR         # set PICMR
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116 
# Set r20 to hold enable exceptions and interrupts
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        l.mfspr r20,r0,SPR_SR
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        l.ori r20,r20,SPR_SR_SM|SPR_SR_TEE|SPR_SR_F
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120 
# Set r21 to hold value of TTMR
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        l.movhi r5,hi(SPR_TTMR_SR | SPR_TTMR_IE)
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        l.add  r21,r5,r17
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124 
#
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# MAIN LOOP
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#
127 
_main_loop:
128 
# reinitialize memory and registers
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  l.addi  r3,r0,0xaaaa
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  l.addi  r9,r0,0xbbbb
131 
  l.sw    0(r23),r3
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  l.sw    4(r23),r9
133 
  l.sw    8(r23),r3
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135 
# Reinitializes tick timer
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  l.addi  r17,r17,1
137 
  l.mtspr r0,r0,SPR_TTCR                # set TTCR
138 
  l.mtspr r0,r21,SPR_TTMR               # set TTMR
139 
  l.mtspr r0,r0,SPR_TTCR                # set TTCR
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        l.addi  r21,r21,1
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142 
# Enable exceptions and interrupts
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        l.mtspr r0,r20,SPR_SR   # set SR
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145 
##### TEST CODE #####
146 
_ie_start:
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  l.movhi r3,0x1234         #00
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  l.sw    0(r23),r3         #04
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  l.movhi r3,hi(RAM_START)  #08
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  l.lwz   r3,0(r3)          #0c
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  l.movhi r3,hi(RAM_START)  #10
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  l.addi  r3,r3,4           #14
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  l.j     1f                #18
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  l.lwz   r3,0(r3)          #1c
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  l.addi  r3,r3,1           #20
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1:
157 
  l.sfeqi r3,0xdead         #24
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  l.jal   2f                #28
159 
  l.addi  r3,r0,0x5678      #2c
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161 
_return_addr:
162 
2:
163 
  l.bf    _die              #30
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  l.sw    8(r23),r3         #34
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_ie_end:
166 
  l.nop                     #38
167 
##### END OF TEST CODE #####
168 
 
169 
# do some testing
170 
 
171 
  l.j     _main_loop
172 
  l.nop
173 
 
174 
_i00:
175 
  l.sfeqi r3,0xaaaa
176 
  l.bnf   _die
177 
  l.nop
178 
  l.j     _resume
179 
  l.nop
180 
_i04:
181 
  l.movhi  r26,0x1234
182 
  l.sfeq   r3,r26
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  l.bnf   _die
184 
  l.nop
185 
  l.lwz   r26,0(r23)
186 
  l.sfeqi r26,0xaaaa
187 
  l.bnf   _die
188 
  l.nop
189 
  l.j     _resume
190 
  l.nop
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_i08:
192 
  l.movhi r26,0x1234
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  l.sfeq  r3,r26
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  l.bnf   _die
195 
  l.nop
196 
  l.lwz   r27,0(r23)
197 
  l.sfeq  r27,r26
198 
  l.bnf   _die
199 
  l.nop
200 
  l.j     _resume
201 
  l.nop
202 
_i0c:
203 
  l.sfeq  r3,r23
204 
  l.bnf   _die
205 
  l.nop
206 
  l.j     _resume
207 
  l.nop
208 
_i10:
209 
  l.movhi r26,0x1234
210 
  l.sfeq  r26,r3
211 
  l.bnf   _die
212 
  l.nop
213 
  l.j     _resume
214 
  l.nop
215 
_i14:
216 
  l.sfeq  r3,r23
217 
  l.bnf   _die
218 
  l.nop
219 
  l.j     _resume
220 
  l.nop
221 
_i18:
222 
  l.addi  r26,r23,4
223 
  l.sfeq  r3,r26
224 
  l.bnf   _die
225 
  l.nop
226 
  l.j     _resume
227 
  l.nop
228 
_i1c:
229 
  l.j     _die
230 
  l.nop
231 
_i20:
232 
  l.j     _die
233 
  l.nop
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_i24:
235 
  l.mfspr r26,r0,SPR_ESR_BASE
236 
  l.addi  r30,r3,0
237 
  l.addi  r3,r26,0
238 
  l.nop   2
239 
  l.addi  r3,r30,0
240 
  l.andi  r26,r26,SPR_SR_F
241 
  l.sfeq  r26,r0
242 
  l.bf   _die
243 
  l.nop
244 
  l.sfeqi  r3,0xbbbb
245 
  l.bnf   _die
246 
  l.nop
247 
  l.j     _resume
248 
  l.nop
249 
_i28:
250 
  l.mfspr r26,r0,SPR_ESR_BASE
251 
  l.addi  r30,r3,0
252 
  l.addi  r3,r26,0
253 
  l.nop   2
254 
  l.addi  r3,r30,0
255 
  l.andi  r26,r26,SPR_SR_F
256 
  l.sfeq  r26,r0
257 
  l.bnf    _die
258 
  l.nop
259 
  l.sfeqi  r22,1
260 
  l.bf     _resume
261 
  l.addi   r22,r0,1
262 
  l.sfeqi  r9,0xbbbb
263 
  l.bnf   _die
264 
  l.nop
265 
  l.j     _resume
266 
  l.nop
267 
_i2c:
268 
  l.movhi  r26,hi(_return_addr)
269 
  l.ori    r26,r26,lo(_return_addr)
270 
  l.sfeq   r9,r26
271 
  l.bnf   _die
272 
  l.nop
273 
  l.sfeqi  r3,0xbbbb
274 
  l.bnf   _die
275 
  l.nop
276 
  l.j     _resume
277 
  l.nop
278 
_i30:
279 
  l.sfeqi  r3,0x5678
280 
  l.bnf   _die
281 
  l.nop
282 
  l.j     _resume
283 
  l.nop
284 
_i34:
285 
  l.sfeqi  r3,0x5678
286 
  l.bnf   _die
287 
  l.nop
288 
  l.lwz    r26,8(r23)
289 
  l.sfeqi  r26,0xaaaa
290 
  l.bnf   _die
291 
  l.nop
292 
  l.j     _resume
293 
  l.nop
294 
_i38:
295 
  l.lwz    r26,8(r23)
296 
  l.sfeqi  r26,0x5678
297 
  l.bnf   _die
298 
  l.nop
299 
#
300 
# mark finished ok
301 
#
302 
  l.movhi r3,hi(0xdeaddead)
303 
  l.ori   r3,r3,lo(0xdeaddead)
304 
  l.nop   2
305 
  l.addi  r3,r0,0
306 52 julius 
  l.jal   _or32_exit
307 25 julius 
  l.nop
308 
_ok:
309 
  l.j     _ok
310 
  l.nop
311 
 
312 
_resume:
313 
  l.mfspr  r27,r0,SPR_ESR_BASE
314 
  l.addi   r26,r0,SPR_SR_TEE
315 
  l.addi   r28,r0,-1
316 
  l.xor    r26,r26,r28
317 
  l.and    r26,r26,r27
318 
  l.mtspr  r0,r26,SPR_ESR_BASE
319 
 
320 
  l.rfe
321 
  l.addi    r3,r3,5         # should not be executed

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