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tobiflex |
------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- --
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-- This is the 68000 software compatible Kernal of TG68 --
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-- --
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-- Copyright (c) 2007 Tobias Gubener <tobiflex@opencores.org> --
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-- --
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-- This source file is free software: you can redistribute it and/or modify --
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-- it under the terms of the GNU Lesser General Public License as published --
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-- by the Free Software Foundation, either version 3 of the License, or --
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-- (at your option) any later version. --
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-- --
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-- This source file is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-- --
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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--
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-- Revision 1.0 2007/11/05
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-- Clean up code and first release
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--
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-- known bugs/todo:
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-- Add CHK INSTRUCTION
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-- Add MOVEP INSTRUCTION
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-- full decode ILLEGAL INSTRUCTIONS
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-- Add FDC Output
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-- add odd Address test
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-- add TRACE
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-- Movem with regmask==x0000
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity TG68_fast is
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port(clk : in std_logic;
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reset : in std_logic; --low active
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clkena_in : in std_logic:='1';
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data_in : in std_logic_vector(15 downto 0);
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IPL : in std_logic_vector(2 downto 0):="111";
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test_IPL : in std_logic:='0'; --only for debugging
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address : out std_logic_vector(31 downto 0);
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data_write : out std_logic_vector(15 downto 0);
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state_out : out std_logic_vector(1 downto 0);
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decodeOPC : buffer std_logic;
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wr : out std_logic;
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UDS, LDS : out std_logic
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);
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end TG68_fast;
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architecture logic of TG68_fast is
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signal state : std_logic_vector(1 downto 0);
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signal clkena : std_logic;
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signal TG68_PC : std_logic_vector(31 downto 0);
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signal TG68_PC_add : std_logic_vector(31 downto 0);
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signal memaddr : std_logic_vector(31 downto 0);
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signal memaddr_in : std_logic_vector(31 downto 0);
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signal ea_data : std_logic_vector(31 downto 0);
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signal ea_data_OP1 : std_logic;
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signal setaddrlong : std_logic;
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signal OP1out, OP2out : std_logic_vector(31 downto 0);
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signal OP1outbrief : std_logic_vector(15 downto 0);
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signal OP1in : std_logic_vector(31 downto 0);
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signal data_write_tmp : std_logic_vector(31 downto 0);
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signal Xtmp : std_logic_vector(31 downto 0);
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signal PC_dataa, PC_datab, PC_result : std_logic_vector(31 downto 0);
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signal setregstore : std_logic;
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signal datatype : std_logic_vector(1 downto 0);
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signal longread : std_logic;
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signal longreaddirect : std_logic;
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signal long_done : std_logic;
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signal nextpass : std_logic;
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signal setnextpass : std_logic;
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signal setdispbyte : std_logic;
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signal setdisp : std_logic;
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signal setdispbrief : std_logic;
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signal prefix : std_logic;
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signal regdirectsource : std_logic;
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signal endOPC : std_logic;
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signal postadd : std_logic;
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signal presub : std_logic;
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signal addsub_a : std_logic_vector(31 downto 0);
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signal addsub_b : std_logic_vector(31 downto 0);
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signal addsub_q : std_logic_vector(31 downto 0);
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signal briefext : std_logic_vector(31 downto 0);
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signal setbriefext : std_logic;
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signal addsub : std_logic;
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signal c_in : std_logic_vector(3 downto 0);
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signal c_out : std_logic_vector(2 downto 0);
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signal add_result : std_logic_vector(33 downto 0);
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signal addsub_ofl : std_logic_vector(2 downto 0);
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signal flag_z : std_logic_vector(2 downto 0);
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signal last_data_read : std_logic_vector(15 downto 0);
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signal data_read : std_logic_vector(31 downto 0);
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signal microaddr : std_logic_vector(7 downto 0);
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signal micronext : std_logic_vector(7 downto 0);
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signal microstep : std_logic;
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signal microset : std_logic;
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signal registerin : std_logic_vector(31 downto 0);
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signal reg_QA : std_logic_vector(31 downto 0);
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signal reg_QB : std_logic_vector(31 downto 0);
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signal Hwrena,Lwrena : std_logic;
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signal Regwrena : std_logic;
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signal rf_dest_addr : std_logic_vector(6 downto 0);
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signal rf_source_addr : std_logic_vector(6 downto 0);
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signal rf_dest_addr_tmp : std_logic_vector(6 downto 0);
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signal rf_source_addr_tmp : std_logic_vector(6 downto 0);
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signal opcode : std_logic_vector(15 downto 0);
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signal laststate : std_logic_vector(1 downto 0);
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signal setstate : std_logic_vector(1 downto 0);
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signal mem_address : std_logic_vector(31 downto 0);
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signal memaddr_a : std_logic_vector(31 downto 0);
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signal mem_data_read : std_logic_vector(31 downto 0);
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signal mem_data_write : std_logic_vector(31 downto 0);
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signal set_mem_rega : std_logic;
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signal data_read_ram : std_logic_vector(31 downto 0);
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signal data_read_uart : std_logic_vector(7 downto 0);
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signal counter_reg : std_logic_vector(31 downto 0);
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signal TG68_PC_br8 : std_logic;
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signal TG68_PC_brw : std_logic;
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signal TG68_PC_nop : std_logic;
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signal setgetbrief : std_logic;
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signal getbrief : std_logic;
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signal brief : std_logic_vector(15 downto 0);
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signal dest_areg : std_logic;
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signal source_areg : std_logic;
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signal data_is_source : std_logic;
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signal set_store_in_tmp : std_logic;
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signal store_in_tmp : std_logic;
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signal write_back : std_logic;
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signal setaddsub : std_logic;
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signal setstackaddr : std_logic;
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signal writePC : std_logic;
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signal writePC_add : std_logic;
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signal set_TG68_PC_dec: std_logic;
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signal TG68_PC_dec : std_logic_vector(1 downto 0);
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signal directPC : std_logic;
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signal set_directPC : std_logic;
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signal execOPC : std_logic;
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signal fetchOPC : std_logic;
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signal Flags : std_logic_vector(15 downto 0); --T.S..III ...XNZVC
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signal set_Flags : std_logic_vector(3 downto 0); --NZVC
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signal exec_ADD : std_logic;
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signal exec_OR : std_logic;
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signal exec_AND : std_logic;
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signal exec_EOR : std_logic;
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signal exec_MOVE : std_logic;
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signal exec_MOVEQ : std_logic;
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signal exec_MOVESR : std_logic;
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signal exec_DIRECT : std_logic;
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signal exec_ADDQ : std_logic;
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signal exec_CMP : std_logic;
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signal exec_ROT : std_logic;
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signal exec_exg : std_logic;
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signal exec_swap : std_logic;
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signal exec_write_back: std_logic;
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signal exec_tas : std_logic;
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signal exec_EXT : std_logic;
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signal exec_ABCD : std_logic;
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signal exec_SBCD : std_logic;
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signal exec_MULU : std_logic;
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signal exec_DIVU : std_logic;
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signal exec_Scc : std_logic;
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signal exec_CPMAW : std_logic;
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signal set_exec_ADD : std_logic;
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signal set_exec_OR : std_logic;
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signal set_exec_AND : std_logic;
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signal set_exec_EOR : std_logic;
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signal set_exec_MOVE : std_logic;
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signal set_exec_MOVEQ : std_logic;
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signal set_exec_MOVESR: std_logic;
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signal set_exec_ADDQ : std_logic;
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signal set_exec_CMP : std_logic;
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signal set_exec_ROT : std_logic;
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signal set_exec_tas : std_logic;
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signal set_exec_EXT : std_logic;
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signal set_exec_ABCD : std_logic;
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signal set_exec_SBCD : std_logic;
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signal set_exec_MULU : std_logic;
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signal set_exec_DIVU : std_logic;
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signal set_exec_Scc : std_logic;
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signal set_exec_CPMAW : std_logic;
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signal condition : std_logic;
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signal OP2out_one : std_logic;
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signal OP1out_zero : std_logic;
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signal ea_to_pc : std_logic;
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signal ea_build : std_logic;
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signal ea_only : std_logic;
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signal get_ea_now : std_logic;
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signal source_lowbits : std_logic;
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signal dest_hbits : std_logic;
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signal rot_rot : std_logic;
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signal rot_lsb : std_logic;
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signal rot_msb : std_logic;
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signal rot_XC : std_logic;
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signal rot_nop : std_logic;
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signal rot_out : std_logic_vector(31 downto 0);
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signal rot_bits : std_logic_vector(1 downto 0);
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signal rot_cnt : std_logic_vector(5 downto 0);
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signal set_rot_cnt : std_logic_vector(5 downto 0);
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signal movem_busy : std_logic;
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signal set_movem_busy : std_logic;
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signal movem_addr : std_logic;
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signal movem_regaddr : std_logic_vector(3 downto 0);
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signal movem_mask : std_logic_vector(15 downto 0);
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signal set_get_movem_mask : std_logic;
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signal get_movem_mask : std_logic;
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signal movem_muxa : std_logic_vector(7 downto 0);
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signal movem_muxb : std_logic_vector(3 downto 0);
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signal movem_muxc : std_logic_vector(1 downto 0);
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signal movem_presub : std_logic;
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signal save_memaddr : std_logic;
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signal movem_bits : std_logic_vector(4 downto 0);
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signal ea_calc_b : std_logic_vector(31 downto 0);
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signal set_mem_addsub : std_logic;
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signal bit_bits : std_logic_vector(1 downto 0);
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signal bit_number_reg : std_logic_vector(4 downto 0);
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signal bit_number : std_logic_vector(4 downto 0);
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signal exec_Bits : std_logic;
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signal bits_out : std_logic_vector(31 downto 0);
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signal one_bit_in : std_logic;
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signal one_bit_out : std_logic;
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signal set_get_bitnumber : std_logic;
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signal get_bitnumber : std_logic;
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signal mem_byte : std_logic;
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signal set_direct_data: std_logic;
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signal use_direct_data: std_logic;
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signal direct_data : std_logic;
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signal set_get_extendedOPC : std_logic;
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signal get_extendedOPC: std_logic;
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signal setstate_delay : std_logic_vector(1 downto 0);
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signal setstate_mux : std_logic_vector(1 downto 0);
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signal use_XZFlag : std_logic;
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signal use_XFlag : std_logic;
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signal dummy_a : std_logic_vector(8 downto 0);
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signal niba_l : std_logic_vector(5 downto 0);
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signal niba_h : std_logic_vector(5 downto 0);
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signal niba_lc : std_logic;
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signal niba_hc : std_logic;
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signal bcda_lc : std_logic;
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signal bcda_hc : std_logic;
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signal dummy_s : std_logic_vector(8 downto 0);
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signal nibs_l : std_logic_vector(5 downto 0);
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signal nibs_h : std_logic_vector(5 downto 0);
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signal nibs_lc : std_logic;
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signal nibs_hc : std_logic;
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signal dummy_mulu : std_logic_vector(31 downto 0);
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signal dummy_div : std_logic_vector(31 downto 0);
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signal dummy_div_sub : std_logic_vector(16 downto 0);
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signal dummy_div_over : std_logic_vector(16 downto 0);
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signal set_V_Flag : std_logic;
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signal OP1sign : std_logic;
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signal set_sign : std_logic;
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signal sign : std_logic;
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signal sign2 : std_logic;
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signal muls_msb : std_logic;
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signal mulu_reg : std_logic_vector(31 downto 0);
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signal div_reg : std_logic_vector(31 downto 0);
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signal div_sign : std_logic;
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signal div_quot : std_logic_vector(31 downto 0);
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signal div_ovl : std_logic;
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signal pre_V_Flag : std_logic;
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signal set_vectoraddr : std_logic;
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signal writeSR : std_logic;
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signal trap_illegal : std_logic;
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signal trap_priv : std_logic;
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signal trap_1010 : std_logic;
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signal trap_1111 : std_logic;
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signal trap_trap : std_logic;
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signal trap_trapv : std_logic;
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signal trap_interrupt : std_logic;
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signal trap : std_logic;
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signal trapd : std_logic;
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-- signal trap_PC : std_logic_vector(31 downto 0);
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signal trap_SR : std_logic_vector(15 downto 0);
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signal set_directSR : std_logic;
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signal directSR : std_logic;
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signal set_stop : std_logic;
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signal stop : std_logic;
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signal trap_vector : std_logic_vector(31 downto 0);
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signal to_USP : std_logic;
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signal from_USP : std_logic;
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signal to_SR : std_logic;
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signal from_SR : std_logic;
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signal illegal_write_mode : std_logic;
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signal illegal_read_mode : std_logic;
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signal illegal_byteaddr : std_logic;
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signal use_SP : std_logic;
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signal no_Flags : std_logic;
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signal IPL_nr : std_logic_vector(2 downto 0);
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signal rIPL_nr : std_logic_vector(2 downto 0);
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signal interrupt : std_logic;
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signal SVmode : std_logic;
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signal check_movep : std_logic;
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signal check_chk : std_logic;
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|
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signal test_delay : std_logic_vector(2 downto 0);
|
313 |
|
|
signal set_PCmarker : std_logic;
|
314 |
|
|
signal PCmarker : std_logic;
|
315 |
|
|
signal set_Z_error : std_logic;
|
316 |
|
|
signal Z_error : std_logic;
|
317 |
|
|
|
318 |
|
|
|
319 |
|
|
type regfile_t is array(0 to 16) of std_logic_vector(31 downto 0);
|
320 |
|
|
signal regfile : regfile_t;
|
321 |
|
|
signal RWindex_A : integer range 0 to 16;
|
322 |
|
|
signal RWindex_B : integer range 0 to 16;
|
323 |
|
|
|
324 |
|
|
BEGIN
|
325 |
|
|
|
326 |
|
|
-----------------------------------------------------------------------------
|
327 |
|
|
-- Registerfile
|
328 |
|
|
-----------------------------------------------------------------------------
|
329 |
|
|
|
330 |
|
|
RWindex_A <= conv_integer(rf_dest_addr(4)&(rf_dest_addr(3 downto 0) XOR "1111"));
|
331 |
|
|
RWindex_B <= conv_integer(rf_source_addr(4)&(rf_source_addr(3 downto 0) XOR "1111"));
|
332 |
|
|
|
333 |
|
|
PROCESS (clk)
|
334 |
|
|
BEGIN
|
335 |
|
|
IF falling_edge(clk) THEN
|
336 |
|
|
IF clkena='1' THEN
|
337 |
|
|
reg_QA <= regfile(RWindex_A);
|
338 |
|
|
reg_QB <= regfile(RWindex_B);
|
339 |
|
|
END IF;
|
340 |
|
|
END IF;
|
341 |
|
|
IF rising_edge(clk) THEN
|
342 |
|
|
IF clkena='1' THEN
|
343 |
|
|
IF Lwrena='1' THEN
|
344 |
|
|
regfile(RWindex_A)(15 downto 0) <= registerin(15 downto 0);
|
345 |
|
|
END IF;
|
346 |
|
|
IF Hwrena='1' THEN
|
347 |
|
|
regfile(RWindex_A)(31 downto 16) <= registerin(31 downto 16);
|
348 |
|
|
END IF;
|
349 |
|
|
END IF;
|
350 |
|
|
END IF;
|
351 |
|
|
END PROCESS;
|
352 |
|
|
|
353 |
|
|
|
354 |
|
|
|
355 |
|
|
address <= TG68_PC when state="00" else X"ffffffff" when state="01" else memaddr;
|
356 |
|
|
LDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='1') AND state/="01" ELSE '1';
|
357 |
|
|
UDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='0') AND state/="01" ELSE '1';
|
358 |
|
|
state_out <= state;
|
359 |
|
|
wr <= '0' WHEN state="11" ELSE '1';
|
360 |
|
|
IPL_nr <= NOT IPL;
|
361 |
|
|
|
362 |
|
|
|
363 |
|
|
-----------------------------------------------------------------------------
|
364 |
|
|
-- "ALU"
|
365 |
|
|
-----------------------------------------------------------------------------
|
366 |
|
|
PROCESS (addsub_a, addsub_b, addsub, add_result, c_in)
|
367 |
|
|
BEGIN
|
368 |
|
|
IF addsub='1' THEN --ADD
|
369 |
|
|
add_result <= (('0'&addsub_a&c_in(0))+('0'&addsub_b&c_in(0)));
|
370 |
|
|
ELSE --SUB
|
371 |
|
|
add_result <= (('0'&addsub_a&'0')-('0'&addsub_b&c_in(0)));
|
372 |
|
|
END IF;
|
373 |
|
|
addsub_q <= add_result(32 downto 1);
|
374 |
|
|
c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
|
375 |
|
|
c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
|
376 |
|
|
c_in(3) <= add_result(33);
|
377 |
|
|
addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7)); --V Byte
|
378 |
|
|
addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15)); --V Word
|
379 |
|
|
addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31)); --V Long
|
380 |
|
|
c_out <= c_in(3 downto 1);
|
381 |
|
|
END PROCESS;
|
382 |
|
|
|
383 |
|
|
-----------------------------------------------------------------------------
|
384 |
|
|
-- MEM_IO
|
385 |
|
|
-----------------------------------------------------------------------------
|
386 |
|
|
PROCESS (clk, reset, clkena_in, opcode, rIPL_nr, longread, get_extendedOPC, trap_illegal, z_error, trap_trapv, trap_priv, trap_1010, trap_1111, trap_trap,
|
387 |
|
|
memaddr, memaddr_a, set_mem_addsub, movem_presub, movem_busy, state, PCmarker, execOPC, datatype, setdisp, setdispbrief, briefext, setdispbyte, brief,
|
388 |
|
|
trap_vector, interrupt, set_mem_rega, reg_QA, setaddrlong, data_read, decodeOPC, TG68_PC, data_in, long_done, last_data_read, mem_byte,
|
389 |
|
|
data_write_tmp, addsub_q, set_vectoraddr)
|
390 |
|
|
BEGIN
|
391 |
|
|
clkena <= clkena_in AND NOT longread AND NOT get_extendedOPC;
|
392 |
|
|
|
393 |
|
|
-- IF rising_edge(clk) THEN
|
394 |
|
|
-- IF clkena='1' THEN
|
395 |
|
|
-- trap_vector <= "000000000000000000000000011"&rIPL_nr&"00";
|
396 |
|
|
trap_vector <= (others => '0');
|
397 |
|
|
-- IF trap_addr_fault='1' THEN
|
398 |
|
|
-- trap_vector(7 downto 0) <= X"08";
|
399 |
|
|
-- END IF;
|
400 |
|
|
-- IF trap_addr_error='1' THEN
|
401 |
|
|
-- trap_vector(7 downto 0) <= X"0C";
|
402 |
|
|
-- END IF;
|
403 |
|
|
IF trap_illegal='1' THEN
|
404 |
|
|
trap_vector(7 downto 0) <= X"10";
|
405 |
|
|
-- END IF;
|
406 |
|
|
ELSIF z_error='1' THEN
|
407 |
|
|
trap_vector(7 downto 0) <= X"14";
|
408 |
|
|
-- END IF;
|
409 |
|
|
-- IF trap_chk='1' THEN
|
410 |
|
|
-- trap_vector(7 downto 0) <= X"18";
|
411 |
|
|
-- END IF;
|
412 |
|
|
ELSIF trap_trapv='1' THEN
|
413 |
|
|
trap_vector(7 downto 0) <= X"1C";
|
414 |
|
|
-- END IF;
|
415 |
|
|
ELSIF trap_priv='1' THEN
|
416 |
|
|
trap_vector(7 downto 0) <= X"20";
|
417 |
|
|
-- END IF;
|
418 |
|
|
-- IF trap_trace='1' THEN
|
419 |
|
|
-- trap_vector(7 downto 0) <= X"24";
|
420 |
|
|
-- END IF;
|
421 |
|
|
ELSIF trap_1010='1' THEN
|
422 |
|
|
trap_vector(7 downto 0) <= X"28";
|
423 |
|
|
-- END IF;
|
424 |
|
|
ELSIF trap_1111='1' THEN
|
425 |
|
|
trap_vector(7 downto 0) <= X"2C";
|
426 |
|
|
-- END IF;
|
427 |
|
|
ELSIF trap_trap='1' THEN
|
428 |
|
|
trap_vector(7 downto 2) <= "10"&opcode(3 downto 0);
|
429 |
|
|
-- ELSIF trap_interrupt='1' THEN
|
430 |
|
|
ELSE
|
431 |
|
|
trap_vector(7 downto 2) <= "011"&rIPL_nr;
|
432 |
|
|
-- END IF;
|
433 |
|
|
-- END IF;
|
434 |
|
|
END IF;
|
435 |
|
|
|
436 |
|
|
memaddr_a(3 downto 0) <= "0000";
|
437 |
|
|
memaddr_a(7 downto 4) <= (OTHERS=>memaddr_a(3));
|
438 |
|
|
memaddr_a(15 downto 8) <= (OTHERS=>memaddr_a(7));
|
439 |
|
|
memaddr_a(31 downto 16) <= (OTHERS=>memaddr_a(15));
|
440 |
|
|
IF movem_presub='1' THEN
|
441 |
|
|
IF movem_busy='1' OR longread='1' THEN
|
442 |
|
|
memaddr_a(3 downto 0) <= "1110";
|
443 |
|
|
END IF;
|
444 |
|
|
ELSIF state(1)='1' OR (get_extendedOPC='1' AND PCmarker='1') THEN
|
445 |
|
|
memaddr_a(1) <= '1';
|
446 |
|
|
ELSIF execOPC='1' THEN
|
447 |
|
|
IF datatype="10" THEN
|
448 |
|
|
memaddr_a(3 downto 0) <= "1100";
|
449 |
|
|
ELSE
|
450 |
|
|
memaddr_a(3 downto 0) <= "1110";
|
451 |
|
|
END IF;
|
452 |
|
|
ELSIF setdisp='1' THEN
|
453 |
|
|
IF setdispbrief='1' THEN
|
454 |
|
|
memaddr_a <= briefext;
|
455 |
|
|
ELSIF setdispbyte='1' THEN
|
456 |
|
|
memaddr_a(7 downto 0) <= brief(7 downto 0);
|
457 |
|
|
ELSE
|
458 |
|
|
memaddr_a(15 downto 0) <= brief;
|
459 |
|
|
END IF;
|
460 |
|
|
END IF;
|
461 |
|
|
|
462 |
|
|
memaddr_in <= memaddr+memaddr_a;
|
463 |
|
|
IF longread='0' THEN
|
464 |
|
|
IF set_mem_addsub='1' THEN
|
465 |
|
|
memaddr_in <= addsub_q;
|
466 |
|
|
ELSIF set_vectoraddr='1' THEN
|
467 |
|
|
memaddr_in <= trap_vector;
|
468 |
|
|
ELSIF interrupt='1' THEN
|
469 |
|
|
memaddr_in <= "1111111111111111111111111111"&rIPL_nr&'0';
|
470 |
|
|
ELSIF set_mem_rega='1' THEN
|
471 |
|
|
memaddr_in <= reg_QA;
|
472 |
|
|
ELSIF setaddrlong='1' AND longread='0' THEN
|
473 |
|
|
memaddr_in <= data_read;
|
474 |
|
|
ELSIF decodeOPC='1' THEN
|
475 |
|
|
memaddr_in <= TG68_PC;
|
476 |
|
|
END IF;
|
477 |
|
|
END IF;
|
478 |
|
|
|
479 |
|
|
data_read(15 downto 0) <= data_in;
|
480 |
|
|
data_read(31 downto 16) <= (OTHERS=>data_in(15));
|
481 |
|
|
IF long_done='1' THEN
|
482 |
|
|
data_read(31 downto 16) <= last_data_read;
|
483 |
|
|
END IF;
|
484 |
|
|
IF mem_byte='1' AND memaddr(0)='0' THEN
|
485 |
|
|
data_read(7 downto 0) <= data_in(15 downto 8);
|
486 |
|
|
END IF;
|
487 |
|
|
|
488 |
|
|
IF longread='1' THEN
|
489 |
|
|
data_write <= data_write_tmp(31 downto 16);
|
490 |
|
|
ELSE
|
491 |
|
|
data_write(7 downto 0) <= data_write_tmp(7 downto 0);
|
492 |
|
|
IF mem_byte='1' THEN
|
493 |
|
|
data_write(15 downto 8) <= data_write_tmp(7 downto 0);
|
494 |
|
|
ELSE
|
495 |
|
|
data_write(15 downto 8) <= data_write_tmp(15 downto 8);
|
496 |
|
|
IF datatype="00" THEN
|
497 |
|
|
data_write(7 downto 0) <= data_write_tmp(15 downto 8);
|
498 |
|
|
END IF;
|
499 |
|
|
END IF;
|
500 |
|
|
END IF;
|
501 |
|
|
|
502 |
|
|
IF reset='0' THEN
|
503 |
|
|
longread <= '0';
|
504 |
|
|
long_done <= '0';
|
505 |
|
|
ELSIF rising_edge(clk) THEN
|
506 |
|
|
IF clkena_in='1' THEN
|
507 |
|
|
last_data_read <= data_in;
|
508 |
|
|
long_done <= longread;
|
509 |
|
|
IF get_extendedOPC='0' OR (get_extendedOPC='1' AND PCmarker='1') THEN
|
510 |
|
|
memaddr <= memaddr_in;
|
511 |
|
|
END IF;
|
512 |
|
|
IF get_extendedOPC='0' THEN
|
513 |
|
|
|
514 |
|
|
IF ((setstate_mux(1)='1' AND datatype="10") OR longreaddirect='1') AND longread='0' AND interrupt='0' THEN
|
515 |
|
|
longread <= '1';
|
516 |
|
|
ELSE
|
517 |
|
|
longread <= '0';
|
518 |
|
|
END IF;
|
519 |
|
|
END IF;
|
520 |
|
|
|
521 |
|
|
END IF;
|
522 |
|
|
END IF;
|
523 |
|
|
END PROCESS;
|
524 |
|
|
-----------------------------------------------------------------------------
|
525 |
|
|
-- brief
|
526 |
|
|
-----------------------------------------------------------------------------
|
527 |
|
|
process (clk, brief, OP1out)
|
528 |
|
|
begin
|
529 |
|
|
IF brief(11)='1' THEN
|
530 |
|
|
OP1outbrief <= OP1out(31 downto 16);
|
531 |
|
|
ELSE
|
532 |
|
|
OP1outbrief <= (OTHERS=>OP1out(15));
|
533 |
|
|
END IF;
|
534 |
|
|
IF rising_edge(clk) THEN
|
535 |
|
|
IF clkena='1' THEN
|
536 |
|
|
-- briefext <= OP1outbrief&OP1out(15 downto 0);
|
537 |
|
|
CASE brief(10 downto 9) IS
|
538 |
|
|
WHEN "00" => briefext <= OP1outbrief&OP1out(15 downto 0);
|
539 |
|
|
WHEN "01" => briefext <= OP1outbrief(14 downto 0)&OP1out(15 downto 0)&'0';
|
540 |
|
|
WHEN "10" => briefext <= OP1outbrief(13 downto 0)&OP1out(15 downto 0)&"00";
|
541 |
|
|
WHEN "11" => briefext <= OP1outbrief(12 downto 0)&OP1out(15 downto 0)&"000";
|
542 |
|
|
END CASE;
|
543 |
|
|
end if;
|
544 |
|
|
end if;
|
545 |
|
|
end process;
|
546 |
|
|
|
547 |
|
|
-----------------------------------------------------------------------------
|
548 |
|
|
-- PC Calc + fetch opcode
|
549 |
|
|
-----------------------------------------------------------------------------
|
550 |
|
|
process (clk, reset, opcode, TG68_PC, TG68_PC_dec, TG68_PC_br8, TG68_PC_brw, PC_dataa, PC_datab, execOPC, last_data_read, get_extendedOPC,
|
551 |
|
|
setstate_delay, setstate)
|
552 |
|
|
begin
|
553 |
|
|
PC_dataa <= TG68_PC;
|
554 |
|
|
PC_datab(2 downto 0) <= "010";
|
555 |
|
|
PC_datab(7 downto 3) <= (others => PC_datab(2));
|
556 |
|
|
PC_datab(15 downto 8) <= (others => PC_datab(7));
|
557 |
|
|
PC_datab(31 downto 16) <= (others => PC_datab(15));
|
558 |
|
|
IF execOPC='0' THEN
|
559 |
|
|
IF TG68_PC_br8='1' THEN
|
560 |
|
|
PC_datab(7 downto 0) <= opcode(7 downto 0);
|
561 |
|
|
END IF;
|
562 |
|
|
IF TG68_PC_dec(1)='1' THEN
|
563 |
|
|
PC_datab(2) <= '1';
|
564 |
|
|
END IF;
|
565 |
|
|
IF TG68_PC_brw = '1' THEN
|
566 |
|
|
PC_datab(15 downto 0) <= last_data_read(15 downto 0);
|
567 |
|
|
END IF;
|
568 |
|
|
END IF;
|
569 |
|
|
TG68_PC_add <= PC_dataa+PC_datab;
|
570 |
|
|
|
571 |
|
|
IF get_extendedOPC='1' THEN
|
572 |
|
|
setstate_mux <= setstate_delay;
|
573 |
|
|
ELSE
|
574 |
|
|
setstate_mux <= setstate;
|
575 |
|
|
END IF;
|
576 |
|
|
|
577 |
|
|
|
578 |
|
|
IF reset = '0' THEN
|
579 |
|
|
opcode(15 downto 12) <= X"7"; --moveq
|
580 |
|
|
opcode(8 downto 6) <= "010"; --long
|
581 |
|
|
TG68_PC <= (others =>'0');
|
582 |
|
|
state <= "01";
|
583 |
|
|
decodeOPC <= '0';
|
584 |
|
|
fetchOPC <= '0';
|
585 |
|
|
endOPC <= '0';
|
586 |
|
|
interrupt <= '0';
|
587 |
|
|
trap_interrupt <= '1';
|
588 |
|
|
execOPC <= '0';
|
589 |
|
|
getbrief <= '0';
|
590 |
|
|
TG68_PC_dec <= "00";
|
591 |
|
|
directPC <= '0';
|
592 |
|
|
directSR <= '0';
|
593 |
|
|
stop <= '0';
|
594 |
|
|
exec_ADD <= '0';
|
595 |
|
|
exec_OR <= '0';
|
596 |
|
|
exec_AND <= '0';
|
597 |
|
|
exec_EOR <= '0';
|
598 |
|
|
exec_MOVE <= '0';
|
599 |
|
|
exec_MOVEQ <= '0';
|
600 |
|
|
exec_MOVESR <= '0';
|
601 |
|
|
exec_ADDQ <= '0';
|
602 |
|
|
exec_CMP <= '0';
|
603 |
|
|
exec_ROT <= '0';
|
604 |
|
|
exec_EXT <= '0';
|
605 |
|
|
exec_ABCD <= '0';
|
606 |
|
|
exec_SBCD <= '0';
|
607 |
|
|
exec_MULU <= '0';
|
608 |
|
|
exec_DIVU <= '0';
|
609 |
|
|
exec_Scc <= '0';
|
610 |
|
|
exec_CPMAW <= '0';
|
611 |
|
|
mem_byte <= '0';
|
612 |
|
|
rot_cnt <="000001";
|
613 |
|
|
get_extendedOPC <= '0';
|
614 |
|
|
get_bitnumber <= '0';
|
615 |
|
|
get_movem_mask <= '0';
|
616 |
|
|
test_delay <= "000";
|
617 |
|
|
PCmarker <= '0';
|
618 |
|
|
ELSIF rising_edge(clk) THEN
|
619 |
|
|
IF clkena_in='1' THEN
|
620 |
|
|
get_extendedOPC <= set_get_extendedOPC;
|
621 |
|
|
get_bitnumber <= set_get_bitnumber;
|
622 |
|
|
get_movem_mask <= set_get_movem_mask;
|
623 |
|
|
setstate_delay <= setstate;
|
624 |
|
|
|
625 |
|
|
TG68_PC_dec <= TG68_PC_dec(0)&set_TG68_PC_dec;
|
626 |
|
|
IF directPC='1' AND clkena='1' THEN
|
627 |
|
|
TG68_PC <= data_read;
|
628 |
|
|
ELSIF ea_to_pc='1' AND longread='0' THEN
|
629 |
|
|
TG68_PC <= memaddr_in;
|
630 |
|
|
ELSIF (state ="00" AND TG68_PC_nop='0') OR TG68_PC_br8='1' OR TG68_PC_brw='1' OR TG68_PC_dec(1)='1' THEN
|
631 |
|
|
TG68_PC <= TG68_PC_add;
|
632 |
|
|
END IF;
|
633 |
|
|
|
634 |
|
|
IF get_bitnumber='1' THEN
|
635 |
|
|
bit_number_reg <= data_read(4 downto 0);
|
636 |
|
|
END IF;
|
637 |
|
|
|
638 |
|
|
IF clkena='1' OR get_extendedOPC='1' THEN
|
639 |
|
|
IF set_get_extendedOPC='1' THEN
|
640 |
|
|
state <= "00";
|
641 |
|
|
ELSIF get_extendedOPC='1' THEN
|
642 |
|
|
state <= setstate_mux;
|
643 |
|
|
ELSIF fetchOPC='1' OR (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR stop='1' THEN
|
644 |
|
|
state <= "01"; --decode cycle, execute cycle
|
645 |
|
|
ELSE
|
646 |
|
|
state <= setstate_mux;
|
647 |
|
|
END IF;
|
648 |
|
|
IF setstate_mux(1)='1' AND datatype="00" AND set_get_extendedOPC='0' THEN
|
649 |
|
|
mem_byte <= '1';
|
650 |
|
|
ELSE
|
651 |
|
|
mem_byte <= '0';
|
652 |
|
|
END IF;
|
653 |
|
|
|
654 |
|
|
END IF;
|
655 |
|
|
END IF;
|
656 |
|
|
|
657 |
|
|
IF clkena='1' THEN
|
658 |
|
|
exec_ADD <= '0';
|
659 |
|
|
exec_OR <= '0';
|
660 |
|
|
exec_AND <= '0';
|
661 |
|
|
exec_EOR <= '0';
|
662 |
|
|
exec_MOVE <= '0';
|
663 |
|
|
exec_MOVEQ <= '0';
|
664 |
|
|
exec_MOVESR <= '0';
|
665 |
|
|
exec_ADDQ <= '0';
|
666 |
|
|
exec_CMP <= '0';
|
667 |
|
|
exec_ROT <= '0';
|
668 |
|
|
exec_ABCD <= '0';
|
669 |
|
|
exec_SBCD <= '0';
|
670 |
|
|
fetchOPC <= '0';
|
671 |
|
|
exec_CPMAW <= '0';
|
672 |
|
|
endOPC <= '0';
|
673 |
|
|
interrupt <= '0';
|
674 |
|
|
execOPC <= '0';
|
675 |
|
|
exec_EXT <= '0';
|
676 |
|
|
exec_Scc <= '0';
|
677 |
|
|
decodeOPC <= fetchOPC;
|
678 |
|
|
directPC <= set_directPC;
|
679 |
|
|
directSR <= set_directSR;
|
680 |
|
|
exec_MULU <= set_exec_MULU;
|
681 |
|
|
exec_DIVU <= set_exec_DIVU;
|
682 |
|
|
|
683 |
|
|
stop <= set_stop OR (stop AND NOT interrupt);
|
684 |
|
|
IF set_PCmarker='1' THEN
|
685 |
|
|
PCmarker <= '1';
|
686 |
|
|
ELSIF (state="10" AND longread='0') OR (ea_only='1' AND get_ea_now='1') THEN
|
687 |
|
|
PCmarker <= '0';
|
688 |
|
|
END IF;
|
689 |
|
|
IF (decodeOPC OR execOPC)='1' THEN
|
690 |
|
|
rot_cnt <= set_rot_cnt;
|
691 |
|
|
END IF;
|
692 |
|
|
IF microstep='0' AND setstate_mux="00" AND (setnextpass='0' OR ea_only='1') AND endOPC='0' AND movem_busy='0' AND set_movem_busy='0' AND set_get_bitnumber='0' THEN
|
693 |
|
|
nextpass <= '0';
|
694 |
|
|
-- IF stop='0' THEN
|
695 |
|
|
IF (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" THEN
|
696 |
|
|
endOPC <= '1';
|
697 |
|
|
IF Flags(10 downto 8)<IPL_nr OR IPL_nr="111" THEN
|
698 |
|
|
interrupt <= '1';
|
699 |
|
|
trap_interrupt <= '1';
|
700 |
|
|
rIPL_nr <= IPL_nr;
|
701 |
|
|
ELSE
|
702 |
|
|
IF stop='0' THEN
|
703 |
|
|
fetchOPC <= '1';
|
704 |
|
|
END IF;
|
705 |
|
|
END IF;
|
706 |
|
|
END IF;
|
707 |
|
|
IF exec_write_back='0' OR state/="11" THEN
|
708 |
|
|
IF stop='0' THEN
|
709 |
|
|
execOPC <= '1';
|
710 |
|
|
END IF;
|
711 |
|
|
exec_ADD <= set_exec_ADD;
|
712 |
|
|
exec_OR <= set_exec_OR;
|
713 |
|
|
exec_AND <= set_exec_AND;
|
714 |
|
|
exec_EOR <= set_exec_EOR;
|
715 |
|
|
exec_MOVE <= set_exec_MOVE;
|
716 |
|
|
exec_MOVEQ <= set_exec_MOVEQ;
|
717 |
|
|
exec_MOVESR <= set_exec_MOVESR;
|
718 |
|
|
exec_ADDQ <= set_exec_ADDQ;
|
719 |
|
|
exec_CMP <= set_exec_CMP;
|
720 |
|
|
exec_ROT <= set_exec_ROT;
|
721 |
|
|
exec_tas <= set_exec_tas;
|
722 |
|
|
exec_EXT <= set_exec_EXT;
|
723 |
|
|
exec_ABCD <= set_exec_ABCD;
|
724 |
|
|
exec_SBCD <= set_exec_SBCD;
|
725 |
|
|
exec_Scc <= set_exec_Scc;
|
726 |
|
|
exec_CPMAW <= set_exec_CPMAW;
|
727 |
|
|
END IF;
|
728 |
|
|
-- END IF;
|
729 |
|
|
ELSE
|
730 |
|
|
IF endOPC='0' AND (setnextpass='1' OR (regdirectsource='1' AND decodeOPC='1')) THEN
|
731 |
|
|
nextpass <= '1';
|
732 |
|
|
END IF;
|
733 |
|
|
END IF;
|
734 |
|
|
IF interrupt='1' THEN
|
735 |
|
|
opcode(15 downto 12) <= X"7"; --moveq
|
736 |
|
|
opcode(8 downto 6) <= "010"; --long
|
737 |
|
|
-- trap_PC <= TG68_PC;
|
738 |
|
|
END IF;
|
739 |
|
|
IF fetchOPC='1' THEN
|
740 |
|
|
trap_interrupt <= '0';
|
741 |
|
|
IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' THEN
|
742 |
|
|
-- IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' OR opcode(15 downto 6)="0100111011" THEN --nur für Validator
|
743 |
|
|
opcode <= X"60FE";
|
744 |
|
|
IF to_SR='0' THEN
|
745 |
|
|
test_delay <= "001";
|
746 |
|
|
END IF;
|
747 |
|
|
ELSE
|
748 |
|
|
opcode <= data_read(15 downto 0);
|
749 |
|
|
END IF;
|
750 |
|
|
getbrief <= '0';
|
751 |
|
|
-- trap_PC <= TG68_PC;
|
752 |
|
|
ELSE
|
753 |
|
|
test_delay <= test_delay(1 downto 0)&'0';
|
754 |
|
|
getbrief <= setgetbrief;
|
755 |
|
|
END IF;
|
756 |
|
|
IF decodeOPC='1' OR interrupt='1' THEN
|
757 |
|
|
trap_SR <= Flags;
|
758 |
|
|
END IF;
|
759 |
|
|
|
760 |
|
|
IF getbrief='1' THEN
|
761 |
|
|
brief <= data_read(15 downto 0);
|
762 |
|
|
END IF;
|
763 |
|
|
end if;
|
764 |
|
|
end if;
|
765 |
|
|
end process;
|
766 |
|
|
|
767 |
|
|
-----------------------------------------------------------------------------
|
768 |
|
|
-- handle EA_data, data_write_tmp
|
769 |
|
|
-----------------------------------------------------------------------------
|
770 |
|
|
PROCESS (clk, reset, opcode)
|
771 |
|
|
BEGIN
|
772 |
|
|
IF reset = '0' THEN
|
773 |
|
|
set_store_in_tmp <='0';
|
774 |
|
|
exec_DIRECT <= '0';
|
775 |
|
|
exec_write_back <= '0';
|
776 |
|
|
direct_data <= '0';
|
777 |
|
|
use_direct_data <= '0';
|
778 |
|
|
Z_error <= '0';
|
779 |
|
|
ELSIF rising_edge(clk) THEN
|
780 |
|
|
IF clkena='1' THEN
|
781 |
|
|
direct_data <= '0';
|
782 |
|
|
IF endOPC='1' THEN
|
783 |
|
|
set_store_in_tmp <='0';
|
784 |
|
|
exec_DIRECT <= '0';
|
785 |
|
|
exec_write_back <= '0';
|
786 |
|
|
use_direct_data <= '0';
|
787 |
|
|
Z_error <= '0';
|
788 |
|
|
ELSE
|
789 |
|
|
IF set_Z_error='1' THEN
|
790 |
|
|
Z_error <= '1';
|
791 |
|
|
END IF;
|
792 |
|
|
exec_DIRECT <= set_exec_MOVE;
|
793 |
|
|
IF setstate_mux="10" AND write_back='1' THEN
|
794 |
|
|
exec_write_back <= '1';
|
795 |
|
|
END IF;
|
796 |
|
|
END IF;
|
797 |
|
|
IF set_direct_data='1' THEN
|
798 |
|
|
direct_data <= '1';
|
799 |
|
|
use_direct_data <= '1';
|
800 |
|
|
END IF;
|
801 |
|
|
IF set_exec_MOVE='1' AND state="11" THEN
|
802 |
|
|
use_direct_data <= '1';
|
803 |
|
|
END IF;
|
804 |
|
|
|
805 |
|
|
IF (exec_DIRECT='1' AND state="00" AND getbrief='0' AND endOPC='0') OR state="10" THEN
|
806 |
|
|
set_store_in_tmp <= '1';
|
807 |
|
|
ea_data <= data_read;
|
808 |
|
|
END IF;
|
809 |
|
|
|
810 |
|
|
IF writePC_add='1' THEN
|
811 |
|
|
data_write_tmp <= TG68_PC_add;
|
812 |
|
|
ELSIF writePC='1' OR fetchOPC='1' OR interrupt='1' OR (trap_trap='1' AND decodeOPC='1') THEN --fetchOPC für Trap
|
813 |
|
|
data_write_tmp <= TG68_PC;
|
814 |
|
|
ELSIF execOPC='1' OR (get_ea_now='1' AND ea_only='1') THEN --get_ea_now='1' AND ea_only='1' ist für pea
|
815 |
|
|
data_write_tmp <= registerin(31 downto 8)&(registerin(7)OR exec_tas)®isterin(6 downto 0);
|
816 |
|
|
ELSIF (exec_DIRECT='1' AND state="10") OR direct_data='1' THEN
|
817 |
|
|
data_write_tmp <= data_read;
|
818 |
|
|
ELSIF movem_busy='1' AND datatype="10" AND movem_presub='1' THEN
|
819 |
|
|
data_write_tmp <= OP2out(15 downto 0)&OP2out(31 downto 16);
|
820 |
|
|
ELSIF (NOT trap AND decodeOPC)='1' OR movem_busy='1'THEN
|
821 |
|
|
data_write_tmp <= OP2out;
|
822 |
|
|
ELSIF writeSR='1'THEN
|
823 |
|
|
data_write_tmp(15 downto 0) <= trap_SR(15 downto 8)& Flags(7 downto 0);
|
824 |
|
|
END IF;
|
825 |
|
|
END IF;
|
826 |
|
|
END IF;
|
827 |
|
|
END PROCESS;
|
828 |
|
|
|
829 |
|
|
-----------------------------------------------------------------------------
|
830 |
|
|
-- set dest regaddr
|
831 |
|
|
-----------------------------------------------------------------------------
|
832 |
|
|
PROCESS (opcode, rf_dest_addr_tmp, to_USP, Flags, trap, movem_addr, movem_presub, movem_regaddr, setbriefext, brief, setstackaddr, dest_hbits, dest_areg, data_is_source)
|
833 |
|
|
BEGIN
|
834 |
|
|
rf_dest_addr <= rf_dest_addr_tmp;
|
835 |
|
|
IF rf_dest_addr_tmp(3 downto 0)="1111" AND to_USP='0' THEN
|
836 |
|
|
rf_dest_addr(4) <= Flags(13) OR trap;
|
837 |
|
|
END IF;
|
838 |
|
|
IF movem_addr='1' THEN
|
839 |
|
|
IF movem_presub='1' THEN
|
840 |
|
|
rf_dest_addr_tmp <= "000"&(movem_regaddr XOR "1111");
|
841 |
|
|
ELSE
|
842 |
|
|
rf_dest_addr_tmp <= "000"&movem_regaddr;
|
843 |
|
|
END IF;
|
844 |
|
|
ELSIF setbriefext='1' THEN
|
845 |
|
|
rf_dest_addr_tmp <= ("000"&brief(15 downto 12));
|
846 |
|
|
ELSIF setstackaddr='1' THEN
|
847 |
|
|
rf_dest_addr_tmp <= "0001111";
|
848 |
|
|
ELSIF dest_hbits='1' THEN
|
849 |
|
|
rf_dest_addr_tmp <= "000"&dest_areg&opcode(11 downto 9);
|
850 |
|
|
ELSE
|
851 |
|
|
IF opcode(5 downto 3)="000" OR data_is_source='1' THEN
|
852 |
|
|
rf_dest_addr_tmp <= "000"&dest_areg&opcode(2 downto 0);
|
853 |
|
|
ELSE
|
854 |
|
|
rf_dest_addr_tmp <= "0001"&opcode(2 downto 0);
|
855 |
|
|
END IF;
|
856 |
|
|
END IF;
|
857 |
|
|
END PROCESS;
|
858 |
|
|
|
859 |
|
|
-----------------------------------------------------------------------------
|
860 |
|
|
-- set OP1
|
861 |
|
|
-----------------------------------------------------------------------------
|
862 |
|
|
PROCESS (reg_QA, OP1out_zero, from_SR, Flags, ea_data_OP1, set_store_in_tmp, ea_data)
|
863 |
|
|
BEGIN
|
864 |
|
|
OP1out <= reg_QA;
|
865 |
|
|
IF OP1out_zero='1' THEN
|
866 |
|
|
OP1out <= (OTHERS => '0');
|
867 |
|
|
ELSIF from_SR='1' THEN
|
868 |
|
|
OP1out(15 downto 0) <= Flags;
|
869 |
|
|
ELSIF ea_data_OP1='1' AND set_store_in_tmp='1' THEN
|
870 |
|
|
OP1out <= ea_data;
|
871 |
|
|
END IF;
|
872 |
|
|
END PROCESS;
|
873 |
|
|
|
874 |
|
|
-----------------------------------------------------------------------------
|
875 |
|
|
-- set source regaddr
|
876 |
|
|
-----------------------------------------------------------------------------
|
877 |
|
|
PROCESS (opcode, Flags, movem_addr, movem_presub, movem_regaddr, source_lowbits, source_areg, from_USP, rf_source_addr_tmp)
|
878 |
|
|
BEGIN
|
879 |
|
|
rf_source_addr <= rf_source_addr_tmp;
|
880 |
|
|
IF rf_source_addr_tmp(3 downto 0)="1111" AND from_USP='0' THEN
|
881 |
|
|
rf_source_addr(4) <= Flags(13);
|
882 |
|
|
END IF;
|
883 |
|
|
IF movem_addr='1' THEN
|
884 |
|
|
IF movem_presub='1' THEN
|
885 |
|
|
rf_source_addr_tmp <= "000"&(movem_regaddr XOR "1111");
|
886 |
|
|
ELSE
|
887 |
|
|
rf_source_addr_tmp <= "000"&movem_regaddr;
|
888 |
|
|
END IF;
|
889 |
|
|
ELSIF from_USP='1' THEN
|
890 |
|
|
rf_source_addr_tmp <= "0001111";
|
891 |
|
|
ELSIF source_lowbits='1' THEN
|
892 |
|
|
rf_source_addr_tmp <= "000"&source_areg&opcode(2 downto 0);
|
893 |
|
|
ELSE
|
894 |
|
|
rf_source_addr_tmp <= "000"&source_areg&opcode(11 downto 9);
|
895 |
|
|
END IF;
|
896 |
|
|
END PROCESS;
|
897 |
|
|
|
898 |
|
|
-----------------------------------------------------------------------------
|
899 |
|
|
-- set OP2
|
900 |
|
|
-----------------------------------------------------------------------------
|
901 |
|
|
PROCESS (OP2out, reg_QB, opcode, datatype, OP2out_one, exec_EXT, exec_MOVEQ, EXEC_ADDQ, use_direct_data, data_write_tmp, ea_data_OP1, set_store_in_tmp, ea_data)
|
902 |
|
|
BEGIN
|
903 |
|
|
OP2out(15 downto 0) <= reg_QB(15 downto 0);
|
904 |
|
|
OP2out(31 downto 16) <= (OTHERS => OP2out(15));
|
905 |
|
|
IF OP2out_one='1' THEN
|
906 |
|
|
OP2out(15 downto 0) <= "1111111111111111";
|
907 |
|
|
ELSIF exec_EXT='1' THEN
|
908 |
|
|
IF opcode(6)='0' THEN --ext.w
|
909 |
|
|
OP2out(15 downto 8) <= (OTHERS => OP2out(7));
|
910 |
|
|
END IF;
|
911 |
|
|
ELSIF use_direct_data='1' THEN
|
912 |
|
|
OP2out <= data_write_tmp;
|
913 |
|
|
ELSIF ea_data_OP1='0' AND set_store_in_tmp='1' THEN
|
914 |
|
|
OP2out <= ea_data;
|
915 |
|
|
ELSIF exec_MOVEQ='1' THEN
|
916 |
|
|
OP2out(7 downto 0) <= opcode(7 downto 0);
|
917 |
|
|
OP2out(15 downto 8) <= (OTHERS => opcode(7));
|
918 |
|
|
ELSIF exec_ADDQ='1' THEN
|
919 |
|
|
OP2out(2 downto 0) <= opcode(11 downto 9);
|
920 |
|
|
IF opcode(11 downto 9)="000" THEN
|
921 |
|
|
OP2out(3) <='1';
|
922 |
|
|
ELSE
|
923 |
|
|
OP2out(3) <='0';
|
924 |
|
|
END IF;
|
925 |
|
|
OP2out(15 downto 4) <= (OTHERS => '0');
|
926 |
|
|
ELSIF datatype="10" THEN
|
927 |
|
|
OP2out(31 downto 16) <= reg_QB(31 downto 16);
|
928 |
|
|
END IF;
|
929 |
|
|
END PROCESS;
|
930 |
|
|
|
931 |
|
|
-----------------------------------------------------------------------------
|
932 |
|
|
-- addsub
|
933 |
|
|
-----------------------------------------------------------------------------
|
934 |
|
|
PROCESS (OP1out, OP2out, presub, postadd, execOPC, OP2out_one, datatype, use_SP, use_XZFlag, use_XFlag, Flags, setaddsub)
|
935 |
|
|
BEGIN
|
936 |
|
|
addsub_a <= OP1out;
|
937 |
|
|
addsub_b <= OP2out;
|
938 |
|
|
addsub <= NOT presub;
|
939 |
|
|
c_in(0) <='0';
|
940 |
|
|
IF execOPC='0' AND OP2out_one='0' THEN
|
941 |
|
|
IF datatype="00" AND use_SP='0' THEN
|
942 |
|
|
addsub_b <= "00000000000000000000000000000001";
|
943 |
|
|
ELSIF datatype="10" AND (presub OR postadd)='1' THEN
|
944 |
|
|
addsub_b <= "00000000000000000000000000000100";
|
945 |
|
|
ELSE
|
946 |
|
|
addsub_b <= "00000000000000000000000000000010";
|
947 |
|
|
END IF;
|
948 |
|
|
ELSE
|
949 |
|
|
IF (use_XZFlag='1' OR use_XFlag='1') AND Flags(4)='1' THEN
|
950 |
|
|
c_in(0) <= '1';
|
951 |
|
|
END IF;
|
952 |
|
|
addsub <= setaddsub;
|
953 |
|
|
END IF;
|
954 |
|
|
END PROCESS;
|
955 |
|
|
|
956 |
|
|
-----------------------------------------------------------------------------
|
957 |
|
|
-- Write Reg
|
958 |
|
|
-----------------------------------------------------------------------------
|
959 |
|
|
PROCESS (clkena, OP1in, datatype, presub, postadd, endOPC, regwrena, state, execOPC, last_data_read, movem_addr, rf_dest_addr, reg_QA)
|
960 |
|
|
BEGIN
|
961 |
|
|
Lwrena <= '0';
|
962 |
|
|
Hwrena <= '0';
|
963 |
|
|
registerin <= OP1in;
|
964 |
|
|
|
965 |
|
|
IF (presub='1' OR postadd='1') AND endOPC='0' THEN -- -(An)+
|
966 |
|
|
Hwrena <= '1';
|
967 |
|
|
Lwrena <= '1';
|
968 |
|
|
ELSIF Regwrena='1' THEN --read (mem)
|
969 |
|
|
Lwrena <= '1';
|
970 |
|
|
CASE datatype IS
|
971 |
|
|
WHEN "00" => --BYTE
|
972 |
|
|
registerin(15 downto 8) <= reg_QA(15 downto 8);
|
973 |
|
|
WHEN "01" => --WORD
|
974 |
|
|
IF rf_dest_addr(3)='1' OR movem_addr='1' THEN
|
975 |
|
|
Hwrena <='1';
|
976 |
|
|
END IF;
|
977 |
|
|
WHEN OTHERS => --LONG
|
978 |
|
|
Hwrena <= '1';
|
979 |
|
|
END CASE;
|
980 |
|
|
END IF;
|
981 |
|
|
END PROCESS;
|
982 |
|
|
|
983 |
|
|
------------------------------------------------------------------------------
|
984 |
|
|
--ALU
|
985 |
|
|
------------------------------------------------------------------------------
|
986 |
|
|
PROCESS (opcode, OP1in, OP1out, OP2out, datatype, c_out, exec_ABCD, exec_SBCD, exec_CPMAW, exec_MOVESR, bits_out, Flags, flag_z, use_XZFlag, addsub_ofl,
|
987 |
|
|
dummy_s, dummy_a, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, addsub_q, movem_addr, data_read, exec_MULU, exec_DIVU, exec_OR,
|
988 |
|
|
exec_AND, exec_Scc, exec_EOR, exec_MOVE, exec_exg, exec_ROT, execOPC, exec_swap, exec_Bits, rot_out, dummy_mulu, dummy_div, save_memaddr, memaddr,
|
989 |
|
|
memaddr_in, ea_only, get_ea_now)
|
990 |
|
|
BEGIN
|
991 |
|
|
|
992 |
|
|
--BCD_ARITH-------------------------------------------------------------------
|
993 |
|
|
--ADC
|
994 |
|
|
dummy_a <= niba_hc&(niba_h(4 downto 1)+('0',niba_hc,niba_hc,'0'))&(niba_l(4 downto 1)+('0',niba_lc,niba_lc,'0'));
|
995 |
|
|
niba_l <= ('0'&OP1out(3 downto 0)&'1') + ('0'&OP2out(3 downto 0)&Flags(4));
|
996 |
|
|
niba_lc <= niba_l(5) OR (niba_l(4) AND niba_l(3)) OR (niba_l(4) AND niba_l(2));
|
997 |
|
|
|
998 |
|
|
niba_h <= ('0'&OP1out(7 downto 4)&'1') + ('0'&OP2out(7 downto 4)&niba_lc);
|
999 |
|
|
niba_hc <= niba_h(5) OR (niba_h(4) AND niba_h(3)) OR (niba_h(4) AND niba_h(2));
|
1000 |
|
|
--SBC
|
1001 |
|
|
dummy_s <= nibs_hc&(nibs_h(4 downto 1)-('0',nibs_hc,nibs_hc,'0'))&(nibs_l(4 downto 1)-('0',nibs_lc,nibs_lc,'0'));
|
1002 |
|
|
nibs_l <= ('0'&OP1out(3 downto 0)&'0') - ('0'&OP2out(3 downto 0)&Flags(4));
|
1003 |
|
|
nibs_lc <= nibs_l(5);
|
1004 |
|
|
|
1005 |
|
|
nibs_h <= ('0'&OP1out(7 downto 4)&'0') - ('0'&OP2out(7 downto 4)&nibs_lc);
|
1006 |
|
|
nibs_hc <= nibs_h(5);
|
1007 |
|
|
------------------------------------------------------------------------------
|
1008 |
|
|
|
1009 |
|
|
flag_z <= "000";
|
1010 |
|
|
|
1011 |
|
|
OP1in <= addsub_q;
|
1012 |
|
|
IF movem_addr='1' THEN
|
1013 |
|
|
OP1in <= data_read;
|
1014 |
|
|
ELSIF exec_ABCD='1' THEN
|
1015 |
|
|
OP1in(7 downto 0) <= dummy_a(7 downto 0);
|
1016 |
|
|
ELSIF exec_SBCD='1' THEN
|
1017 |
|
|
OP1in(7 downto 0) <= dummy_s(7 downto 0);
|
1018 |
|
|
ELSIF exec_MULU='1' THEN
|
1019 |
|
|
OP1in <= dummy_mulu;
|
1020 |
|
|
ELSIF exec_DIVU='1' AND execOPC='1' THEN
|
1021 |
|
|
OP1in <= dummy_div;
|
1022 |
|
|
ELSIF exec_OR='1' THEN
|
1023 |
|
|
OP1in <= OP2out OR OP1out;
|
1024 |
|
|
ELSIF exec_AND='1' OR exec_Scc='1' THEN
|
1025 |
|
|
OP1in <= OP2out AND OP1out;
|
1026 |
|
|
ELSIF exec_EOR='1' THEN
|
1027 |
|
|
OP1in <= OP2out XOR OP1out;
|
1028 |
|
|
ELSIF exec_MOVE='1' OR exec_exg='1' THEN
|
1029 |
|
|
OP1in <= OP2out;
|
1030 |
|
|
ELSIF exec_ROT='1' THEN
|
1031 |
|
|
OP1in <= rot_out;
|
1032 |
|
|
ELSIF save_memaddr='1' THEN
|
1033 |
|
|
OP1in <= memaddr;
|
1034 |
|
|
ELSIF get_ea_now='1' AND ea_only='1' THEN
|
1035 |
|
|
OP1in <= memaddr_in;
|
1036 |
|
|
ELSIF exec_swap='1' THEN
|
1037 |
|
|
OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
|
1038 |
|
|
ELSIF exec_bits='1' THEN
|
1039 |
|
|
OP1in <= bits_out;
|
1040 |
|
|
ELSIF exec_MOVESR='1' THEN
|
1041 |
|
|
OP1in(15 downto 0) <= Flags;
|
1042 |
|
|
END IF;
|
1043 |
|
|
|
1044 |
|
|
IF use_XZFlag='1' AND flags(2)='0' THEN
|
1045 |
|
|
flag_z <= "000";
|
1046 |
|
|
ELSIF OP1in(7 downto 0)="00000000" THEN
|
1047 |
|
|
flag_z(0) <= '1';
|
1048 |
|
|
IF OP1in(15 downto 8)="00000000" THEN
|
1049 |
|
|
flag_z(1) <= '1';
|
1050 |
|
|
IF OP1in(31 downto 16)="0000000000000000" THEN
|
1051 |
|
|
flag_z(2) <= '1';
|
1052 |
|
|
END IF;
|
1053 |
|
|
END IF;
|
1054 |
|
|
END IF;
|
1055 |
|
|
|
1056 |
|
|
-- --Flags NZVC
|
1057 |
|
|
IF datatype="00" THEN --Byte
|
1058 |
|
|
set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
|
1059 |
|
|
IF exec_ABCD='1' THEN
|
1060 |
|
|
set_flags(0) <= dummy_a(8);
|
1061 |
|
|
ELSIF exec_SBCD='1' THEN
|
1062 |
|
|
set_flags(0) <= dummy_s(8);
|
1063 |
|
|
END IF;
|
1064 |
|
|
ELSIF datatype="10" OR exec_CPMAW='1' THEN --Long
|
1065 |
|
|
set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
|
1066 |
|
|
ELSE --Word
|
1067 |
|
|
set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
|
1068 |
|
|
END IF;
|
1069 |
|
|
END PROCESS;
|
1070 |
|
|
|
1071 |
|
|
------------------------------------------------------------------------------
|
1072 |
|
|
--Flags
|
1073 |
|
|
------------------------------------------------------------------------------
|
1074 |
|
|
PROCESS (clk, reset, opcode)
|
1075 |
|
|
BEGIN
|
1076 |
|
|
IF reset='0' THEN
|
1077 |
|
|
Flags(13) <= '1';
|
1078 |
|
|
SVmode <= '1';
|
1079 |
|
|
Flags(10 downto 8) <= "111";
|
1080 |
|
|
ELSIF rising_edge(clk) THEN
|
1081 |
|
|
|
1082 |
|
|
IF clkena = '1' THEN
|
1083 |
|
|
IF directSR='1' THEN
|
1084 |
|
|
Flags <= data_read(15 downto 0);
|
1085 |
|
|
END IF;
|
1086 |
|
|
IF interrupt='1' THEN
|
1087 |
|
|
Flags(10 downto 8) <=rIPL_nr;
|
1088 |
|
|
SVmode <= '1';
|
1089 |
|
|
END IF;
|
1090 |
|
|
IF writeSR='1' OR interrupt='1' THEN
|
1091 |
|
|
Flags(13) <='1';
|
1092 |
|
|
END IF;
|
1093 |
|
|
IF endOPC='1' AND to_SR='0' THEN
|
1094 |
|
|
SVmode <= Flags(13);
|
1095 |
|
|
END IF;
|
1096 |
|
|
IF execOPC='1' AND to_SR='1' THEN
|
1097 |
|
|
Flags(7 downto 0) <= OP1in(7 downto 0); --CCR
|
1098 |
|
|
IF datatype="01" AND (opcode(14)='0' OR opcode(9)='1') THEN --move to CCR wird als word gespeichert
|
1099 |
|
|
Flags(15 downto 8) <= OP1in(15 downto 8); --SR
|
1100 |
|
|
SVmode <= OP1in(13);
|
1101 |
|
|
END IF;
|
1102 |
|
|
ELSIF Z_error='1' THEN
|
1103 |
|
|
IF opcode(8)='0' THEN
|
1104 |
|
|
Flags(3 downto 0) <= "1000";
|
1105 |
|
|
ELSE
|
1106 |
|
|
Flags(3 downto 0) <= "0100";
|
1107 |
|
|
END IF;
|
1108 |
|
|
ELSIF no_Flags='0' AND trap='0' THEN
|
1109 |
|
|
IF exec_ADD='1' THEN
|
1110 |
|
|
Flags(4) <= set_flags(0);
|
1111 |
|
|
ELSIF exec_ROT='1' AND rot_bits/="11" AND rot_nop='0' THEN
|
1112 |
|
|
Flags(4) <= rot_XC;
|
1113 |
|
|
END IF;
|
1114 |
|
|
|
1115 |
|
|
IF (exec_ADD OR exec_CMP)='1' THEN
|
1116 |
|
|
Flags(3 downto 0) <= set_flags;
|
1117 |
|
|
ELSIF decodeOPC='1' and set_exec_ROT='1' THEN
|
1118 |
|
|
Flags(1) <= '0';
|
1119 |
|
|
ELSIF exec_DIVU='1' THEN
|
1120 |
|
|
IF set_V_Flag='1' THEN
|
1121 |
|
|
Flags(3 downto 0) <= "1010";
|
1122 |
|
|
ELSE
|
1123 |
|
|
Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
|
1124 |
|
|
END IF;
|
1125 |
|
|
ELSIF exec_OR='1' OR exec_AND='1' OR exec_EOR='1' OR exec_MOVE='1' OR exec_swap='1' OR exec_MULU='1' THEN
|
1126 |
|
|
Flags(3 downto 0) <= set_flags(3 downto 2)&"00";
|
1127 |
|
|
ELSIF exec_ROT='1' THEN
|
1128 |
|
|
Flags(3 downto 2) <= set_flags(3 downto 2);
|
1129 |
|
|
Flags(0) <= rot_XC;
|
1130 |
|
|
IF rot_bits="00" THEN --ASL/ASR
|
1131 |
|
|
Flags(1) <= ((set_flags(3) XOR rot_rot) OR Flags(1));
|
1132 |
|
|
END IF;
|
1133 |
|
|
ELSIF exec_bits='1' THEN
|
1134 |
|
|
Flags(2) <= NOT one_bit_in;
|
1135 |
|
|
END IF;
|
1136 |
|
|
END IF;
|
1137 |
|
|
END IF;
|
1138 |
|
|
END IF;
|
1139 |
|
|
END PROCESS;
|
1140 |
|
|
|
1141 |
|
|
-----------------------------------------------------------------------------
|
1142 |
|
|
-- execute opcode
|
1143 |
|
|
-----------------------------------------------------------------------------
|
1144 |
|
|
PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, prefix, nextpass, condition, set_V_flag, trap, trapd, interrupt, trap_interrupt,
|
1145 |
|
|
Z_error, microaddr, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC,
|
1146 |
|
|
Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec)
|
1147 |
|
|
BEGIN
|
1148 |
|
|
TG68_PC_br8 <= '0';
|
1149 |
|
|
TG68_PC_brw <= '0';
|
1150 |
|
|
TG68_PC_nop <= '0';
|
1151 |
|
|
setstate <= "00";
|
1152 |
|
|
Regwrena <= '0';
|
1153 |
|
|
microstep <= '0';
|
1154 |
|
|
microset <= '0';
|
1155 |
|
|
postadd <= '0';
|
1156 |
|
|
presub <= '0';
|
1157 |
|
|
movem_presub <= '0';
|
1158 |
|
|
setaddsub <= '1';
|
1159 |
|
|
micronext <= "00000001";
|
1160 |
|
|
setaddrlong <= '0';
|
1161 |
|
|
setnextpass <= '0';
|
1162 |
|
|
regdirectsource <= '0';
|
1163 |
|
|
setdisp <= '0';
|
1164 |
|
|
setdispbyte <= '0';
|
1165 |
|
|
setdispbrief <= '0';
|
1166 |
|
|
setbriefext <= '0';
|
1167 |
|
|
setgetbrief <= '0';
|
1168 |
|
|
longreaddirect <= '0';
|
1169 |
|
|
dest_areg <= '0';
|
1170 |
|
|
source_areg <= '0';
|
1171 |
|
|
data_is_source <= '0';
|
1172 |
|
|
write_back <= '0';
|
1173 |
|
|
setstackaddr <= '0';
|
1174 |
|
|
writePC <= '0';
|
1175 |
|
|
writePC_add <= '0';
|
1176 |
|
|
set_TG68_PC_dec <= '0';
|
1177 |
|
|
set_directPC <= '0';
|
1178 |
|
|
set_exec_ADD <= '0';
|
1179 |
|
|
set_exec_OR <= '0';
|
1180 |
|
|
set_exec_AND <= '0';
|
1181 |
|
|
set_exec_EOR <= '0';
|
1182 |
|
|
set_exec_MOVE <= '0';
|
1183 |
|
|
set_exec_MOVEQ <= '0';
|
1184 |
|
|
set_exec_MOVESR <= '0';
|
1185 |
|
|
set_exec_ADDQ <= '0';
|
1186 |
|
|
set_exec_CMP <= '0';
|
1187 |
|
|
set_exec_ROT <= '0';
|
1188 |
|
|
set_exec_EXT <= '0';
|
1189 |
|
|
set_exec_CPMAW <= '0';
|
1190 |
|
|
OP2out_one <= '0';
|
1191 |
|
|
ea_to_pc <= '0';
|
1192 |
|
|
ea_build <= '0';
|
1193 |
|
|
get_ea_now <= '0';
|
1194 |
|
|
rot_bits <= "XX";
|
1195 |
|
|
rot_nop <= '0';
|
1196 |
|
|
set_rot_cnt <= "000001";
|
1197 |
|
|
set_movem_busy <= '0';
|
1198 |
|
|
set_get_movem_mask <= '0';
|
1199 |
|
|
save_memaddr <= '0';
|
1200 |
|
|
set_mem_addsub <= '0';
|
1201 |
|
|
exec_exg <= '0';
|
1202 |
|
|
exec_swap <= '0';
|
1203 |
|
|
exec_Bits <= '0';
|
1204 |
|
|
set_get_bitnumber <= '0';
|
1205 |
|
|
dest_hbits <= '0';
|
1206 |
|
|
source_lowbits <= '0';
|
1207 |
|
|
set_mem_rega <= '0';
|
1208 |
|
|
ea_data_OP1 <= '0';
|
1209 |
|
|
ea_only <= '0';
|
1210 |
|
|
set_direct_data <= '0';
|
1211 |
|
|
set_get_extendedOPC <= '0';
|
1212 |
|
|
set_exec_tas <= '0';
|
1213 |
|
|
OP1out_zero <= '0';
|
1214 |
|
|
use_XZFlag <= '0';
|
1215 |
|
|
use_XFlag <= '0';
|
1216 |
|
|
set_exec_ABCD <= '0';
|
1217 |
|
|
set_exec_SBCD <= '0';
|
1218 |
|
|
set_exec_MULU <= '0';
|
1219 |
|
|
set_exec_DIVU <= '0';
|
1220 |
|
|
set_exec_Scc <= '0';
|
1221 |
|
|
trap_illegal <='0';
|
1222 |
|
|
trap_priv <='0';
|
1223 |
|
|
trap_1010 <='0';
|
1224 |
|
|
trap_1111 <='0';
|
1225 |
|
|
trap_trap <='0';
|
1226 |
|
|
trap_trapv <= '0';
|
1227 |
|
|
trap <='0';
|
1228 |
|
|
set_vectoraddr <='0';
|
1229 |
|
|
writeSR <= '0';
|
1230 |
|
|
set_directSR <= '0';
|
1231 |
|
|
set_stop <= '0';
|
1232 |
|
|
from_SR <= '0';
|
1233 |
|
|
to_SR <= '0';
|
1234 |
|
|
from_USP <= '0';
|
1235 |
|
|
to_USP <= '0';
|
1236 |
|
|
illegal_write_mode <= '0';
|
1237 |
|
|
illegal_read_mode <= '0';
|
1238 |
|
|
illegal_byteaddr <= '0';
|
1239 |
|
|
no_Flags <= '0';
|
1240 |
|
|
set_PCmarker <= '0';
|
1241 |
|
|
use_SP <= '0';
|
1242 |
|
|
set_Z_error <= '0';
|
1243 |
|
|
|
1244 |
|
|
check_movep <= '0';
|
1245 |
|
|
check_chk <= '0';
|
1246 |
|
|
|
1247 |
|
|
------------------------------------------------------------------------------
|
1248 |
|
|
--Sourcepass
|
1249 |
|
|
------------------------------------------------------------------------------
|
1250 |
|
|
IF ea_only='0' AND get_ea_now='1' THEN
|
1251 |
|
|
setstate <= "10";
|
1252 |
|
|
END IF;
|
1253 |
|
|
|
1254 |
|
|
IF ea_build='1' THEN
|
1255 |
|
|
CASE opcode(5 downto 3) IS --source
|
1256 |
|
|
WHEN "010"|"011"|"100" => -- -(An)+
|
1257 |
|
|
get_ea_now <='1';
|
1258 |
|
|
setnextpass <= '1';
|
1259 |
|
|
IF opcode(4)='1' THEN
|
1260 |
|
|
set_mem_rega <= '1';
|
1261 |
|
|
ELSE
|
1262 |
|
|
set_mem_addsub <= '1';
|
1263 |
|
|
END IF;
|
1264 |
|
|
IF opcode(3)='1' THEN --(An)+
|
1265 |
|
|
postadd <= '1';
|
1266 |
|
|
IF opcode(2 downto 0)="111" THEN
|
1267 |
|
|
use_SP <= '1';
|
1268 |
|
|
END IF;
|
1269 |
|
|
END IF;
|
1270 |
|
|
IF opcode(5)='1' THEN -- -(An)
|
1271 |
|
|
presub <= '1';
|
1272 |
|
|
IF opcode(2 downto 0)="111" THEN
|
1273 |
|
|
use_SP <= '1';
|
1274 |
|
|
END IF;
|
1275 |
|
|
END IF;
|
1276 |
|
|
IF opcode(4 downto 3)/="10" THEN
|
1277 |
|
|
regwrena <= '1';
|
1278 |
|
|
END IF;
|
1279 |
|
|
WHEN "101" => --(d16,An)
|
1280 |
|
|
microstep <='1';
|
1281 |
|
|
micronext <="00000110";
|
1282 |
|
|
setgetbrief <='1';
|
1283 |
|
|
set_mem_regA <= '1';
|
1284 |
|
|
WHEN "110" => --(d8,An,Xn)
|
1285 |
|
|
microstep <='1';
|
1286 |
|
|
micronext <="00001000";
|
1287 |
|
|
setgetbrief <='1';
|
1288 |
|
|
set_mem_regA <= '1';
|
1289 |
|
|
WHEN "111" =>
|
1290 |
|
|
CASE opcode(2 downto 0) IS
|
1291 |
|
|
WHEN "000" => --(xxxx).w
|
1292 |
|
|
micronext <="00000010";
|
1293 |
|
|
microstep <='1';
|
1294 |
|
|
WHEN "001" => --(xxxx).l
|
1295 |
|
|
longreaddirect <= '1';
|
1296 |
|
|
micronext <="00000010";
|
1297 |
|
|
microstep <='1';
|
1298 |
|
|
WHEN "010" => --(d16,PC)
|
1299 |
|
|
microstep <='1';
|
1300 |
|
|
micronext <="00000110";
|
1301 |
|
|
setgetbrief <= '1';
|
1302 |
|
|
set_PCmarker <= '1';
|
1303 |
|
|
WHEN "011" => --(d8,PC,Xn)
|
1304 |
|
|
microstep <='1';
|
1305 |
|
|
micronext <="00001000";
|
1306 |
|
|
setgetbrief <= '1';
|
1307 |
|
|
set_PCmarker <= '1';
|
1308 |
|
|
WHEN "100" => --#data
|
1309 |
|
|
setnextpass <= '1';
|
1310 |
|
|
set_direct_data <= '1';
|
1311 |
|
|
IF datatype="10" THEN
|
1312 |
|
|
longreaddirect <= '1';
|
1313 |
|
|
END IF;
|
1314 |
|
|
WHEN OTHERS =>
|
1315 |
|
|
END CASE;
|
1316 |
|
|
WHEN OTHERS =>
|
1317 |
|
|
END CASE;
|
1318 |
|
|
END IF;
|
1319 |
|
|
------------------------------------------------------------------------------
|
1320 |
|
|
--prepere opcode
|
1321 |
|
|
------------------------------------------------------------------------------
|
1322 |
|
|
CASE opcode(7 downto 6) IS
|
1323 |
|
|
WHEN "00" => datatype <= "00"; --Byte
|
1324 |
|
|
WHEN "01" => datatype <= "01"; --Word
|
1325 |
|
|
WHEN OTHERS => datatype <= "10"; --Long
|
1326 |
|
|
END CASE;
|
1327 |
|
|
|
1328 |
|
|
IF execOPC='1' AND endOPC='0' AND exec_write_back='1' THEN
|
1329 |
|
|
setstate <="11";
|
1330 |
|
|
END IF;
|
1331 |
|
|
|
1332 |
|
|
------------------------------------------------------------------------------
|
1333 |
|
|
--test illegal mode
|
1334 |
|
|
------------------------------------------------------------------------------
|
1335 |
|
|
IF (opcode(5 downto 3)="111" AND opcode(2 downto 1)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
|
1336 |
|
|
illegal_write_mode <= '1';
|
1337 |
|
|
END IF;
|
1338 |
|
|
IF (opcode(5 downto 2)="1111" AND opcode(1 downto 0)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
|
1339 |
|
|
illegal_read_mode <= '1';
|
1340 |
|
|
END IF;
|
1341 |
|
|
IF opcode(5 downto 3)="001" AND datatype="00" THEN
|
1342 |
|
|
illegal_byteaddr <= '1';
|
1343 |
|
|
END IF;
|
1344 |
|
|
|
1345 |
|
|
|
1346 |
|
|
CASE opcode(15 downto 12) IS
|
1347 |
|
|
-- 0000 ----------------------------------------------------------------------------
|
1348 |
|
|
WHEN "0000" =>
|
1349 |
|
|
--hier muss noch MOVEP rein
|
1350 |
|
|
IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
|
1351 |
|
|
trap_illegal <= '1';
|
1352 |
|
|
trap <= '1';
|
1353 |
|
|
ELSE
|
1354 |
|
|
IF opcode(8)='1' OR opcode(11 downto 8)="1000" THEN --Bits
|
1355 |
|
|
IF execOPC='1' AND get_extendedOPC='0' THEN
|
1356 |
|
|
IF opcode(7 downto 6)/="00" AND endOPC='1' THEN
|
1357 |
|
|
regwrena <= '1';
|
1358 |
|
|
END IF;
|
1359 |
|
|
exec_Bits <= '1';
|
1360 |
|
|
ea_data_OP1 <= '1';
|
1361 |
|
|
END IF;
|
1362 |
|
|
-- IF get_extendedOPC='1' THEN
|
1363 |
|
|
-- datatype <= "01"; --Word
|
1364 |
|
|
-- ELS
|
1365 |
|
|
IF opcode(5 downto 4)="00" THEN
|
1366 |
|
|
datatype <= "10"; --Long
|
1367 |
|
|
ELSE
|
1368 |
|
|
datatype <= "00"; --Byte
|
1369 |
|
|
IF opcode(7 downto 6)/="00" THEN
|
1370 |
|
|
write_back <= '1';
|
1371 |
|
|
END IF;
|
1372 |
|
|
END IF;
|
1373 |
|
|
IF decodeOPC='1' THEN
|
1374 |
|
|
ea_build <= '1';
|
1375 |
|
|
IF opcode(8)='0' THEN
|
1376 |
|
|
IF opcode(5 downto 4)/="00" THEN --Dn, An
|
1377 |
|
|
set_get_extendedOPC <= '1';
|
1378 |
|
|
END IF;
|
1379 |
|
|
set_get_bitnumber <= '1';
|
1380 |
|
|
END IF;
|
1381 |
|
|
END IF;
|
1382 |
|
|
ELSE --andi, ...xxxi
|
1383 |
|
|
IF opcode(11 downto 8)="0000" THEN --ORI
|
1384 |
|
|
set_exec_OR <= '1';
|
1385 |
|
|
END IF;
|
1386 |
|
|
IF opcode(11 downto 8)="0010" THEN --ANDI
|
1387 |
|
|
set_exec_AND <= '1';
|
1388 |
|
|
END IF;
|
1389 |
|
|
IF opcode(11 downto 8)="0100" OR opcode(11 downto 8)="0110" THEN --SUBI, ADDI
|
1390 |
|
|
set_exec_ADD <= '1';
|
1391 |
|
|
END IF;
|
1392 |
|
|
IF opcode(11 downto 8)="1010" THEN --EORI
|
1393 |
|
|
set_exec_EOR <= '1';
|
1394 |
|
|
END IF;
|
1395 |
|
|
IF opcode(11 downto 8)="1100" THEN --CMPI
|
1396 |
|
|
set_exec_CMP <= '1';
|
1397 |
|
|
ELSIF trap='0' THEN
|
1398 |
|
|
write_back <= '1';
|
1399 |
|
|
END IF;
|
1400 |
|
|
IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec_AND OR set_exec_OR OR set_exec_EOR)='1' THEN --SR
|
1401 |
|
|
-- IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="1010") THEN --SR
|
1402 |
|
|
IF SVmode='0' AND opcode(6)='1' THEN --SR
|
1403 |
|
|
trap_priv <= '1';
|
1404 |
|
|
trap <= '1';
|
1405 |
|
|
ELSE
|
1406 |
|
|
from_SR <= '1';
|
1407 |
|
|
to_SR <= '1';
|
1408 |
|
|
IF decodeOPC='1' THEN
|
1409 |
|
|
setnextpass <= '1';
|
1410 |
|
|
set_direct_data <= '1';
|
1411 |
|
|
END IF;
|
1412 |
|
|
END IF;
|
1413 |
|
|
ELSE
|
1414 |
|
|
IF decodeOPC='1' THEN
|
1415 |
|
|
IF opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="0100" --ANDI, ORI, SUBI
|
1416 |
|
|
OR opcode(11 downto 8)="0110" OR opcode(11 downto 8)="1010" OR opcode(11 downto 8)="1100" THEN --ADDI, EORI, CMPI
|
1417 |
|
|
-- IF (set_exec_AND OR set_exec_OR OR set_exec_ADD --ANDI, ORI, SUBI
|
1418 |
|
|
-- OR set_exec_EOR OR set_exec_CMP)='1' THEN --ADDI, EORI, CMPI
|
1419 |
|
|
|
1420 |
|
|
microstep <='1';
|
1421 |
|
|
micronext <="00101000";
|
1422 |
|
|
set_direct_data <= '1';
|
1423 |
|
|
IF datatype="10" THEN
|
1424 |
|
|
longreaddirect <= '1';
|
1425 |
|
|
END IF;
|
1426 |
|
|
END IF;
|
1427 |
|
|
END IF;
|
1428 |
|
|
|
1429 |
|
|
IF execOPC='1' THEN
|
1430 |
|
|
ea_data_OP1 <= '1';
|
1431 |
|
|
IF opcode(11 downto 8)/="1100" THEN --CMPI
|
1432 |
|
|
IF endOPC='1' THEN
|
1433 |
|
|
Regwrena <= '1';
|
1434 |
|
|
END IF;
|
1435 |
|
|
END IF;
|
1436 |
|
|
IF opcode(11 downto 8)="1100" OR opcode(11 downto 8)="0100" THEN --CMPI, SUBI
|
1437 |
|
|
setaddsub <= '0';
|
1438 |
|
|
END IF;
|
1439 |
|
|
END IF;
|
1440 |
|
|
END IF;
|
1441 |
|
|
END IF;
|
1442 |
|
|
END IF;
|
1443 |
|
|
|
1444 |
|
|
-- 0001, 0010, 0011 -----------------------------------------------------------------
|
1445 |
|
|
WHEN "0001"|"0010"|"0011" => --move.b, move.l, move.w
|
1446 |
|
|
set_exec_MOVE <= '1';
|
1447 |
|
|
IF opcode(8 downto 6)="001" THEN
|
1448 |
|
|
no_Flags <= '1';
|
1449 |
|
|
END IF;
|
1450 |
|
|
IF opcode(5 downto 4)="00" THEN --Dn, An
|
1451 |
|
|
regdirectsource <= '1';
|
1452 |
|
|
END IF;
|
1453 |
|
|
CASE opcode(13 downto 12) IS
|
1454 |
|
|
WHEN "01" => datatype <= "00"; --Byte
|
1455 |
|
|
WHEN "10" => datatype <= "10"; --Long
|
1456 |
|
|
WHEN OTHERS => datatype <= "01"; --Word
|
1457 |
|
|
END CASE;
|
1458 |
|
|
source_lowbits <= '1'; -- Dn=> An=>
|
1459 |
|
|
IF opcode(3)='1' THEN
|
1460 |
|
|
source_areg <= '1';
|
1461 |
|
|
END IF;
|
1462 |
|
|
IF getbrief='1' AND nextpass='1' THEN -- =>(d16,An) =>(d8,An,Xn)
|
1463 |
|
|
set_mem_rega <= '1';
|
1464 |
|
|
END IF;
|
1465 |
|
|
|
1466 |
|
|
IF execOPC='1' AND opcode(8 downto 7)="00" THEN
|
1467 |
|
|
Regwrena <= '1';
|
1468 |
|
|
END IF;
|
1469 |
|
|
|
1470 |
|
|
IF nextpass='1' OR execOPC='1' OR opcode(5 downto 4)="00" THEN
|
1471 |
|
|
dest_hbits <= '1';
|
1472 |
|
|
IF opcode(8 downto 6)/="000" THEN
|
1473 |
|
|
dest_areg <= '1';
|
1474 |
|
|
END IF;
|
1475 |
|
|
END IF;
|
1476 |
|
|
|
1477 |
|
|
IF decodeOPC='1' THEN
|
1478 |
|
|
ea_build <= '1';
|
1479 |
|
|
END IF;
|
1480 |
|
|
|
1481 |
|
|
IF prefix='0' AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
|
1482 |
|
|
CASE opcode(8 downto 6) IS --destination
|
1483 |
|
|
-- WHEN "000" => --Dn
|
1484 |
|
|
-- WHEN "001" => --An
|
1485 |
|
|
WHEN "010"|"011"|"100" => --destination -(an)+
|
1486 |
|
|
IF opcode(7)='1' THEN
|
1487 |
|
|
set_mem_rega <= '1';
|
1488 |
|
|
ELSE
|
1489 |
|
|
set_mem_addsub <= '1';
|
1490 |
|
|
END IF;
|
1491 |
|
|
IF opcode(6)='1' THEN --(An)+
|
1492 |
|
|
postadd <= '1';
|
1493 |
|
|
IF opcode(11 downto 9)="111" THEN
|
1494 |
|
|
use_SP <= '1';
|
1495 |
|
|
END IF;
|
1496 |
|
|
END IF;
|
1497 |
|
|
IF opcode(8)='1' THEN -- -(An)
|
1498 |
|
|
presub <= '1';
|
1499 |
|
|
IF opcode(11 downto 9)="111" THEN
|
1500 |
|
|
use_SP <= '1';
|
1501 |
|
|
END IF;
|
1502 |
|
|
END IF;
|
1503 |
|
|
IF opcode(7 downto 6)/="10" THEN
|
1504 |
|
|
regwrena <= '1';
|
1505 |
|
|
END IF;
|
1506 |
|
|
setstate <= "11";
|
1507 |
|
|
microstep <='1'; --nop
|
1508 |
|
|
WHEN "101" => --(d16,An)
|
1509 |
|
|
microstep <='1';
|
1510 |
|
|
micronext <="00001011";
|
1511 |
|
|
set_mem_regA <= '1';
|
1512 |
|
|
setgetbrief <= '1';
|
1513 |
|
|
WHEN "110" => --(d8,An,Xn)
|
1514 |
|
|
microstep <='1';
|
1515 |
|
|
micronext <="00001110";
|
1516 |
|
|
set_mem_regA <= '1';
|
1517 |
|
|
setgetbrief <= '1';
|
1518 |
|
|
WHEN "111" =>
|
1519 |
|
|
CASE opcode(11 downto 9) IS
|
1520 |
|
|
WHEN "000" => --(xxxx).w
|
1521 |
|
|
microstep <='1';
|
1522 |
|
|
micronext <="00000011";
|
1523 |
|
|
WHEN "001" => --(xxxx).l
|
1524 |
|
|
longreaddirect <= '1';
|
1525 |
|
|
microstep <='1';
|
1526 |
|
|
micronext <="00000011";
|
1527 |
|
|
WHEN OTHERS =>
|
1528 |
|
|
END CASE;
|
1529 |
|
|
WHEN OTHERS =>
|
1530 |
|
|
END CASE;
|
1531 |
|
|
END IF;
|
1532 |
|
|
-- 0100 ----------------------------------------------------------------------------
|
1533 |
|
|
WHEN "0100" => --rts_group
|
1534 |
|
|
IF opcode(8)='1' THEN --lea
|
1535 |
|
|
IF opcode(6)='1' THEN --lea
|
1536 |
|
|
IF opcode(7)='1' THEN
|
1537 |
|
|
ea_only <= '1';
|
1538 |
|
|
IF opcode(5 downto 3)="010" THEN --lea (Am),An
|
1539 |
|
|
set_exec_move <='1';
|
1540 |
|
|
no_Flags <='1';
|
1541 |
|
|
dest_areg <= '1';
|
1542 |
|
|
dest_hbits <= '1';
|
1543 |
|
|
source_lowbits <= '1';
|
1544 |
|
|
source_areg <= '1';
|
1545 |
|
|
IF execOPC='1' THEN
|
1546 |
|
|
Regwrena <= '1';
|
1547 |
|
|
END IF;
|
1548 |
|
|
ELSE
|
1549 |
|
|
IF decodeOPC='1' THEN
|
1550 |
|
|
ea_build <= '1';
|
1551 |
|
|
END IF;
|
1552 |
|
|
END IF;
|
1553 |
|
|
IF get_ea_now='1' THEN
|
1554 |
|
|
dest_areg <= '1';
|
1555 |
|
|
dest_hbits <= '1';
|
1556 |
|
|
regwrena <= '1';
|
1557 |
|
|
END IF;
|
1558 |
|
|
ELSE
|
1559 |
|
|
trap_illegal <= '1';
|
1560 |
|
|
trap <= '1';
|
1561 |
|
|
END IF;
|
1562 |
|
|
ELSE --chk
|
1563 |
|
|
trap_illegal <= '1';
|
1564 |
|
|
trap <= '1';
|
1565 |
|
|
check_chk <= '1';
|
1566 |
|
|
END IF;
|
1567 |
|
|
ELSE
|
1568 |
|
|
CASE opcode(11 downto 9) IS
|
1569 |
|
|
WHEN "000"=>
|
1570 |
|
|
IF decodeOPC='1' THEN
|
1571 |
|
|
ea_build <= '1';
|
1572 |
|
|
END IF;
|
1573 |
|
|
IF opcode(7downto 6)="11" THEN --move from SR
|
1574 |
|
|
set_exec_MOVESR <= '1';
|
1575 |
|
|
datatype <= "01";
|
1576 |
|
|
write_back <='1'; -- im 68000 wird auch erst gelesen
|
1577 |
|
|
IF execOPC='1' THEN
|
1578 |
|
|
IF endOPC='1' THEN
|
1579 |
|
|
Regwrena <= '1';
|
1580 |
|
|
END IF;
|
1581 |
|
|
END IF;
|
1582 |
|
|
ELSE --negx
|
1583 |
|
|
use_XFlag <= '1';
|
1584 |
|
|
write_back <='1';
|
1585 |
|
|
set_exec_ADD <= '1';
|
1586 |
|
|
setaddsub <='0';
|
1587 |
|
|
IF execOPC='1' THEN
|
1588 |
|
|
source_lowbits <= '1';
|
1589 |
|
|
OP1out_zero <= '1';
|
1590 |
|
|
IF endOPC='1' THEN
|
1591 |
|
|
Regwrena <= '1';
|
1592 |
|
|
END IF;
|
1593 |
|
|
END IF;
|
1594 |
|
|
END IF;
|
1595 |
|
|
WHEN "001"=>
|
1596 |
|
|
IF opcode(7downto 6)="11" THEN --move from CCR 68010
|
1597 |
|
|
trap_illegal <= '1';
|
1598 |
|
|
trap <= '1';
|
1599 |
|
|
ELSE --clr
|
1600 |
|
|
IF decodeOPC='1' THEN
|
1601 |
|
|
ea_build <= '1';
|
1602 |
|
|
END IF;
|
1603 |
|
|
write_back <='1';
|
1604 |
|
|
set_exec_AND <= '1';
|
1605 |
|
|
IF execOPC='1' THEN
|
1606 |
|
|
OP1out_zero <= '1';
|
1607 |
|
|
IF endOPC='1' THEN
|
1608 |
|
|
Regwrena <= '1';
|
1609 |
|
|
END IF;
|
1610 |
|
|
END IF;
|
1611 |
|
|
END IF;
|
1612 |
|
|
WHEN "010"=>
|
1613 |
|
|
IF decodeOPC='1' THEN
|
1614 |
|
|
ea_build <= '1';
|
1615 |
|
|
END IF;
|
1616 |
|
|
IF opcode(7downto 6)="11" THEN --move to CCR
|
1617 |
|
|
set_exec_MOVE <= '1';
|
1618 |
|
|
datatype <= "01";
|
1619 |
|
|
IF execOPC='1' THEN
|
1620 |
|
|
source_lowbits <= '1';
|
1621 |
|
|
to_SR <= '1';
|
1622 |
|
|
END IF;
|
1623 |
|
|
ELSE --neg
|
1624 |
|
|
write_back <='1';
|
1625 |
|
|
set_exec_ADD <= '1';
|
1626 |
|
|
setaddsub <='0';
|
1627 |
|
|
IF execOPC='1' THEN
|
1628 |
|
|
source_lowbits <= '1';
|
1629 |
|
|
OP1out_zero <= '1';
|
1630 |
|
|
IF endOPC='1' THEN
|
1631 |
|
|
Regwrena <= '1';
|
1632 |
|
|
END IF;
|
1633 |
|
|
END IF;
|
1634 |
|
|
END IF;
|
1635 |
|
|
WHEN "011"=> --not, move toSR
|
1636 |
|
|
IF opcode(7downto 6)="11" THEN --move to SR
|
1637 |
|
|
IF SVmode='1' THEN
|
1638 |
|
|
IF decodeOPC='1' THEN
|
1639 |
|
|
ea_build <= '1';
|
1640 |
|
|
END IF;
|
1641 |
|
|
set_exec_MOVE <= '1';
|
1642 |
|
|
datatype <= "01";
|
1643 |
|
|
IF execOPC='1' THEN
|
1644 |
|
|
source_lowbits <= '1';
|
1645 |
|
|
to_SR <= '1';
|
1646 |
|
|
END IF;
|
1647 |
|
|
ELSE
|
1648 |
|
|
trap_priv <= '1';
|
1649 |
|
|
trap <= '1';
|
1650 |
|
|
END IF;
|
1651 |
|
|
ELSE --not
|
1652 |
|
|
IF decodeOPC='1' THEN
|
1653 |
|
|
ea_build <= '1';
|
1654 |
|
|
END IF;
|
1655 |
|
|
write_back <='1';
|
1656 |
|
|
set_exec_EOR <= '1';
|
1657 |
|
|
IF execOPC='1' THEN
|
1658 |
|
|
OP2out_one <= '1';
|
1659 |
|
|
ea_data_OP1 <= '1';
|
1660 |
|
|
IF endOPC='1' THEN
|
1661 |
|
|
Regwrena <= '1';
|
1662 |
|
|
END IF;
|
1663 |
|
|
END IF;
|
1664 |
|
|
END IF;
|
1665 |
|
|
WHEN "100"|"110"=>
|
1666 |
|
|
IF opcode(7)='1' THEN --movem, ext
|
1667 |
|
|
IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN --ext
|
1668 |
|
|
source_lowbits <= '1';
|
1669 |
|
|
IF decodeOPC='1' THEN
|
1670 |
|
|
set_exec_EXT <= '1';
|
1671 |
|
|
set_exec_move <= '1';
|
1672 |
|
|
END IF;
|
1673 |
|
|
IF opcode(6)='0' THEN
|
1674 |
|
|
datatype <= "01"; --WORD
|
1675 |
|
|
END IF;
|
1676 |
|
|
IF execOPC='1' THEN
|
1677 |
|
|
regwrena <= '1';
|
1678 |
|
|
END IF;
|
1679 |
|
|
ELSE --movem
|
1680 |
|
|
-- IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN --MOVEM
|
1681 |
|
|
ea_only <= '1';
|
1682 |
|
|
IF decodeOPC='1' THEN
|
1683 |
|
|
datatype <= "01"; --Word
|
1684 |
|
|
set_get_movem_mask <='1';
|
1685 |
|
|
set_get_extendedOPC <='1';
|
1686 |
|
|
|
1687 |
|
|
IF opcode(5 downto 3)="010" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" THEN
|
1688 |
|
|
set_mem_rega <= '1';
|
1689 |
|
|
setstate <= "01";
|
1690 |
|
|
IF opcode(10)='0' THEN
|
1691 |
|
|
set_movem_busy <='1';
|
1692 |
|
|
ELSE
|
1693 |
|
|
micronext <="00100010";
|
1694 |
|
|
microstep <='1';
|
1695 |
|
|
END IF;
|
1696 |
|
|
ELSE
|
1697 |
|
|
ea_build <= '1';
|
1698 |
|
|
END IF;
|
1699 |
|
|
|
1700 |
|
|
ELSE
|
1701 |
|
|
IF opcode(6)='0' THEN
|
1702 |
|
|
datatype <= "01"; --Word
|
1703 |
|
|
END IF;
|
1704 |
|
|
END IF;
|
1705 |
|
|
IF execOPC='1' THEN
|
1706 |
|
|
IF opcode(5 downto 3)="100" OR opcode(5 downto 3)="011" THEN
|
1707 |
|
|
regwrena <= '1';
|
1708 |
|
|
save_memaddr <= '1';
|
1709 |
|
|
END IF;
|
1710 |
|
|
END IF;
|
1711 |
|
|
IF get_ea_now='1' THEN
|
1712 |
|
|
set_movem_busy <= '1';
|
1713 |
|
|
IF opcode(10)='0' THEN
|
1714 |
|
|
setstate <="01";
|
1715 |
|
|
ELSE
|
1716 |
|
|
setstate <="10";
|
1717 |
|
|
END IF;
|
1718 |
|
|
END IF;
|
1719 |
|
|
IF opcode(5 downto 3)="100" THEN
|
1720 |
|
|
movem_presub <= '1';
|
1721 |
|
|
END IF;
|
1722 |
|
|
IF movem_addr='1' THEN
|
1723 |
|
|
IF opcode(10)='1' THEN
|
1724 |
|
|
regwrena <= '1';
|
1725 |
|
|
END IF;
|
1726 |
|
|
END IF;
|
1727 |
|
|
IF movem_busy='1' THEN
|
1728 |
|
|
IF opcode(10)='0' THEN
|
1729 |
|
|
setstate <="11";
|
1730 |
|
|
ELSE
|
1731 |
|
|
setstate <="10";
|
1732 |
|
|
END IF;
|
1733 |
|
|
END IF;
|
1734 |
|
|
END IF;
|
1735 |
|
|
ELSE
|
1736 |
|
|
IF opcode(10)='1' THEN --MUL, DIV 68020
|
1737 |
|
|
trap_illegal <= '1';
|
1738 |
|
|
trap <= '1';
|
1739 |
|
|
ELSE --pea, swap
|
1740 |
|
|
IF opcode(6)='1' THEN
|
1741 |
|
|
datatype <= "10";
|
1742 |
|
|
IF opcode(5 downto 3)="000" THEN --swap
|
1743 |
|
|
IF execOPC='1' THEN
|
1744 |
|
|
exec_swap <= '1';
|
1745 |
|
|
regwrena <= '1';
|
1746 |
|
|
END IF;
|
1747 |
|
|
ELSIF opcode(5 downto 3)="001" THEN --bkpt
|
1748 |
|
|
|
1749 |
|
|
ELSE --pea
|
1750 |
|
|
ea_only <= '1';
|
1751 |
|
|
IF decodeOPC='1' THEN
|
1752 |
|
|
ea_build <= '1';
|
1753 |
|
|
END IF;
|
1754 |
|
|
IF nextpass='1' AND prefix='0' THEN
|
1755 |
|
|
presub <= '1';
|
1756 |
|
|
setstackaddr <='1';
|
1757 |
|
|
set_mem_addsub <= '1';
|
1758 |
|
|
setstate <="11";
|
1759 |
|
|
microstep <='1';
|
1760 |
|
|
END IF;
|
1761 |
|
|
IF get_ea_now='1' THEN
|
1762 |
|
|
setstate <="01";
|
1763 |
|
|
END IF;
|
1764 |
|
|
END IF;
|
1765 |
|
|
ELSE --nbcd
|
1766 |
|
|
IF decodeOPC='1' THEN --nbcd
|
1767 |
|
|
ea_build <= '1';
|
1768 |
|
|
END IF;
|
1769 |
|
|
use_XFlag <= '1';
|
1770 |
|
|
write_back <='1';
|
1771 |
|
|
set_exec_ADD <= '1';
|
1772 |
|
|
set_exec_SBCD <= '1';
|
1773 |
|
|
IF execOPC='1' THEN
|
1774 |
|
|
source_lowbits <= '1';
|
1775 |
|
|
OP1out_zero <= '1';
|
1776 |
|
|
IF endOPC='1' THEN
|
1777 |
|
|
Regwrena <= '1';
|
1778 |
|
|
END IF;
|
1779 |
|
|
END IF;
|
1780 |
|
|
END IF;
|
1781 |
|
|
END IF;
|
1782 |
|
|
END IF;
|
1783 |
|
|
|
1784 |
|
|
WHEN "101"=> --tst, tas
|
1785 |
|
|
IF decodeOPC='1' THEN
|
1786 |
|
|
ea_build <= '1';
|
1787 |
|
|
END IF;
|
1788 |
|
|
IF execOPC='1' THEN
|
1789 |
|
|
dest_hbits <= '1'; --for Flags
|
1790 |
|
|
source_lowbits <= '1';
|
1791 |
|
|
-- IF opcode(3)='1' THEN --MC68020...
|
1792 |
|
|
-- source_areg <= '1';
|
1793 |
|
|
-- END IF;
|
1794 |
|
|
END IF;
|
1795 |
|
|
set_exec_MOVE <= '1';
|
1796 |
|
|
IF opcode(7 downto 6)="11" THEN --tas
|
1797 |
|
|
set_exec_tas <= '1';
|
1798 |
|
|
write_back <= '1';
|
1799 |
|
|
datatype <= "00"; --Byte
|
1800 |
|
|
IF execOPC='1' AND endOPC='1' THEN
|
1801 |
|
|
regwrena <= '1';
|
1802 |
|
|
END IF;
|
1803 |
|
|
END IF;
|
1804 |
|
|
-- WHEN "110"=>
|
1805 |
|
|
WHEN "111"=> --4EXX
|
1806 |
|
|
IF opcode(7)='1' THEN --jsr, jmp
|
1807 |
|
|
datatype <= "10";
|
1808 |
|
|
ea_only <= '1';
|
1809 |
|
|
IF nextpass='1' AND prefix='0' THEN
|
1810 |
|
|
presub <= '1';
|
1811 |
|
|
setstackaddr <='1';
|
1812 |
|
|
set_mem_addsub <= '1';
|
1813 |
|
|
setstate <="11";
|
1814 |
|
|
microstep <='1';
|
1815 |
|
|
END IF;
|
1816 |
|
|
IF decodeOPC='1' THEN
|
1817 |
|
|
ea_build <= '1';
|
1818 |
|
|
END IF;
|
1819 |
|
|
IF get_ea_now='1' THEN --jsr
|
1820 |
|
|
IF opcode(6)='0' THEN
|
1821 |
|
|
setstate <="01";
|
1822 |
|
|
END IF;
|
1823 |
|
|
ea_to_pc <= '1';
|
1824 |
|
|
IF opcode(5 downto 0)="111001" THEN
|
1825 |
|
|
writePC_add <= '1';
|
1826 |
|
|
ELSE
|
1827 |
|
|
writePC <= '1';
|
1828 |
|
|
END IF;
|
1829 |
|
|
END IF;
|
1830 |
|
|
ELSE --
|
1831 |
|
|
CASE opcode(6 downto 0) IS
|
1832 |
|
|
WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"| --trap
|
1833 |
|
|
"1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" => --trap
|
1834 |
|
|
trap_trap <='1';
|
1835 |
|
|
trap <= '1';
|
1836 |
|
|
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111" => --link
|
1837 |
|
|
datatype <= "10";
|
1838 |
|
|
IF decodeOPC='1' THEN
|
1839 |
|
|
micronext <="01000000";
|
1840 |
|
|
microstep <='1';
|
1841 |
|
|
set_exec_MOVE <= '1'; --für displacement
|
1842 |
|
|
presub <= '1';
|
1843 |
|
|
setstackaddr <='1';
|
1844 |
|
|
set_mem_addsub <= '1';
|
1845 |
|
|
source_lowbits <= '1';
|
1846 |
|
|
source_areg <= '1';
|
1847 |
|
|
END IF;
|
1848 |
|
|
IF execOPC='1' THEN
|
1849 |
|
|
setstackaddr <='1';
|
1850 |
|
|
regwrena <= '1';
|
1851 |
|
|
END IF;
|
1852 |
|
|
|
1853 |
|
|
WHEN "1011000"|"1011001"|"1011010"|"1011011"|"1011100"|"1011101"|"1011110"|"1011111" => --unlink
|
1854 |
|
|
datatype <= "10";
|
1855 |
|
|
IF decodeOPC='1' THEN
|
1856 |
|
|
setstate <= "10";
|
1857 |
|
|
set_mem_rega <= '1';
|
1858 |
|
|
ELSIF execOPC='1' THEN
|
1859 |
|
|
regwrena <= '1';
|
1860 |
|
|
exec_exg <= '1';
|
1861 |
|
|
ELSE
|
1862 |
|
|
setstackaddr <='1';
|
1863 |
|
|
regwrena <= '1';
|
1864 |
|
|
get_ea_now <= '1';
|
1865 |
|
|
ea_only <= '1';
|
1866 |
|
|
END IF;
|
1867 |
|
|
|
1868 |
|
|
WHEN "1100000"|"1100001"|"1100010"|"1100011"|"1100100"|"1100101"|"1100110"|"1100111" => --move An,USP
|
1869 |
|
|
IF SVmode='1' THEN
|
1870 |
|
|
no_Flags <= '1';
|
1871 |
|
|
to_USP <= '1';
|
1872 |
|
|
setstackaddr <= '1';
|
1873 |
|
|
source_lowbits <= '1';
|
1874 |
|
|
source_areg <= '1';
|
1875 |
|
|
set_exec_MOVE <= '1';
|
1876 |
|
|
datatype <= "10";
|
1877 |
|
|
IF execOPC='1' THEN
|
1878 |
|
|
regwrena <= '1';
|
1879 |
|
|
END IF;
|
1880 |
|
|
ELSE
|
1881 |
|
|
trap_priv <= '1';
|
1882 |
|
|
trap <= '1';
|
1883 |
|
|
END IF;
|
1884 |
|
|
WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" => --move USP,An
|
1885 |
|
|
IF SVmode='1' THEN
|
1886 |
|
|
no_Flags <= '1';
|
1887 |
|
|
from_USP <= '1';
|
1888 |
|
|
set_exec_MOVE <= '1';
|
1889 |
|
|
datatype <= "10";
|
1890 |
|
|
IF execOPC='1' THEN
|
1891 |
|
|
regwrena <= '1';
|
1892 |
|
|
END IF;
|
1893 |
|
|
ELSE
|
1894 |
|
|
trap_priv <= '1';
|
1895 |
|
|
trap <= '1';
|
1896 |
|
|
END IF;
|
1897 |
|
|
|
1898 |
|
|
WHEN "1110000" => --reset
|
1899 |
|
|
IF SVmode='0' THEN
|
1900 |
|
|
trap_priv <= '1';
|
1901 |
|
|
trap <= '1';
|
1902 |
|
|
END IF;
|
1903 |
|
|
|
1904 |
|
|
WHEN "1110001" => --nop
|
1905 |
|
|
|
1906 |
|
|
WHEN "1110010" => --stop
|
1907 |
|
|
IF SVmode='0' THEN
|
1908 |
|
|
trap_priv <= '1';
|
1909 |
|
|
trap <= '1';
|
1910 |
|
|
ELSE
|
1911 |
|
|
IF decodeOPC='1' THEN
|
1912 |
|
|
setnextpass <= '1';
|
1913 |
|
|
set_directSR <= '1';
|
1914 |
|
|
set_stop <= '1';
|
1915 |
|
|
END IF;
|
1916 |
|
|
END IF;
|
1917 |
|
|
|
1918 |
|
|
WHEN "1110011" => --rte
|
1919 |
|
|
IF SVmode='1' THEN
|
1920 |
|
|
IF decodeOPC='1' THEN
|
1921 |
|
|
datatype <= "01";
|
1922 |
|
|
setstate <= "10";
|
1923 |
|
|
postadd <= '1';
|
1924 |
|
|
setstackaddr <= '1';
|
1925 |
|
|
set_mem_rega <= '1';
|
1926 |
|
|
set_directSR <= '1';
|
1927 |
|
|
microstep <='1';
|
1928 |
|
|
micronext <= "01001000";
|
1929 |
|
|
END IF;
|
1930 |
|
|
ELSE
|
1931 |
|
|
trap_priv <= '1';
|
1932 |
|
|
trap <= '1';
|
1933 |
|
|
END IF;
|
1934 |
|
|
|
1935 |
|
|
WHEN "1110101" => --rts
|
1936 |
|
|
IF decodeOPC='1' THEN
|
1937 |
|
|
datatype <= "10";
|
1938 |
|
|
setstate <= "10";
|
1939 |
|
|
postadd <= '1';
|
1940 |
|
|
setstackaddr <= '1';
|
1941 |
|
|
set_mem_rega <= '1';
|
1942 |
|
|
set_directPC <= '1';
|
1943 |
|
|
microstep <='1';
|
1944 |
|
|
END IF;
|
1945 |
|
|
|
1946 |
|
|
WHEN "1110110" => --trapv
|
1947 |
|
|
IF Flags(1)='1' THEN
|
1948 |
|
|
trap_trapv <= '1';
|
1949 |
|
|
trap <= '1';
|
1950 |
|
|
END IF;
|
1951 |
|
|
|
1952 |
|
|
WHEN OTHERS =>
|
1953 |
|
|
trap_illegal <= '1';
|
1954 |
|
|
trap <= '1';
|
1955 |
|
|
END CASE;
|
1956 |
|
|
END IF;
|
1957 |
|
|
END CASE;
|
1958 |
|
|
END IF;
|
1959 |
|
|
|
1960 |
|
|
-- 0101 ----------------------------------------------------------------------------
|
1961 |
|
|
WHEN "0101" => --subq, addq
|
1962 |
|
|
|
1963 |
|
|
IF opcode(7 downto 6)="11" THEN --dbcc
|
1964 |
|
|
IF opcode(5 downto 3)="001" THEN --dbcc
|
1965 |
|
|
datatype <= "01"; --Word
|
1966 |
|
|
IF decodeOPC='1' THEN
|
1967 |
|
|
OP2out_one <= '1';
|
1968 |
|
|
IF condition='0' THEN
|
1969 |
|
|
Regwrena <= '1';
|
1970 |
|
|
IF c_in(2)='1' THEN
|
1971 |
|
|
micronext <="00011110";
|
1972 |
|
|
END IF;
|
1973 |
|
|
END IF;
|
1974 |
|
|
data_is_source <= '1';
|
1975 |
|
|
microstep <='1';
|
1976 |
|
|
END IF;
|
1977 |
|
|
ELSE --Scc
|
1978 |
|
|
datatype <= "00"; --Byte
|
1979 |
|
|
write_back <= '1';
|
1980 |
|
|
IF decodeOPC='1' THEN
|
1981 |
|
|
ea_build <= '1';
|
1982 |
|
|
END IF;
|
1983 |
|
|
IF condition='0' THEN
|
1984 |
|
|
set_exec_Scc <= '1';
|
1985 |
|
|
END IF;
|
1986 |
|
|
IF execOPC='1' THEN
|
1987 |
|
|
IF condition='1' THEN
|
1988 |
|
|
OP2out_one <= '1';
|
1989 |
|
|
exec_EXG <= '1';
|
1990 |
|
|
ELSE
|
1991 |
|
|
OP1out_zero <= '1';
|
1992 |
|
|
END IF;
|
1993 |
|
|
IF endOPC='1' THEN
|
1994 |
|
|
Regwrena <= '1';
|
1995 |
|
|
END IF;
|
1996 |
|
|
END IF;
|
1997 |
|
|
END IF;
|
1998 |
|
|
ELSE --addq, subq
|
1999 |
|
|
IF decodeOPC='1' THEN
|
2000 |
|
|
ea_build <= '1';
|
2001 |
|
|
END IF;
|
2002 |
|
|
IF opcode(5 downto 3)="001" THEN
|
2003 |
|
|
no_Flags <= '1';
|
2004 |
|
|
END IF;
|
2005 |
|
|
write_back <= '1';
|
2006 |
|
|
set_exec_ADDQ <= '1';
|
2007 |
|
|
set_exec_ADD <= '1';
|
2008 |
|
|
IF execOPC='1' THEN
|
2009 |
|
|
ea_data_OP1 <= '1';
|
2010 |
|
|
IF endOPC='1' THEN
|
2011 |
|
|
Regwrena <= '1';
|
2012 |
|
|
END IF;
|
2013 |
|
|
IF opcode(8)='1' THEN
|
2014 |
|
|
setaddsub <= '0';
|
2015 |
|
|
END IF;
|
2016 |
|
|
END IF;
|
2017 |
|
|
END IF;
|
2018 |
|
|
|
2019 |
|
|
-- 0110 ----------------------------------------------------------------------------
|
2020 |
|
|
WHEN "0110" => --bra,bsr,bcc
|
2021 |
|
|
datatype <= "10";
|
2022 |
|
|
|
2023 |
|
|
IF prefix='0' THEN
|
2024 |
|
|
IF opcode(11 downto 8)="0001" THEN --bsr
|
2025 |
|
|
IF opcode(7 downto 0)="00000000" THEN
|
2026 |
|
|
micronext <="00011000";
|
2027 |
|
|
ELSE
|
2028 |
|
|
micronext <="00011001";
|
2029 |
|
|
setstate <= "01";
|
2030 |
|
|
END IF;
|
2031 |
|
|
microstep <='1';
|
2032 |
|
|
presub <= '1';
|
2033 |
|
|
setstackaddr <='1';
|
2034 |
|
|
set_mem_addsub <= '1';
|
2035 |
|
|
ELSE --bra
|
2036 |
|
|
IF opcode(7 downto 0)="00000000" THEN
|
2037 |
|
|
microstep <='1';
|
2038 |
|
|
micronext <="00010010";
|
2039 |
|
|
END IF;
|
2040 |
|
|
IF condition='1' THEN
|
2041 |
|
|
TG68_PC_br8 <= '1';
|
2042 |
|
|
END IF;
|
2043 |
|
|
END IF;
|
2044 |
|
|
END IF;
|
2045 |
|
|
|
2046 |
|
|
-- 0111 ----------------------------------------------------------------------------
|
2047 |
|
|
WHEN "0111" => --moveq
|
2048 |
|
|
IF opcode(8)='0' THEN
|
2049 |
|
|
IF trap_interrupt='0' THEN
|
2050 |
|
|
datatype <= "10"; --Long
|
2051 |
|
|
Regwrena <= '1';
|
2052 |
|
|
set_exec_MOVEQ <= '1';
|
2053 |
|
|
set_exec_MOVE <= '1';
|
2054 |
|
|
dest_hbits <= '1';
|
2055 |
|
|
END IF;
|
2056 |
|
|
ELSE
|
2057 |
|
|
trap_illegal <= '1';
|
2058 |
|
|
trap <= '1';
|
2059 |
|
|
END IF;
|
2060 |
|
|
|
2061 |
|
|
-- 1000 ----------------------------------------------------------------------------
|
2062 |
|
|
WHEN "1000" => --or
|
2063 |
|
|
IF opcode(7 downto 6)="11" THEN --divu, divs
|
2064 |
|
|
IF opcode(5 downto 4)="00" THEN --Dn, An
|
2065 |
|
|
regdirectsource <= '1';
|
2066 |
|
|
END IF;
|
2067 |
|
|
IF (prefix='0' AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
|
2068 |
|
|
set_exec_DIVU <= '1';
|
2069 |
|
|
setstate <="01";
|
2070 |
|
|
microstep <='1';
|
2071 |
|
|
micronext <="10100000";
|
2072 |
|
|
END IF;
|
2073 |
|
|
IF decodeOPC='1' THEN
|
2074 |
|
|
ea_build <= '1';
|
2075 |
|
|
END IF;
|
2076 |
|
|
IF execOPC='1' AND z_error='0' AND set_V_Flag='0' THEN
|
2077 |
|
|
regwrena <= '1';
|
2078 |
|
|
END IF;
|
2079 |
|
|
IF (prefix='1' AND nextpass='1') OR execOPC='1' THEN
|
2080 |
|
|
dest_hbits <= '1';
|
2081 |
|
|
source_lowbits <='1';
|
2082 |
|
|
ELSE
|
2083 |
|
|
datatype <= "01";
|
2084 |
|
|
END IF;
|
2085 |
|
|
|
2086 |
|
|
|
2087 |
|
|
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --sbcd, pack , unpack
|
2088 |
|
|
IF opcode(7 downto 6)="00" THEN --sbcd
|
2089 |
|
|
use_XZFlag <= '1';
|
2090 |
|
|
set_exec_ADD <= '1';
|
2091 |
|
|
set_exec_SBCD <= '1';
|
2092 |
|
|
IF opcode(3)='1' THEN
|
2093 |
|
|
write_back <= '1';
|
2094 |
|
|
IF decodeOPC='1' THEN
|
2095 |
|
|
set_direct_data <= '1';
|
2096 |
|
|
setstate <= "10";
|
2097 |
|
|
set_mem_addsub <= '1';
|
2098 |
|
|
presub <= '1';
|
2099 |
|
|
microstep <='1';
|
2100 |
|
|
micronext <="00110000";
|
2101 |
|
|
END IF;
|
2102 |
|
|
END IF;
|
2103 |
|
|
IF execOPC='1' THEN
|
2104 |
|
|
ea_data_OP1 <= '1';
|
2105 |
|
|
dest_hbits <= '1';
|
2106 |
|
|
source_lowbits <='1';
|
2107 |
|
|
IF endOPC='1' THEN
|
2108 |
|
|
Regwrena <= '1';
|
2109 |
|
|
END IF;
|
2110 |
|
|
END IF;
|
2111 |
|
|
ELSE --pack, unpack
|
2112 |
|
|
trap_illegal <= '1';
|
2113 |
|
|
trap <= '1';
|
2114 |
|
|
END IF;
|
2115 |
|
|
ELSE --or
|
2116 |
|
|
set_exec_OR <= '1';
|
2117 |
|
|
IF opcode(8)='1' THEN
|
2118 |
|
|
write_back <= '1';
|
2119 |
|
|
END IF;
|
2120 |
|
|
IF decodeOPC='1' THEN
|
2121 |
|
|
ea_build <= '1';
|
2122 |
|
|
END IF;
|
2123 |
|
|
IF execOPC='1' THEN
|
2124 |
|
|
IF endOPC='1' THEN
|
2125 |
|
|
Regwrena <= '1';
|
2126 |
|
|
END IF;
|
2127 |
|
|
IF opcode(8)='1' THEN
|
2128 |
|
|
ea_data_OP1 <= '1';
|
2129 |
|
|
ELSE
|
2130 |
|
|
dest_hbits <= '1';
|
2131 |
|
|
source_lowbits <='1';
|
2132 |
|
|
IF opcode(3)='1' THEN
|
2133 |
|
|
source_areg <= '1';
|
2134 |
|
|
END IF;
|
2135 |
|
|
END IF;
|
2136 |
|
|
END IF;
|
2137 |
|
|
END IF;
|
2138 |
|
|
|
2139 |
|
|
-- 1001, 1101 -----------------------------------------------------------------------
|
2140 |
|
|
WHEN "1001"|"1101" => --sub, add
|
2141 |
|
|
set_exec_ADD <= '1';
|
2142 |
|
|
IF decodeOPC='1' THEN
|
2143 |
|
|
ea_build <= '1';
|
2144 |
|
|
END IF;
|
2145 |
|
|
IF opcode(8 downto 6)="011" THEN --adda.w, suba.w
|
2146 |
|
|
datatype <= "01"; --Word
|
2147 |
|
|
END IF;
|
2148 |
|
|
IF execOPC='1' THEN
|
2149 |
|
|
IF endOPC='1' THEN
|
2150 |
|
|
Regwrena <= '1';
|
2151 |
|
|
END IF;
|
2152 |
|
|
IF opcode(14)='0' THEN
|
2153 |
|
|
setaddsub <= '0';
|
2154 |
|
|
END IF;
|
2155 |
|
|
END IF;
|
2156 |
|
|
IF opcode(8)='1' AND opcode(5 downto 4)="00" AND opcode(7 downto 6)/="11" THEN --addx, subx
|
2157 |
|
|
use_XZFlag <= '1';
|
2158 |
|
|
IF opcode(3)='1' THEN
|
2159 |
|
|
write_back <= '1';
|
2160 |
|
|
IF decodeOPC='1' THEN
|
2161 |
|
|
set_direct_data <= '1';
|
2162 |
|
|
setstate <= "10";
|
2163 |
|
|
set_mem_addsub <= '1';
|
2164 |
|
|
presub <= '1';
|
2165 |
|
|
microstep <='1';
|
2166 |
|
|
micronext <="00110000";
|
2167 |
|
|
END IF;
|
2168 |
|
|
END IF;
|
2169 |
|
|
IF execOPC='1' THEN
|
2170 |
|
|
ea_data_OP1 <= '1';
|
2171 |
|
|
dest_hbits <= '1';
|
2172 |
|
|
source_lowbits <='1';
|
2173 |
|
|
END IF;
|
2174 |
|
|
ELSE --sub, add
|
2175 |
|
|
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN
|
2176 |
|
|
write_back <= '1';
|
2177 |
|
|
END IF;
|
2178 |
|
|
IF execOPC='1' THEN
|
2179 |
|
|
IF opcode(7 downto 6)="11" THEN --adda, suba
|
2180 |
|
|
no_Flags <= '1';
|
2181 |
|
|
dest_areg <='1';
|
2182 |
|
|
dest_hbits <= '1';
|
2183 |
|
|
source_lowbits <='1';
|
2184 |
|
|
IF opcode(3)='1' THEN
|
2185 |
|
|
source_areg <= '1';
|
2186 |
|
|
END IF;
|
2187 |
|
|
ELSE
|
2188 |
|
|
IF opcode(8)='1' THEN
|
2189 |
|
|
ea_data_OP1 <= '1';
|
2190 |
|
|
ELSE
|
2191 |
|
|
dest_hbits <= '1';
|
2192 |
|
|
source_lowbits <='1';
|
2193 |
|
|
IF opcode(3)='1' THEN
|
2194 |
|
|
source_areg <= '1';
|
2195 |
|
|
END IF;
|
2196 |
|
|
END IF;
|
2197 |
|
|
END IF;
|
2198 |
|
|
END IF;
|
2199 |
|
|
END IF;
|
2200 |
|
|
|
2201 |
|
|
-- 1010 ----------------------------------------------------------------------------
|
2202 |
|
|
WHEN "1010" => --Trap 1010
|
2203 |
|
|
trap_1010 <= '1';
|
2204 |
|
|
trap <= '1';
|
2205 |
|
|
-- 1011 ----------------------------------------------------------------------------
|
2206 |
|
|
WHEN "1011" => --eor, cmp
|
2207 |
|
|
IF decodeOPC='1' THEN
|
2208 |
|
|
ea_build <= '1';
|
2209 |
|
|
END IF;
|
2210 |
|
|
IF opcode(8 downto 6)="011" THEN --cmpa.w
|
2211 |
|
|
datatype <= "01"; --Word
|
2212 |
|
|
set_exec_CPMAW <= '1';
|
2213 |
|
|
END IF;
|
2214 |
|
|
IF opcode(8)='1' AND opcode(5 downto 3)="001" AND opcode(7 downto 6)/="11" THEN --cmpm
|
2215 |
|
|
set_exec_CMP <= '1';
|
2216 |
|
|
IF decodeOPC='1' THEN
|
2217 |
|
|
set_direct_data <= '1';
|
2218 |
|
|
setstate <= "10";
|
2219 |
|
|
set_mem_rega <= '1';
|
2220 |
|
|
postadd <= '1';
|
2221 |
|
|
microstep <='1';
|
2222 |
|
|
micronext <="00110010";
|
2223 |
|
|
END IF;
|
2224 |
|
|
IF execOPC='1' THEN
|
2225 |
|
|
ea_data_OP1 <= '1';
|
2226 |
|
|
setaddsub <= '0';
|
2227 |
|
|
END IF;
|
2228 |
|
|
ELSE --sub, add
|
2229 |
|
|
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
|
2230 |
|
|
set_exec_EOR <= '1';
|
2231 |
|
|
write_back <= '1';
|
2232 |
|
|
ELSE --cmp
|
2233 |
|
|
set_exec_CMP <= '1';
|
2234 |
|
|
END IF;
|
2235 |
|
|
|
2236 |
|
|
IF execOPC='1' THEN
|
2237 |
|
|
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
|
2238 |
|
|
ea_data_OP1 <= '1';
|
2239 |
|
|
IF endOPC='1' THEN
|
2240 |
|
|
Regwrena <= '1';
|
2241 |
|
|
END IF;
|
2242 |
|
|
ELSE --cmp
|
2243 |
|
|
source_lowbits <='1';
|
2244 |
|
|
IF opcode(3)='1' THEN
|
2245 |
|
|
source_areg <= '1';
|
2246 |
|
|
END IF;
|
2247 |
|
|
IF opcode(7 downto 6)="11" THEN --cmpa
|
2248 |
|
|
dest_areg <='1';
|
2249 |
|
|
END IF;
|
2250 |
|
|
dest_hbits <= '1';
|
2251 |
|
|
setaddsub <= '0';
|
2252 |
|
|
END IF;
|
2253 |
|
|
END IF;
|
2254 |
|
|
END IF;
|
2255 |
|
|
|
2256 |
|
|
-- 1100 ----------------------------------------------------------------------------
|
2257 |
|
|
WHEN "1100" => --and, exg
|
2258 |
|
|
IF opcode(7 downto 6)="11" THEN --mulu, muls
|
2259 |
|
|
IF opcode(5 downto 4)="00" THEN --Dn, An
|
2260 |
|
|
regdirectsource <= '1';
|
2261 |
|
|
END IF;
|
2262 |
|
|
IF (prefix='0' AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
|
2263 |
|
|
set_exec_MULU <= '1';
|
2264 |
|
|
setstate <="01";
|
2265 |
|
|
microstep <='1';
|
2266 |
|
|
micronext <="10000000";
|
2267 |
|
|
END IF;
|
2268 |
|
|
IF decodeOPC='1' THEN
|
2269 |
|
|
ea_build <= '1';
|
2270 |
|
|
END IF;
|
2271 |
|
|
IF execOPC='1' THEN
|
2272 |
|
|
regwrena <= '1';
|
2273 |
|
|
END IF;
|
2274 |
|
|
IF (prefix='1' AND nextpass='1') OR execOPC='1' THEN
|
2275 |
|
|
dest_hbits <= '1';
|
2276 |
|
|
source_lowbits <='1';
|
2277 |
|
|
ELSE
|
2278 |
|
|
datatype <= "01";
|
2279 |
|
|
END IF;
|
2280 |
|
|
|
2281 |
|
|
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --exg, abcd
|
2282 |
|
|
IF opcode(7 downto 6)="00" THEN --abcd
|
2283 |
|
|
use_XZFlag <= '1';
|
2284 |
|
|
-- datatype <= "00"; --ist schon default
|
2285 |
|
|
set_exec_ADD <= '1';
|
2286 |
|
|
set_exec_ABCD <= '1';
|
2287 |
|
|
IF opcode(3)='1' THEN
|
2288 |
|
|
write_back <= '1';
|
2289 |
|
|
IF decodeOPC='1' THEN
|
2290 |
|
|
set_direct_data <= '1';
|
2291 |
|
|
setstate <= "10";
|
2292 |
|
|
set_mem_addsub <= '1';
|
2293 |
|
|
presub <= '1';
|
2294 |
|
|
microstep <='1';
|
2295 |
|
|
micronext <="00110000";
|
2296 |
|
|
END IF;
|
2297 |
|
|
END IF;
|
2298 |
|
|
IF execOPC='1' THEN
|
2299 |
|
|
ea_data_OP1 <= '1';
|
2300 |
|
|
dest_hbits <= '1';
|
2301 |
|
|
source_lowbits <='1';
|
2302 |
|
|
IF endOPC='1' THEN
|
2303 |
|
|
Regwrena <= '1';
|
2304 |
|
|
END IF;
|
2305 |
|
|
END IF;
|
2306 |
|
|
ELSE --exg
|
2307 |
|
|
datatype <= "10";
|
2308 |
|
|
regwrena <= '1';
|
2309 |
|
|
IF opcode(6)='1' AND opcode(3)='1' THEN
|
2310 |
|
|
dest_areg <= '1';
|
2311 |
|
|
source_areg <= '1';
|
2312 |
|
|
END IF;
|
2313 |
|
|
IF decodeOPC='1' THEN
|
2314 |
|
|
set_mem_rega <= '1';
|
2315 |
|
|
exec_exg <= '1';
|
2316 |
|
|
ELSE
|
2317 |
|
|
save_memaddr <= '1';
|
2318 |
|
|
dest_hbits <= '1';
|
2319 |
|
|
END IF;
|
2320 |
|
|
END IF;
|
2321 |
|
|
ELSE --and
|
2322 |
|
|
set_exec_AND <= '1';
|
2323 |
|
|
IF opcode(8)='1' THEN
|
2324 |
|
|
write_back <= '1';
|
2325 |
|
|
END IF;
|
2326 |
|
|
IF decodeOPC='1' THEN
|
2327 |
|
|
ea_build <= '1';
|
2328 |
|
|
END IF;
|
2329 |
|
|
|
2330 |
|
|
IF execOPC='1' THEN
|
2331 |
|
|
IF endOPC='1' THEN
|
2332 |
|
|
Regwrena <= '1';
|
2333 |
|
|
END IF;
|
2334 |
|
|
IF opcode(8)='1' THEN
|
2335 |
|
|
ea_data_OP1 <= '1';
|
2336 |
|
|
ELSE
|
2337 |
|
|
dest_hbits <= '1';
|
2338 |
|
|
source_lowbits <='1';
|
2339 |
|
|
IF opcode(3)='1' THEN
|
2340 |
|
|
source_areg <= '1';
|
2341 |
|
|
END IF;
|
2342 |
|
|
END IF;
|
2343 |
|
|
END IF;
|
2344 |
|
|
END IF;
|
2345 |
|
|
|
2346 |
|
|
-- 1110 ----------------------------------------------------------------------------
|
2347 |
|
|
WHEN "1110" => --rotation
|
2348 |
|
|
set_exec_ROT <= '1';
|
2349 |
|
|
IF opcode(7 downto 6)="11" THEN
|
2350 |
|
|
datatype <= "01";
|
2351 |
|
|
rot_bits <= opcode(10 downto 9);
|
2352 |
|
|
ea_data_OP1 <= '1';
|
2353 |
|
|
write_back <= '1';
|
2354 |
|
|
ELSE
|
2355 |
|
|
rot_bits <= opcode(4 downto 3);
|
2356 |
|
|
data_is_source <= '1';
|
2357 |
|
|
END IF;
|
2358 |
|
|
|
2359 |
|
|
IF decodeOPC='1' THEN
|
2360 |
|
|
IF opcode(7 downto 6)="11" THEN
|
2361 |
|
|
ea_build <= '1';
|
2362 |
|
|
ELSE
|
2363 |
|
|
IF opcode(5)='1' THEN
|
2364 |
|
|
IF OP2out(5 downto 0)/="000000" THEN
|
2365 |
|
|
set_rot_cnt <= OP2out(5 downto 0);
|
2366 |
|
|
-- ELSE
|
2367 |
|
|
-- set_no_Flags <='1';
|
2368 |
|
|
END IF;
|
2369 |
|
|
ELSE
|
2370 |
|
|
set_rot_cnt(2 downto 0) <= opcode(11 downto 9);
|
2371 |
|
|
IF opcode(11 downto 9)="000" THEN
|
2372 |
|
|
set_rot_cnt(3) <='1';
|
2373 |
|
|
ELSE
|
2374 |
|
|
set_rot_cnt(3) <='0';
|
2375 |
|
|
END IF;
|
2376 |
|
|
END IF;
|
2377 |
|
|
END IF;
|
2378 |
|
|
END IF;
|
2379 |
|
|
IF opcode(7 downto 6)/="11" THEN
|
2380 |
|
|
IF opcode(5)='1' AND OP2out(5 downto 0)="000000" THEN --Macht Fehler wenn mit sich selbst geschoben wird
|
2381 |
|
|
-- no_Flags <= '1';
|
2382 |
|
|
rot_nop <= '1';
|
2383 |
|
|
ELSIF execOPC='1' THEN
|
2384 |
|
|
Regwrena <= '1';
|
2385 |
|
|
set_rot_cnt <= rot_cnt-1;
|
2386 |
|
|
END IF;
|
2387 |
|
|
END IF;
|
2388 |
|
|
|
2389 |
|
|
-- ----------------------------------------------------------------------------
|
2390 |
|
|
WHEN OTHERS =>
|
2391 |
|
|
trap_1111 <= '1';
|
2392 |
|
|
trap <= '1';
|
2393 |
|
|
|
2394 |
|
|
END CASE;
|
2395 |
|
|
|
2396 |
|
|
-- END PROCESS;
|
2397 |
|
|
|
2398 |
|
|
-----------------------------------------------------------------------------
|
2399 |
|
|
-- execute microcode
|
2400 |
|
|
-----------------------------------------------------------------------------
|
2401 |
|
|
--PROCESS (microaddr)
|
2402 |
|
|
-- BEGIN
|
2403 |
|
|
IF Z_error='1' THEN -- divu by zero
|
2404 |
|
|
trap <= '1'; --wichtig für USP
|
2405 |
|
|
IF trapd='0' THEN
|
2406 |
|
|
writePC <= '1';
|
2407 |
|
|
microset <= '1';
|
2408 |
|
|
END IF;
|
2409 |
|
|
END IF;
|
2410 |
|
|
|
2411 |
|
|
IF trap='1' AND trapd='0' THEN
|
2412 |
|
|
microstep <= '1';
|
2413 |
|
|
micronext <= "01010000";
|
2414 |
|
|
presub <= '1';
|
2415 |
|
|
setstackaddr <='1';
|
2416 |
|
|
set_mem_addsub <= '1';
|
2417 |
|
|
setstate <= "11";
|
2418 |
|
|
datatype <= "10";
|
2419 |
|
|
END IF;
|
2420 |
|
|
|
2421 |
|
|
IF interrupt='1' THEN
|
2422 |
|
|
microstep <= '1';
|
2423 |
|
|
micronext <= "01000100";
|
2424 |
|
|
setstate <= "10";
|
2425 |
|
|
-- datatype <= "01"; --wirkt sich auf Flags aus
|
2426 |
|
|
END IF;
|
2427 |
|
|
|
2428 |
|
|
|
2429 |
|
|
IF reset='0' THEN
|
2430 |
|
|
microaddr <= "01100000"; --init
|
2431 |
|
|
prefix <= '1';
|
2432 |
|
|
ELSIF rising_edge(clk) THEN
|
2433 |
|
|
IF clkena='1' THEN
|
2434 |
|
|
trapd <= trap;
|
2435 |
|
|
prefix <= (prefix AND ea_build) OR (microstep AND NOT fetchOPC);
|
2436 |
|
|
IF prefix='1' AND ea_build='0' AND microset='0' THEN
|
2437 |
|
|
microaddr <= microaddr + micronext;
|
2438 |
|
|
ELSE
|
2439 |
|
|
microaddr <= micronext;
|
2440 |
|
|
END IF;
|
2441 |
|
|
END IF;
|
2442 |
|
|
END IF;
|
2443 |
|
|
IF prefix='1' THEN
|
2444 |
|
|
CASE microaddr IS
|
2445 |
|
|
WHEN "00000001" => -- nop
|
2446 |
|
|
|
2447 |
|
|
WHEN "00000010" => -- (nnnn).w/l=>
|
2448 |
|
|
get_ea_now <='1';
|
2449 |
|
|
setnextpass <= '1';
|
2450 |
|
|
setaddrlong <= '1';
|
2451 |
|
|
|
2452 |
|
|
WHEN "00000011" => -- =>(nnnn).w/l
|
2453 |
|
|
setstate <= "11";
|
2454 |
|
|
setaddrlong <= '1';
|
2455 |
|
|
microstep <='1';
|
2456 |
|
|
|
2457 |
|
|
WHEN "00000110" => -- d(An)=>, --d(PC)=>
|
2458 |
|
|
microstep <='1';
|
2459 |
|
|
setstate <= "01";
|
2460 |
|
|
WHEN "00000111" => -- d(An)=>, --d(PC)=>
|
2461 |
|
|
get_ea_now <='1';
|
2462 |
|
|
setdisp <= '1'; --word
|
2463 |
|
|
setnextpass <= '1';
|
2464 |
|
|
|
2465 |
|
|
WHEN "00001000" => -- d(An,Xn)=>, --d(PC,Xn)=>
|
2466 |
|
|
microstep <='1';
|
2467 |
|
|
setstate <= "01";
|
2468 |
|
|
WHEN "00001001" => -- d(An,Xn)=>, --d(PC,Xn)=>
|
2469 |
|
|
setdisp <= '1'; --byte
|
2470 |
|
|
setdispbyte <= '1';
|
2471 |
|
|
microstep <='1';
|
2472 |
|
|
setstate <= "01";
|
2473 |
|
|
setbriefext <= '1';
|
2474 |
|
|
WHEN "00001010" =>
|
2475 |
|
|
get_ea_now <='1';
|
2476 |
|
|
setdisp <= '1'; --brief
|
2477 |
|
|
setdispbrief <= '1';
|
2478 |
|
|
setnextpass <= '1';
|
2479 |
|
|
|
2480 |
|
|
WHEN "00001011" => -- =>d(An)
|
2481 |
|
|
microstep <='1';
|
2482 |
|
|
setstate <= "01";
|
2483 |
|
|
WHEN "00001100" => -- =>d(An)
|
2484 |
|
|
setstate <= "11";
|
2485 |
|
|
setdisp <= '1'; --word
|
2486 |
|
|
microstep <='1';
|
2487 |
|
|
WHEN "00001101" =>
|
2488 |
|
|
|
2489 |
|
|
WHEN "00001110" => -- =>d(An,Xn)
|
2490 |
|
|
microstep <='1';
|
2491 |
|
|
setstate <= "01";
|
2492 |
|
|
WHEN "00001111" => -- =>d(An,Xn)
|
2493 |
|
|
setdisp <= '1'; --byte
|
2494 |
|
|
setdispbyte <= '1';
|
2495 |
|
|
microstep <='1';
|
2496 |
|
|
setstate <= "01";
|
2497 |
|
|
setbriefext <= '1';
|
2498 |
|
|
WHEN "00010000" =>
|
2499 |
|
|
setstate <= "11";
|
2500 |
|
|
setdisp <= '1'; --brief
|
2501 |
|
|
setdispbrief <= '1';
|
2502 |
|
|
microstep <='1';
|
2503 |
|
|
WHEN "00010001" =>
|
2504 |
|
|
|
2505 |
|
|
WHEN "00010010" => --bra
|
2506 |
|
|
IF condition='1' THEN
|
2507 |
|
|
TG68_PC_br8 <= '1'; --pc+0000
|
2508 |
|
|
microstep <='1';
|
2509 |
|
|
setstate <= "01";
|
2510 |
|
|
END IF;
|
2511 |
|
|
WHEN "00010011" => --bra
|
2512 |
|
|
TG68_PC_brw <= '1';
|
2513 |
|
|
|
2514 |
|
|
WHEN "00011000" => --bsr
|
2515 |
|
|
set_TG68_PC_dec <= '1'; --in 2 Takten -2
|
2516 |
|
|
microstep <='1';
|
2517 |
|
|
setstate <= "01";
|
2518 |
|
|
WHEN "00011001" => --bsr
|
2519 |
|
|
IF TG68_PC_dec(0)='1' THEN
|
2520 |
|
|
TG68_PC_brw <= '1';
|
2521 |
|
|
ELSE
|
2522 |
|
|
TG68_PC_br8 <= '1';
|
2523 |
|
|
END IF;
|
2524 |
|
|
writePC <= '1';
|
2525 |
|
|
setstate <= "11";
|
2526 |
|
|
microstep <='1';
|
2527 |
|
|
WHEN "00011010" => --bsr
|
2528 |
|
|
|
2529 |
|
|
WHEN "00011110" => --dbcc
|
2530 |
|
|
TG68_PC_nop <= '1';
|
2531 |
|
|
microstep <='1';
|
2532 |
|
|
setstate <= "01";
|
2533 |
|
|
WHEN "00011111" => --dbcc
|
2534 |
|
|
TG68_PC_brw <= '1';
|
2535 |
|
|
|
2536 |
|
|
WHEN "00100010" => --movem
|
2537 |
|
|
set_movem_busy <='1';
|
2538 |
|
|
setstate <= "10";
|
2539 |
|
|
|
2540 |
|
|
WHEN "00101000" => --andi
|
2541 |
|
|
IF opcode(5 downto 4)/="00" THEN
|
2542 |
|
|
ea_build <= '1';
|
2543 |
|
|
setnextpass <= '1';
|
2544 |
|
|
END IF;
|
2545 |
|
|
|
2546 |
|
|
WHEN "00101100" => --jsr
|
2547 |
|
|
presub <= '1';
|
2548 |
|
|
setstackaddr <='1';
|
2549 |
|
|
set_mem_addsub <= '1';
|
2550 |
|
|
setstate <= "11";
|
2551 |
|
|
|
2552 |
|
|
WHEN "00110000" => -- op -(Ax),-(Ay)
|
2553 |
|
|
presub <= '1';
|
2554 |
|
|
dest_hbits <= '1';
|
2555 |
|
|
dest_areg <= '1';
|
2556 |
|
|
set_mem_addsub <= '1';
|
2557 |
|
|
setstate <= "10";
|
2558 |
|
|
|
2559 |
|
|
WHEN "00110010" => -- cmpm (Ay)+,(Ax)+
|
2560 |
|
|
postadd <= '1';
|
2561 |
|
|
dest_hbits <= '1';
|
2562 |
|
|
dest_areg <= '1';
|
2563 |
|
|
set_mem_rega <= '1';
|
2564 |
|
|
setstate <= "10";
|
2565 |
|
|
|
2566 |
|
|
WHEN "01000000" => -- link
|
2567 |
|
|
setstate <="11";
|
2568 |
|
|
save_memaddr <= '1';
|
2569 |
|
|
regwrena <= '1';
|
2570 |
|
|
|
2571 |
|
|
WHEN "01000100" => -- interrupt
|
2572 |
|
|
microstep <= '1';
|
2573 |
|
|
presub <= '1';
|
2574 |
|
|
setstackaddr <='1';
|
2575 |
|
|
set_mem_addsub <= '1';
|
2576 |
|
|
setstate <= "11";
|
2577 |
|
|
datatype <= "10";
|
2578 |
|
|
WHEN "01000101" => -- interrupt
|
2579 |
|
|
microstep <= '1';
|
2580 |
|
|
presub <= '1';
|
2581 |
|
|
setstackaddr <='1';
|
2582 |
|
|
set_mem_addsub <= '1';
|
2583 |
|
|
setstate <= "11";
|
2584 |
|
|
datatype <= "01";
|
2585 |
|
|
writeSR <= '1';
|
2586 |
|
|
WHEN "01000110" => -- interrupt
|
2587 |
|
|
set_vectoraddr <= '1';
|
2588 |
|
|
datatype <= "10";
|
2589 |
|
|
set_directPC <= '1';
|
2590 |
|
|
microstep <='1';
|
2591 |
|
|
|
2592 |
|
|
setstate <= "10";
|
2593 |
|
|
WHEN "01000111" => -- interrupt
|
2594 |
|
|
datatype <= "10";
|
2595 |
|
|
|
2596 |
|
|
WHEN "01001000" => -- RTE
|
2597 |
|
|
datatype <= "10";
|
2598 |
|
|
setstate <= "10";
|
2599 |
|
|
postadd <= '1';
|
2600 |
|
|
setstackaddr <= '1';
|
2601 |
|
|
set_mem_rega <= '1';
|
2602 |
|
|
set_directPC <= '1';
|
2603 |
|
|
microstep <='1';
|
2604 |
|
|
|
2605 |
|
|
WHEN "01010000" => -- TRAP
|
2606 |
|
|
microstep <= '1';
|
2607 |
|
|
presub <= '1';
|
2608 |
|
|
setstackaddr <='1';
|
2609 |
|
|
set_mem_addsub <= '1';
|
2610 |
|
|
setstate <= "11";
|
2611 |
|
|
datatype <= "01";
|
2612 |
|
|
writeSR <= '1';
|
2613 |
|
|
WHEN "01010001" => -- TRAP
|
2614 |
|
|
set_vectoraddr <= '1';
|
2615 |
|
|
datatype <= "10";
|
2616 |
|
|
set_directPC <= '1';
|
2617 |
|
|
microstep <='1';
|
2618 |
|
|
-- longreaddirect <= '1';
|
2619 |
|
|
setstate <= "10";
|
2620 |
|
|
WHEN "01010010" => -- TRAP
|
2621 |
|
|
datatype <= "10";
|
2622 |
|
|
|
2623 |
|
|
|
2624 |
|
|
|
2625 |
|
|
|
2626 |
|
|
WHEN "01100000" => -- init SP
|
2627 |
|
|
microstep <='1';
|
2628 |
|
|
longreaddirect <= '1';
|
2629 |
|
|
WHEN "01100001" => -- init PC
|
2630 |
|
|
get_ea_now <='1'; --\
|
2631 |
|
|
ea_only <= '1'; --- OP1in <= memaddr_in
|
2632 |
|
|
setaddrlong <= '1'; -- memaddr_in <= data_read
|
2633 |
|
|
regwrena <= '1';
|
2634 |
|
|
setstackaddr <='1'; -- dest_addr <= SP
|
2635 |
|
|
set_directPC <= '1';
|
2636 |
|
|
microstep <='1';
|
2637 |
|
|
longreaddirect <= '1';
|
2638 |
|
|
-- WHEN "01100010" => -- wr SP
|
2639 |
|
|
|
2640 |
|
|
|
2641 |
|
|
|
2642 |
|
|
|
2643 |
|
|
WHEN "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|
|
2644 |
|
|
"10000111"|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101" => -- mulu
|
2645 |
|
|
microstep <='1';
|
2646 |
|
|
set_exec_MULU <= '1';
|
2647 |
|
|
setstate <="01";
|
2648 |
|
|
WHEN "10001110" => -- mulu
|
2649 |
|
|
set_exec_MULU <= '1';
|
2650 |
|
|
|
2651 |
|
|
|
2652 |
|
|
WHEN "10100000" => -- divu
|
2653 |
|
|
IF OP2out(15 downto 0)=x"0000" THEN --div zero
|
2654 |
|
|
set_Z_error <= '1';
|
2655 |
|
|
microset <= '1';
|
2656 |
|
|
ELSE
|
2657 |
|
|
set_exec_DIVU <= '1';
|
2658 |
|
|
END IF;
|
2659 |
|
|
setstate <="01";
|
2660 |
|
|
microstep <='1';
|
2661 |
|
|
WHEN "10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100110"|"10100111"|
|
2662 |
|
|
"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101" => -- divu
|
2663 |
|
|
microstep <='1';
|
2664 |
|
|
set_exec_DIVU <= '1';
|
2665 |
|
|
setstate <="01";
|
2666 |
|
|
WHEN "10101110" => -- divu
|
2667 |
|
|
set_exec_DIVU <= '1';
|
2668 |
|
|
|
2669 |
|
|
|
2670 |
|
|
WHEN OTHERS =>
|
2671 |
|
|
END CASE;
|
2672 |
|
|
END IF;
|
2673 |
|
|
END PROCESS;
|
2674 |
|
|
|
2675 |
|
|
-----------------------------------------------------------------------------
|
2676 |
|
|
-- Conditions
|
2677 |
|
|
-----------------------------------------------------------------------------
|
2678 |
|
|
PROCESS (opcode, Flags)
|
2679 |
|
|
BEGIN
|
2680 |
|
|
CASE opcode(11 downto 8) IS
|
2681 |
|
|
WHEN X"0" => condition <= '1';
|
2682 |
|
|
WHEN X"1" => condition <= '0';
|
2683 |
|
|
WHEN X"2" => condition <= NOT Flags(0) AND NOT Flags(2);
|
2684 |
|
|
WHEN X"3" => condition <= Flags(0) OR Flags(2);
|
2685 |
|
|
WHEN X"4" => condition <= NOT Flags(0);
|
2686 |
|
|
WHEN X"5" => condition <= Flags(0);
|
2687 |
|
|
WHEN X"6" => condition <= NOT Flags(2);
|
2688 |
|
|
WHEN X"7" => condition <= Flags(2);
|
2689 |
|
|
WHEN X"8" => condition <= NOT Flags(1);
|
2690 |
|
|
WHEN X"9" => condition <= Flags(1);
|
2691 |
|
|
WHEN X"a" => condition <= NOT Flags(3);
|
2692 |
|
|
WHEN X"b" => condition <= Flags(3);
|
2693 |
|
|
WHEN X"c" => condition <= (Flags(3) AND Flags(1)) OR (NOT Flags(3) AND NOT Flags(1));
|
2694 |
|
|
WHEN X"d" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1));
|
2695 |
|
|
WHEN X"e" => condition <= (Flags(3) AND Flags(1) AND NOT Flags(2)) OR (NOT Flags(3) AND NOT Flags(1) AND NOT Flags(2));
|
2696 |
|
|
WHEN X"f" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)) OR Flags(2);
|
2697 |
|
|
END CASE;
|
2698 |
|
|
END PROCESS;
|
2699 |
|
|
|
2700 |
|
|
-----------------------------------------------------------------------------
|
2701 |
|
|
-- Bits
|
2702 |
|
|
-----------------------------------------------------------------------------
|
2703 |
|
|
PROCESS (opcode, OP1out, OP2out, one_bit_in, one_bit_out, bit_Number, bit_number_reg)
|
2704 |
|
|
BEGIN
|
2705 |
|
|
CASE opcode(7 downto 6) IS
|
2706 |
|
|
WHEN "00" => --btst
|
2707 |
|
|
one_bit_out <= one_bit_in;
|
2708 |
|
|
WHEN "01" => --bchg
|
2709 |
|
|
one_bit_out <= NOT one_bit_in;
|
2710 |
|
|
WHEN "10" => --bclr
|
2711 |
|
|
one_bit_out <= '0';
|
2712 |
|
|
WHEN "11" => --bset
|
2713 |
|
|
one_bit_out <= '1';
|
2714 |
|
|
END CASE;
|
2715 |
|
|
|
2716 |
|
|
IF opcode(8)='0' THEN
|
2717 |
|
|
IF opcode(5 downto 4)="00" THEN
|
2718 |
|
|
bit_number <= bit_number_reg(4 downto 0);
|
2719 |
|
|
ELSE
|
2720 |
|
|
bit_number <= "00"&bit_number_reg(2 downto 0);
|
2721 |
|
|
END IF;
|
2722 |
|
|
ELSE
|
2723 |
|
|
IF opcode(5 downto 4)="00" THEN
|
2724 |
|
|
bit_number <= OP2out(4 downto 0);
|
2725 |
|
|
ELSE
|
2726 |
|
|
bit_number <= "00"&OP2out(2 downto 0);
|
2727 |
|
|
END IF;
|
2728 |
|
|
END IF;
|
2729 |
|
|
|
2730 |
|
|
bits_out <= OP1out;
|
2731 |
|
|
CASE bit_Number IS
|
2732 |
|
|
WHEN "00000" => one_bit_in <= OP1out(0);
|
2733 |
|
|
bits_out(0) <= one_bit_out;
|
2734 |
|
|
WHEN "00001" => one_bit_in <= OP1out(1);
|
2735 |
|
|
bits_out(1) <= one_bit_out;
|
2736 |
|
|
WHEN "00010" => one_bit_in <= OP1out(2);
|
2737 |
|
|
bits_out(2) <= one_bit_out;
|
2738 |
|
|
WHEN "00011" => one_bit_in <= OP1out(3);
|
2739 |
|
|
bits_out(3) <= one_bit_out;
|
2740 |
|
|
WHEN "00100" => one_bit_in <= OP1out(4);
|
2741 |
|
|
bits_out(4) <= one_bit_out;
|
2742 |
|
|
WHEN "00101" => one_bit_in <= OP1out(5);
|
2743 |
|
|
bits_out(5) <= one_bit_out;
|
2744 |
|
|
WHEN "00110" => one_bit_in <= OP1out(6);
|
2745 |
|
|
bits_out(6) <= one_bit_out;
|
2746 |
|
|
WHEN "00111" => one_bit_in <= OP1out(7);
|
2747 |
|
|
bits_out(7) <= one_bit_out;
|
2748 |
|
|
WHEN "01000" => one_bit_in <= OP1out(8);
|
2749 |
|
|
bits_out(8) <= one_bit_out;
|
2750 |
|
|
WHEN "01001" => one_bit_in <= OP1out(9);
|
2751 |
|
|
bits_out(9) <= one_bit_out;
|
2752 |
|
|
WHEN "01010" => one_bit_in <= OP1out(10);
|
2753 |
|
|
bits_out(10) <= one_bit_out;
|
2754 |
|
|
WHEN "01011" => one_bit_in <= OP1out(11);
|
2755 |
|
|
bits_out(11) <= one_bit_out;
|
2756 |
|
|
WHEN "01100" => one_bit_in <= OP1out(12);
|
2757 |
|
|
bits_out(12) <= one_bit_out;
|
2758 |
|
|
WHEN "01101" => one_bit_in <= OP1out(13);
|
2759 |
|
|
bits_out(13) <= one_bit_out;
|
2760 |
|
|
WHEN "01110" => one_bit_in <= OP1out(14);
|
2761 |
|
|
bits_out(14) <= one_bit_out;
|
2762 |
|
|
WHEN "01111" => one_bit_in <= OP1out(15);
|
2763 |
|
|
bits_out(15) <= one_bit_out;
|
2764 |
|
|
WHEN "10000" => one_bit_in <= OP1out(16);
|
2765 |
|
|
bits_out(16) <= one_bit_out;
|
2766 |
|
|
WHEN "10001" => one_bit_in <= OP1out(17);
|
2767 |
|
|
bits_out(17) <= one_bit_out;
|
2768 |
|
|
WHEN "10010" => one_bit_in <= OP1out(18);
|
2769 |
|
|
bits_out(18) <= one_bit_out;
|
2770 |
|
|
WHEN "10011" => one_bit_in <= OP1out(19);
|
2771 |
|
|
bits_out(19) <= one_bit_out;
|
2772 |
|
|
WHEN "10100" => one_bit_in <= OP1out(20);
|
2773 |
|
|
bits_out(20) <= one_bit_out;
|
2774 |
|
|
WHEN "10101" => one_bit_in <= OP1out(21);
|
2775 |
|
|
bits_out(21) <= one_bit_out;
|
2776 |
|
|
WHEN "10110" => one_bit_in <= OP1out(22);
|
2777 |
|
|
bits_out(22) <= one_bit_out;
|
2778 |
|
|
WHEN "10111" => one_bit_in <= OP1out(23);
|
2779 |
|
|
bits_out(23) <= one_bit_out;
|
2780 |
|
|
WHEN "11000" => one_bit_in <= OP1out(24);
|
2781 |
|
|
bits_out(24) <= one_bit_out;
|
2782 |
|
|
WHEN "11001" => one_bit_in <= OP1out(25);
|
2783 |
|
|
bits_out(25) <= one_bit_out;
|
2784 |
|
|
WHEN "11010" => one_bit_in <= OP1out(26);
|
2785 |
|
|
bits_out(26) <= one_bit_out;
|
2786 |
|
|
WHEN "11011" => one_bit_in <= OP1out(27);
|
2787 |
|
|
bits_out(27) <= one_bit_out;
|
2788 |
|
|
WHEN "11100" => one_bit_in <= OP1out(28);
|
2789 |
|
|
bits_out(28) <= one_bit_out;
|
2790 |
|
|
WHEN "11101" => one_bit_in <= OP1out(29);
|
2791 |
|
|
bits_out(29) <= one_bit_out;
|
2792 |
|
|
WHEN "11110" => one_bit_in <= OP1out(30);
|
2793 |
|
|
bits_out(30) <= one_bit_out;
|
2794 |
|
|
WHEN "11111" => one_bit_in <= OP1out(31);
|
2795 |
|
|
bits_out(31) <= one_bit_out;
|
2796 |
|
|
WHEN OTHERS =>
|
2797 |
|
|
END CASE;
|
2798 |
|
|
END PROCESS;
|
2799 |
|
|
|
2800 |
|
|
-----------------------------------------------------------------------------
|
2801 |
|
|
-- Rotation
|
2802 |
|
|
-----------------------------------------------------------------------------
|
2803 |
|
|
PROCESS (opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, rot_nop)
|
2804 |
|
|
BEGIN
|
2805 |
|
|
CASE opcode(7 downto 6) IS
|
2806 |
|
|
WHEN "00" => --Byte
|
2807 |
|
|
rot_rot <= OP1out(7);
|
2808 |
|
|
WHEN "01"|"11" => --Word
|
2809 |
|
|
rot_rot <= OP1out(15);
|
2810 |
|
|
WHEN "10" => --Long
|
2811 |
|
|
rot_rot <= OP1out(31);
|
2812 |
|
|
END CASE;
|
2813 |
|
|
|
2814 |
|
|
CASE rot_bits IS
|
2815 |
|
|
WHEN "00" => --ASL, ASR
|
2816 |
|
|
rot_lsb <= '0';
|
2817 |
|
|
rot_msb <= rot_rot;
|
2818 |
|
|
WHEN "01" => --LSL, LSR
|
2819 |
|
|
rot_lsb <= '0';
|
2820 |
|
|
rot_msb <= '0';
|
2821 |
|
|
WHEN "10" => --ROXL, ROXR
|
2822 |
|
|
rot_lsb <= Flags(4);
|
2823 |
|
|
rot_msb <= Flags(4);
|
2824 |
|
|
WHEN "11" => --ROL, ROR
|
2825 |
|
|
rot_lsb <= rot_rot;
|
2826 |
|
|
rot_msb <= OP1out(0);
|
2827 |
|
|
END CASE;
|
2828 |
|
|
|
2829 |
|
|
IF rot_nop='1' THEN
|
2830 |
|
|
rot_out <= OP1out;
|
2831 |
|
|
rot_XC <= Flags(0);
|
2832 |
|
|
ELSE
|
2833 |
|
|
IF opcode(8)='1' THEN --left
|
2834 |
|
|
rot_out <= OP1out(30 downto 0)&rot_lsb;
|
2835 |
|
|
rot_XC <= rot_rot;
|
2836 |
|
|
ELSE --right
|
2837 |
|
|
rot_XC <= OP1out(0);
|
2838 |
|
|
rot_out <= rot_msb&OP1out(31 downto 1);
|
2839 |
|
|
CASE opcode(7 downto 6) IS
|
2840 |
|
|
WHEN "00" => --Byte
|
2841 |
|
|
rot_out(7) <= rot_msb;
|
2842 |
|
|
WHEN "01"|"11" => --Word
|
2843 |
|
|
rot_out(15) <= rot_msb;
|
2844 |
|
|
WHEN OTHERS =>
|
2845 |
|
|
END CASE;
|
2846 |
|
|
END IF;
|
2847 |
|
|
END IF;
|
2848 |
|
|
END PROCESS;
|
2849 |
|
|
|
2850 |
|
|
-----------------------------------------------------------------------------
|
2851 |
|
|
-- MULU/MULS
|
2852 |
|
|
-----------------------------------------------------------------------------
|
2853 |
|
|
PROCESS (clk, opcode, OP2out, muls_msb, mulu_reg, OP1sign, sign2)
|
2854 |
|
|
BEGIN
|
2855 |
|
|
IF rising_edge(clk) THEN
|
2856 |
|
|
IF clkena='1' THEN
|
2857 |
|
|
IF decodeOPC='1' THEN
|
2858 |
|
|
IF opcode(8)='1' AND reg_QB(15)='1' THEN --MULS Neg faktor
|
2859 |
|
|
OP1sign <= '1';
|
2860 |
|
|
mulu_reg <= "0000000000000000"&(0-reg_QB(15 downto 0));
|
2861 |
|
|
ELSE
|
2862 |
|
|
OP1sign <= '0';
|
2863 |
|
|
mulu_reg <= "0000000000000000"®_QB(15 downto 0);
|
2864 |
|
|
END IF;
|
2865 |
|
|
ELSIF exec_MULU='1' THEN
|
2866 |
|
|
mulu_reg <= dummy_mulu;
|
2867 |
|
|
END IF;
|
2868 |
|
|
END IF;
|
2869 |
|
|
END IF;
|
2870 |
|
|
|
2871 |
|
|
IF (opcode(8)='1' AND OP2out(15)='1') OR OP1sign='1' THEN
|
2872 |
|
|
muls_msb <= mulu_reg(31);
|
2873 |
|
|
ELSE
|
2874 |
|
|
muls_msb <= '0';
|
2875 |
|
|
END IF;
|
2876 |
|
|
|
2877 |
|
|
IF opcode(8)='1' AND OP2out(15)='1' THEN
|
2878 |
|
|
sign2 <= '1';
|
2879 |
|
|
ELSE
|
2880 |
|
|
sign2 <= '0';
|
2881 |
|
|
END IF;
|
2882 |
|
|
|
2883 |
|
|
IF mulu_reg(0)='1' THEN
|
2884 |
|
|
IF OP1sign='1' THEN
|
2885 |
|
|
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))-(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
|
2886 |
|
|
ELSE
|
2887 |
|
|
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))+(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
|
2888 |
|
|
END IF;
|
2889 |
|
|
ELSE
|
2890 |
|
|
dummy_mulu <= muls_msb&mulu_reg(31 downto 1);
|
2891 |
|
|
END IF;
|
2892 |
|
|
END PROCESS;
|
2893 |
|
|
|
2894 |
|
|
-----------------------------------------------------------------------------
|
2895 |
|
|
-- DIVU
|
2896 |
|
|
-----------------------------------------------------------------------------
|
2897 |
|
|
PROCESS (clk, execOPC, opcode, OP1out, OP2out, div_reg, dummy_div_sub, div_quot, div_sign, dummy_div_over, dummy_div)
|
2898 |
|
|
BEGIN
|
2899 |
|
|
set_V_Flag <= '0';
|
2900 |
|
|
|
2901 |
|
|
IF rising_edge(clk) THEN
|
2902 |
|
|
IF clkena='1' THEN
|
2903 |
|
|
IF decodeOPC='1' THEN
|
2904 |
|
|
IF opcode(8)='1' AND reg_QB(31)='1' THEN -- Neg divisor
|
2905 |
|
|
div_sign <= '1';
|
2906 |
|
|
div_reg <= 0-reg_QB;
|
2907 |
|
|
ELSE
|
2908 |
|
|
div_sign <= '0';
|
2909 |
|
|
div_reg <= reg_QB;
|
2910 |
|
|
END IF;
|
2911 |
|
|
ELSIF exec_DIVU='1' THEN
|
2912 |
|
|
div_reg <= div_quot;
|
2913 |
|
|
END IF;
|
2914 |
|
|
END IF;
|
2915 |
|
|
END IF;
|
2916 |
|
|
|
2917 |
|
|
dummy_div_over <= ('0'&OP1out(31 downto 16))-('0'&OP2out(15 downto 0));
|
2918 |
|
|
|
2919 |
|
|
IF opcode(8)='1' AND OP2out(15) ='1' THEN
|
2920 |
|
|
dummy_div_sub <= (div_reg(31 downto 15))+('1'&OP2out(15 downto 0));
|
2921 |
|
|
ELSE
|
2922 |
|
|
dummy_div_sub <= (div_reg(31 downto 15))-('0'&OP2out(15 downto 0));
|
2923 |
|
|
END IF;
|
2924 |
|
|
|
2925 |
|
|
IF (dummy_div_sub(16))='1' THEN
|
2926 |
|
|
div_quot(31 downto 16) <= div_reg(30 downto 15);
|
2927 |
|
|
ELSE
|
2928 |
|
|
div_quot(31 downto 16) <= dummy_div_sub(15 downto 0);
|
2929 |
|
|
END IF;
|
2930 |
|
|
|
2931 |
|
|
div_quot(15 downto 0) <= div_reg(14 downto 0)&NOT dummy_div_sub(16);
|
2932 |
|
|
|
2933 |
|
|
IF execOPC='1' AND opcode(8)='1' AND (OP2out(15) XOR div_sign)='1' THEN
|
2934 |
|
|
dummy_div(15 downto 0) <= 0-div_quot(15 downto 0);
|
2935 |
|
|
ELSE
|
2936 |
|
|
dummy_div(15 downto 0) <= div_quot(15 downto 0);
|
2937 |
|
|
END IF;
|
2938 |
|
|
|
2939 |
|
|
IF div_sign='1' THEN
|
2940 |
|
|
dummy_div(31 downto 16) <= 0-div_quot(31 downto 16);
|
2941 |
|
|
ELSE
|
2942 |
|
|
dummy_div(31 downto 16) <= div_quot(31 downto 16);
|
2943 |
|
|
END IF;
|
2944 |
|
|
|
2945 |
|
|
IF (opcode(8)='1' AND (OP2out(15) XOR div_sign XOR dummy_div(15))='1' AND dummy_div(15 downto 0)/=X"0000") --Overflow DIVS
|
2946 |
|
|
OR (opcode(8)='0' AND dummy_div_over(16)='0') THEN --Overflow DIVU
|
2947 |
|
|
set_V_Flag <= '1';
|
2948 |
|
|
END IF;
|
2949 |
|
|
END PROCESS;
|
2950 |
|
|
|
2951 |
|
|
-----------------------------------------------------------------------------
|
2952 |
|
|
-- Movem
|
2953 |
|
|
-----------------------------------------------------------------------------
|
2954 |
|
|
PROCESS (reset, clk, movem_mask, movem_muxa ,movem_muxb, movem_muxc)
|
2955 |
|
|
BEGIN
|
2956 |
|
|
IF movem_mask(7 downto 0)="00000000" THEN
|
2957 |
|
|
movem_muxa <= movem_mask(15 downto 8);
|
2958 |
|
|
movem_regaddr(3) <= '1';
|
2959 |
|
|
ELSE
|
2960 |
|
|
movem_muxa <= movem_mask(7 downto 0);
|
2961 |
|
|
movem_regaddr(3) <= '0';
|
2962 |
|
|
END IF;
|
2963 |
|
|
IF movem_muxa(3 downto 0)="0000" THEN
|
2964 |
|
|
movem_muxb <= movem_muxa(7 downto 4);
|
2965 |
|
|
movem_regaddr(2) <= '1';
|
2966 |
|
|
ELSE
|
2967 |
|
|
movem_muxb <= movem_muxa(3 downto 0);
|
2968 |
|
|
movem_regaddr(2) <= '0';
|
2969 |
|
|
END IF;
|
2970 |
|
|
IF movem_muxb(1 downto 0)="00" THEN
|
2971 |
|
|
movem_muxc <= movem_muxb(3 downto 2);
|
2972 |
|
|
movem_regaddr(1) <= '1';
|
2973 |
|
|
ELSE
|
2974 |
|
|
movem_muxc <= movem_muxb(1 downto 0);
|
2975 |
|
|
movem_regaddr(1) <= '0';
|
2976 |
|
|
END IF;
|
2977 |
|
|
IF movem_muxc(0)='0' THEN
|
2978 |
|
|
movem_regaddr(0) <= '1';
|
2979 |
|
|
ELSE
|
2980 |
|
|
movem_regaddr(0) <= '0';
|
2981 |
|
|
END IF;
|
2982 |
|
|
|
2983 |
|
|
movem_bits <= ("0000"&movem_mask(0))+("0000"&movem_mask(1))+("0000"&movem_mask(2))+("0000"&movem_mask(3))+
|
2984 |
|
|
("0000"&movem_mask(4))+("0000"&movem_mask(5))+("0000"&movem_mask(6))+("0000"&movem_mask(7))+
|
2985 |
|
|
("0000"&movem_mask(8))+("0000"&movem_mask(9))+("0000"&movem_mask(10))+("0000"&movem_mask(11))+
|
2986 |
|
|
("0000"&movem_mask(12))+("0000"&movem_mask(13))+("0000"&movem_mask(14))+("0000"&movem_mask(15));
|
2987 |
|
|
|
2988 |
|
|
IF reset = '0' THEN
|
2989 |
|
|
movem_busy <= '0';
|
2990 |
|
|
movem_addr <= '0';
|
2991 |
|
|
ELSIF rising_edge(clk) THEN
|
2992 |
|
|
IF clkena_in='1' AND get_movem_mask='1' THEN
|
2993 |
|
|
movem_mask <= data_read(15 downto 0);
|
2994 |
|
|
END IF;
|
2995 |
|
|
IF clkena='1' THEN
|
2996 |
|
|
IF set_movem_busy='1' THEN
|
2997 |
|
|
IF movem_bits(3 downto 1) /= "000" OR opcode(10)='0' THEN
|
2998 |
|
|
movem_busy <= '1';
|
2999 |
|
|
END IF;
|
3000 |
|
|
movem_addr <= '1';
|
3001 |
|
|
END IF;
|
3002 |
|
|
IF movem_addr='1' THEN
|
3003 |
|
|
CASE movem_regaddr IS
|
3004 |
|
|
WHEN "0000" => movem_mask(0) <= '0';
|
3005 |
|
|
WHEN "0001" => movem_mask(1) <= '0';
|
3006 |
|
|
WHEN "0010" => movem_mask(2) <= '0';
|
3007 |
|
|
WHEN "0011" => movem_mask(3) <= '0';
|
3008 |
|
|
WHEN "0100" => movem_mask(4) <= '0';
|
3009 |
|
|
WHEN "0101" => movem_mask(5) <= '0';
|
3010 |
|
|
WHEN "0110" => movem_mask(6) <= '0';
|
3011 |
|
|
WHEN "0111" => movem_mask(7) <= '0';
|
3012 |
|
|
WHEN "1000" => movem_mask(8) <= '0';
|
3013 |
|
|
WHEN "1001" => movem_mask(9) <= '0';
|
3014 |
|
|
WHEN "1010" => movem_mask(10) <= '0';
|
3015 |
|
|
WHEN "1011" => movem_mask(11) <= '0';
|
3016 |
|
|
WHEN "1100" => movem_mask(12) <= '0';
|
3017 |
|
|
WHEN "1101" => movem_mask(13) <= '0';
|
3018 |
|
|
WHEN "1110" => movem_mask(14) <= '0';
|
3019 |
|
|
WHEN "1111" => movem_mask(15) <= '0';
|
3020 |
|
|
END CASE;
|
3021 |
|
|
IF opcode(10)='1' THEN
|
3022 |
|
|
IF movem_bits="00010" OR movem_bits="00001" OR movem_bits="00000" THEN
|
3023 |
|
|
movem_busy <= '0';
|
3024 |
|
|
END IF;
|
3025 |
|
|
END IF;
|
3026 |
|
|
IF movem_bits="00001" OR movem_bits="00000" THEN
|
3027 |
|
|
movem_busy <= '0';
|
3028 |
|
|
movem_addr <= '0';
|
3029 |
|
|
END IF;
|
3030 |
|
|
END IF;
|
3031 |
|
|
END IF;
|
3032 |
|
|
END IF;
|
3033 |
|
|
END PROCESS;
|
3034 |
|
|
END;
|