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tobiflex |
------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- --
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-- This is the TOP-Level for TG68_fast to generate 68K Bus signals --
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-- --
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-- Copyright (c) 2007 Tobias Gubener <tobiflex@opencores.org> --
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-- --
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-- This source file is free software: you can redistribute it and/or modify --
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-- it under the terms of the GNU Lesser General Public License as published --
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-- by the Free Software Foundation, either version 3 of the License, or --
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-- (at your option) any later version. --
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-- --
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-- This source file is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-- --
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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--
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-- Revision 1.0 2007/11/05
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-- Clean up code and first release
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--
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-- known bugs/todo:
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-- Add CHK INSTRUCTION
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-- Add MOVEP INSTRUCTION
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-- full decode ILLEGAL INSTRUCTIONS
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-- Add FDC Output
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-- add odd Address test
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-- add TRACE
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-- Movem with regmask==x0000
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity TG68 is
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port(
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clk : in std_logic;
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reset : in std_logic;
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clkena_in : in std_logic:='1';
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data_in : in std_logic_vector(15 downto 0);
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IPL : in std_logic_vector(2 downto 0):="111";
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dtack : in std_logic;
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addr : out std_logic_vector(31 downto 0);
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data_out : out std_logic_vector(15 downto 0);
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as : out std_logic;
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uds : out std_logic;
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lds : out std_logic;
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rw : out std_logic
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);
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end TG68;
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ARCHITECTURE logic OF TG68 IS
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COMPONENT TG68_fast
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PORT (
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clk : in std_logic;
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reset : in std_logic;
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clkena_in : in std_logic;
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data_in : in std_logic_vector(15 downto 0);
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IPL : in std_logic_vector(2 downto 0);
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test_IPL : in std_logic;
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address : out std_logic_vector(31 downto 0);
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data_write : out std_logic_vector(15 downto 0);
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state_out : out std_logic_vector(1 downto 0);
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decodeOPC : buffer std_logic;
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wr : out std_logic;
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UDS, LDS : out std_logic
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);
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END COMPONENT;
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SIGNAL as_s : std_logic;
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SIGNAL as_e : std_logic;
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SIGNAL uds_s : std_logic;
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SIGNAL uds_e : std_logic;
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SIGNAL lds_s : std_logic;
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SIGNAL lds_e : std_logic;
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SIGNAL rw_s : std_logic;
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SIGNAL rw_e : std_logic;
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SIGNAL waitm : std_logic;
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SIGNAL clkena_e : std_logic;
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SIGNAL S_state : std_logic_vector(1 downto 0);
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SIGNAL decode : std_logic;
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SIGNAL wr : std_logic;
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SIGNAL uds_in : std_logic;
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SIGNAL lds_in : std_logic;
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SIGNAL state : std_logic_vector(1 downto 0);
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SIGNAL clkena : std_logic;
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BEGIN
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TG68_fast_inst: TG68_fast
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PORT MAP (
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clk => not clk, -- : in std_logic;
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reset => reset, -- : in std_logic;
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clkena_in => clkena, -- : in std_logic;
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data_in => data_in, -- : in std_logic_vector(15 downto 0);
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IPL => IPL, -- : in std_logic_vector(2 downto 0);
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test_IPL => '0', -- : in std_logic;
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address => addr, -- : out std_logic_vector(31 downto 0);
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data_write => data_out, -- : out std_logic_vector(15 downto 0);
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state_out => state, -- : out std_logic_vector(1 downto 0);
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decodeOPC => decode, -- : buffer std_logic;
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wr => wr, -- : out std_logic;
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UDS => uds_in, -- : out std_logic;
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LDS => lds_in -- : out std_logic;
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);
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-- clkena <= '1' WHEN clkena_in='1' AND ((clkena_e OR decode)='1')
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-- ELSE '0';
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PROCESS (clk)
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BEGIN
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IF rising_edge(clk) THEN
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-- IF clkena_in='1' AND ((clkena_e OR decode)='1') THEN
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IF clkena_in='1' AND (clkena_e='1' OR state="01") THEN
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clkena <= '1';
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ELSE
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clkena <= '0';
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END IF;
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END IF;
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END PROCESS;
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PROCESS (clk, reset, state, as_s, as_e, rw_s, rw_e, uds_s, uds_e, lds_s, lds_e)
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BEGIN
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IF state="01" THEN
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as <= '1';
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rw <= '1';
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uds <= '1';
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lds <= '1';
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ELSE
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as <= as_s AND as_e;
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rw <= rw_s AND rw_e;
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uds <= uds_s AND uds_e;
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lds <= lds_s AND lds_e;
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END IF;
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IF reset='0' THEN
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S_state <= "11";
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as_s <= '1';
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rw_s <= '1';
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uds_s <= '1';
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lds_s <= '1';
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ELSIF rising_edge(clk) THEN
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IF clkena_in='1' THEN
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as_s <= '1';
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rw_s <= '1';
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uds_s <= '1';
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lds_s <= '1';
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IF state/="01" OR decode='1' THEN
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CASE S_state IS
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WHEN "00" => as_s <= '0';
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rw_s <= wr;
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IF wr='1' THEN
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uds_s <= uds_in;
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lds_s <= lds_in;
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END IF;
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S_state <= "01";
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WHEN "01" => as_s <= '0';
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rw_s <= wr;
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uds_s <= uds_in;
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lds_s <= lds_in;
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S_state <= "10";
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WHEN "10" =>
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rw_s <= wr;
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IF waitm='0' THEN
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S_state <= "11";
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END IF;
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WHEN "11" =>
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S_state <= "00";
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END CASE;
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END IF;
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END IF;
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END IF;
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IF reset='0' THEN
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as_e <= '1';
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rw_e <= '1';
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uds_e <= '1';
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lds_e <= '1';
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clkena_e <= '0';
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ELSIF falling_edge(clk) THEN
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IF clkena_in='1' THEN
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as_e <= '1';
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rw_e <= '1';
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uds_e <= '1';
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lds_e <= '1';
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clkena_e <= '0';
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CASE S_state IS
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WHEN "00" =>
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WHEN "01" =>
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WHEN "10" => as_e <= '0';
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uds_e <= uds_in;
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lds_e <= lds_in;
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IF state="01" THEN
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clkena_e <= '1';
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waitm <= '0';
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ELSE
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clkena_e <= NOT dtack;
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waitm <= dtack;
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END IF;
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WHEN "11" =>
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END CASE;
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END IF;
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END IF;
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END PROCESS;
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END;
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