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mcwaccent |
--
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--
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-- This file is a part of JOP, the Java Optimized Processor
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--
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-- Copyright (C) 2001-2008, Martin Schoeberl (martin@jopdesign.com)
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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-- decode.vhd
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--
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-- cpu decode of JOP3
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--
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-- generate control for pc and stack
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--
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--
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-- resources on ACEX1K30-3
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--
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-- xxx LCs, 42.0 MHz
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--
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-- todo:
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--
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--
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-- 2001-07-03 extracted from core.vhd
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-- 2001-10-28 ldjpc, stjpc
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-- 2001-10-31 stbc
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-- 2001-12-04 cp removed
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-- 2001-12-05 sel_rda, sel_wra: logic from ir (not registered)
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-- sel_smux: logic from ir (not registered, no mix addr/rd-ex: nop befor stsp)
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-- 2001-12-06 moved ir from decode to fetch, jbr unregistered
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-- 2001-12-07 moved jbr decode to bcfetch, ldi loads consts from ram (addr > 31), jp removed
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-- 2001-12-08 instruction set changed to 8 bit
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-- 2002-03-24 new shift instructions
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-- 2002-12-02 wait instruction for memory
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-- 2003-02-12 added instruction ld_opd_8u/16u
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-- 2004-10-07 new alu selection with sel_sub, sel_amux and ena_a
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-- 2004-10-08 moved bsy/pcwait from decode to fetch
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-- 2006-01-12 new ar for local memory addressing: star, ldmi, stmi
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-- stioa, stiod, ldiod removed
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-- 2007-08-31 use addr_width for signal dir
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-- 2007-09-01 use ram_width from jop_config instead of parameter
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--
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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use work.jop_config.all;
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use work.jop_types.all;
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entity decode is
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generic (
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i_width : integer -- instruction width
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);
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port (
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clk, reset : in std_logic;
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instr : in std_logic_vector(i_width-1 downto 0);
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zf, nf : in std_logic; -- nf, eq and lt not used (only brz, brnz)
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eq, lt : in std_logic;
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br : out std_logic;
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jbr : out std_logic;
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ext_addr : out std_logic_vector(EXTA_WIDTH-1 downto 0);
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rd, wr : out std_logic;
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dir : out std_logic_vector(ram_width-1 downto 0);
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sel_sub : out std_logic; -- 0..add, 1..sub
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sel_amux : out std_logic; -- 0..sum, 1..lmux
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ena_a : out std_logic; -- 1..store new value
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sel_bmux : out std_logic; -- 0..a, 1..mem
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sel_log : out std_logic_vector(1 downto 0); -- pop/st, and, or, xor
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sel_shf : out std_logic_vector(1 downto 0); -- sr, sl, sra, (sr)
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sel_lmux : out std_logic_vector(2 downto 0); -- log, shift, mem, io, reg
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sel_imux : out std_logic_vector(1 downto 0); -- java opds
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sel_rmux : out std_logic_vector(1 downto 0); -- sp, vp, jpc
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sel_smux : out std_logic_vector(1 downto 0); -- sp, a, sp-1, sp+1
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sel_mmux : out std_logic; -- 0..a, 1..b
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sel_rda : out std_logic_vector(2 downto 0); --
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sel_wra : out std_logic_vector(2 downto 0); --
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wr_ena : out std_logic;
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ena_b : out std_logic;
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ena_vp : out std_logic;
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ena_jpc : out std_logic;
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ena_ar : out std_logic
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);
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end decode;
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architecture rtl of decode is
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--
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-- Signals
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--
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--
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-- intruction register, shortcut
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--
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-- signal ir : std_logic_vector(i_width-1 downto 0); -- Xilinx does not like this... instruction register
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signal ir : std_logic_vector(7 downto 0); -- instruction register
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begin
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ir <= instr; -- registered in fetch
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ext_addr <= ir(EXTA_WIDTH-1 downto 0); -- address for extension select
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--
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-- branch, jbranch
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--
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process(clk, reset, ir, zf)
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begin
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if (reset='1') then
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br <= '0';
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elsif rising_edge(clk) then
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br <= '0';
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if((ir(7 downto 5)="010" and zf='1') or -- bz
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(ir(7 downto 5)="011" and zf='0')) then -- bnz
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br <= '1';
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end if;
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end if;
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end process;
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-- wait is decoded direct in fetch.vhd!
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process(ir)
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begin
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jbr <= '0';
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if (ir="10000010") then -- jbr: goto and if_xxx
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jbr <= '1';
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end if;
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end process;
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--
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-- addr, read stage:
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-- decode from ir (only logic, no register)
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--
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process(ir)
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begin
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-- ram wraddress and wrena are registered
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wr_ena <= '0';
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if (ir(7 downto 5)="101" or -- 'push' instructions
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ir(7 downto 5)="110" or
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ir(7 downto 5)="111" or
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ir(7 downto 5)="001" or -- stm
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ir(7 downto 3)="00010") then -- st, stn, stmi
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wr_ena <= '1';
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end if;
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rd <= '0';
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if ir(7 downto 3)="11100" then -- ld memio
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rd <= '1';
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end if;
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wr <= '0';
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if ir(7 downto 0)="00000110"
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or ir(7 downto 0)="00000111"
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or ir(7 downto 3)="00001" then -- st memio
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wr <= '1';
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end if;
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sel_imux <= ir(1 downto 0); -- ld opd_x
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-- select for rd/wr address muxes
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dir <= std_logic_vector(to_unsigned(0, ram_width-5)) & ir(4 downto 0);
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sel_rda <= "110"; -- sp
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if (ir(7 downto 3)="11101") then -- ld, ldn, ldmi
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sel_rda <= ir(2 downto 0);
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end if;
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if (ir(7 downto 5)="101") then -- ldm
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sel_rda <= "111";
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end if;
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if (ir(7 downto 5)="110") then -- ldi
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sel_rda <= "111";
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dir <= std_logic_vector(to_unsigned(1, ram_width-5)) &
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ir(4 downto 0); -- addr > 31 constants
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end if;
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sel_wra <= "110"; -- spp
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if ir(7 downto 3)="00010" then -- st, stn, stmi
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sel_wra <= ir(2 downto 0);
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end if;
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if ir(7 downto 5)="001" then -- stm
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sel_wra <= "111";
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end if;
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-- select for sp update
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sel_smux <= "00"; -- sp = sp
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if(ir(7)='0') then -- 'pop' instruction
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sel_smux <= "01"; -- --sp
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end if;
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if(ir(7 downto 5)="101" or -- 'push' instruction
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ir(7 downto 5)="110" or
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ir(7 downto 5)="111") then
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sel_smux <= "10"; -- ++sp
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end if;
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if (ir="00011011") then -- st sp
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sel_smux <= "11"; -- sp = a
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end if;
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end process;
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--
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-- ex stage
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--
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process(clk, reset)
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begin
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if (reset='1') then
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sel_sub <= '0';
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sel_amux <= '0';
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ena_a <= '0';
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sel_bmux <= '0';
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sel_log <= "00";
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sel_shf <= "00";
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sel_lmux <= "000";
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sel_rmux <= "00";
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sel_mmux <= '0';
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ena_b <= '0';
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ena_vp <= '0';
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ena_jpc <= '0';
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ena_ar <= '0';
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elsif rising_edge(clk) then
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sel_log <= "00";
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if (ir(7 downto 2)="000000") then -- pop, and, or, xor
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sel_log <= ir(1 downto 0);
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end if;
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sel_shf <= ir(1 downto 0);
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sel_sub <= '1'; -- default is subtract for lt-flag
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sel_amux <= '1'; -- default is lmux
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ena_a <= '1'; -- default is enable
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ena_vp <= '0';
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ena_jpc <= '0';
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ena_ar <= '0';
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case ir is
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when "00000000" => -- pop
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when "00000001" => -- and
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when "00000010" => -- or
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when "00000011" => -- xor
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when "00000100" => -- add
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sel_sub <= '0';
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sel_amux <= '0';
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when "00000101" => -- sub
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sel_amux <= '0';
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when "00001010" => -- stmra
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when "00001011" => -- stmwa
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when "00001100" => -- stmwd
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when "00001101" => -- stopa
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when "00001110" => -- stopb
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when "00010000" => -- st0
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when "00010001" => -- st1
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when "00010010" => -- st2
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when "00010011" => -- st3
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when "00010100" => -- st
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when "00010101" => -- stmi
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when "00011000" => -- stvp
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ena_vp <= '1';
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when "00011001" => -- stjpc
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ena_jpc <= '1';
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when "00011010" => -- star
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ena_ar <= '1';
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when "00011011" => -- stsp
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when "00011100" => -- ushr
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when "00011101" => -- shl
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when "00011110" => -- shr
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-- when "001-----" => -- stm
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-- when "010-----" => -- bz
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-- when "011-----" => -- bnz
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when "10000000" => -- nop
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ena_a <= '0';
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when "10000001" => -- wait
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ena_a <= '0';
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when "10000010" => -- jbr
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ena_a <= '0';
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-- when "101-----" => -- ldm
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-- when "110-----" => -- ldi
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when "11100010" => -- ldmrd
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when "11100011" => -- ldmbsy
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when "11100101" => -- ldmul
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when "11101000" => -- ld0
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when "11101001" => -- ld1
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when "11101010" => -- ld2
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when "11101011" => -- ld3
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when "11101100" => -- ld
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when "11101101" => -- ldmi
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when "11110000" => -- ldsp
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when "11110001" => -- ldvp
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when "11110010" => -- ldjpc
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when "11110100" => -- ld_opd_8u
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when "11110101" => -- ld_opd_8s
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when "11110110" => -- ld_opd_16u
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when "11110111" => -- ld_opd_16s
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when "11111000" => -- dup
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ena_a <= '0';
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when others =>
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null;
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end case;
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sel_lmux <= "000"; -- log
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if ir(7 downto 2)="000111" then -- ushr, shl, shr
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sel_lmux <= "001";
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end if;
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if ir(7 downto 5)="101" then -- ldm
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sel_lmux <= "010";
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end if;
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|
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if ir(7 downto 5)="110" then -- ldi
|
| 347 |
|
|
sel_lmux <= "010";
|
| 348 |
|
|
end if;
|
| 349 |
|
|
|
| 350 |
|
|
if ir(7 downto 3)="11101" then -- ld, ldn, ldmi
|
| 351 |
|
|
sel_lmux <= "010";
|
| 352 |
|
|
end if;
|
| 353 |
|
|
|
| 354 |
|
|
if ir(7 downto 2)="111101" then -- ld_opd_x
|
| 355 |
|
|
sel_lmux <= "011";
|
| 356 |
|
|
end if;
|
| 357 |
|
|
|
| 358 |
|
|
if ir(7 downto 3)="11100" then -- ld io
|
| 359 |
|
|
sel_lmux <= "100";
|
| 360 |
|
|
end if;
|
| 361 |
|
|
|
| 362 |
|
|
if ir(7 downto 2)="111100" then -- ldsp, ldvp, ldjpc
|
| 363 |
|
|
sel_lmux <= "101";
|
| 364 |
|
|
end if;
|
| 365 |
|
|
|
| 366 |
|
|
-- default 'pop'
|
| 367 |
|
|
sel_bmux <= '1'; -- mem
|
| 368 |
|
|
sel_mmux <= '0'; -- a
|
| 369 |
|
|
if (ir(7)='1') then -- 'push' and 'no stack change'
|
| 370 |
|
|
sel_bmux <= '0'; -- a
|
| 371 |
|
|
sel_mmux <= '1'; -- b
|
| 372 |
|
|
end if;
|
| 373 |
|
|
|
| 374 |
|
|
ena_b <= '1';
|
| 375 |
|
|
if (ir(7 downto 5)="100") then -- 'no stack change' (nop, jbr)
|
| 376 |
|
|
ena_b <= '0';
|
| 377 |
|
|
end if;
|
| 378 |
|
|
|
| 379 |
|
|
sel_rmux <= ir(1 downto 0); -- ldsp, ldvp, ldjpc
|
| 380 |
|
|
|
| 381 |
|
|
end if;
|
| 382 |
|
|
end process;
|
| 383 |
|
|
|
| 384 |
|
|
end rtl;
|
