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[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [Address Generation/] [JOP/] [sc_wizardry_fsm.vhd] - Blame information for rev 22

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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:02:03 01/30/2009 
-- Design Name: 
-- Module Name:    sc_wizardry_fsm - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity sc_wizardry_fsm is
    Port ( clock : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           rd : in  STD_LOGIC;
           wr : in  STD_LOGIC;
           ack_i : in  STD_LOGIC;
           err_i : in  STD_LOGIC;
           address_reg : in  STD_LOGIC_VECTOR (3 downto 0);
                          adr_o_reg : in std_logic_vector(21 downto 0);
                          dat_o_reg : in std_logic_Vector(31 downto 0);
           cyc_o : out  STD_LOGIC;
           stb_o : out  STD_LOGIC;
           we_o : out  STD_LOGIC;
           adr_o : out  STD_LOGIC_VECTOR (21 downto 0);
           dat_o : out  STD_LOGIC_VECTOR (31 downto 0);
           store_address : out  STD_LOGIC;
           store_data : out  STD_LOGIC;
                          store_config_data : out std_logic;
           rdy_cnt : out  unsigned (1 downto 0);
           set_sc_data : out  STD_LOGIC);
end sc_wizardry_fsm;
 
architecture Behavioral of sc_wizardry_fsm is
 
type statetype is (reset_state,wait_for_rd_wr,check_address_value,store_address_state,store_data_state,
                                            write_to_ddr,read_from_ddr,send_sc_ack,wait_for_write_ack,wait_for_read_ack,
                                                 prepare_sc_data,store_config_trigger_data);
signal currentstate, nextstate : statetype;
 
begin
 
process(currentstate,rd,wr,ack_i,address_reg,adr_o_reg,dat_o_reg)
begin
        case currentstate is
                when reset_state =>
                                nextstate <= wait_for_rd_wr;
                        cyc_o <= '0';
                        stb_o <= '0';
                        we_o <= '0';
                        adr_o <= (others => '0');
                        dat_o <= (others => '0');
                        store_address <= '0';
                        store_data <= '0';
                        store_config_data <= '0';
                        rdy_cnt <= "00";
                        set_sc_data <= '0';
 
                when wait_for_rd_wr =>
                                if wr = '1' then
                                        nextstate <= check_address_value;
                                elsif rd = '1' then
                                        nextstate <= prepare_sc_data;
                                else
                                        nextstate <= wait_for_rd_wr;
                                end if;
                        cyc_o <= '0';
                        stb_o <= '0';
                        we_o <= '0';
                        adr_o <= (others => '0');
                        dat_o <= (others => '0');
                        store_address <= '0';
                        store_data <= '0';
                        store_config_data <= '0';
                        rdy_cnt <= "00";
                        set_sc_data <= '0';
 
                when check_address_value =>
                                if address_reg = "0000" then
                                        nextstate <= store_address_state;
                                elsif address_reg = "0001" then
                                        nextstate <= store_data_state;
                                elsif address_reg = "0010" then
                                        nextstate <= write_to_ddr;
                                elsif address_reg = "0011" then
                                        nextstate <= read_from_ddr;
                                elsif address_reg = "0100" then
                                        nextstate <= store_config_trigger_data;
                                else
                                        nextstate <= send_sc_ack; --may need to send a sc ack (rdy_cnt);
                                end if;
                        cyc_o <= '0';
                        stb_o <= '0';
                        we_o <= '0';
                        adr_o <= (others => '0');
                        dat_o <= (others => '0');
                        store_address <= '0';
                        store_data <= '0';
                        store_config_data <= '0';
                        rdy_cnt <= "11";
                        set_sc_data <= '0';
 
                when store_address_state =>
                                nextstate <= send_sc_ack;
                        cyc_o <= '0';
                        stb_o <= '0';
                        we_o <= '0';
                        adr_o <= (others => '0');
                        dat_o <= (others => '0');
                        store_address <= '1';
                        store_data <= '0';
                        store_config_data <= '0';
                        rdy_cnt <= "11";
                        set_sc_data <= '0';
 
                when store_data_state =>
                                nextstate <= send_sc_ack;
                        cyc_o <= '0';
                        stb_o <= '0';
                        we_o <= '0';
                        adr_o <= (others => '0');
                        dat_o <= (others => '0');
                        store_address <= '0';
                        store_data <= '1';
                        store_config_data <= '0';
                        rdy_cnt <= "11";
                        set_sc_data <= '0';
 
                when store_config_trigger_data =>
                                nextstate <= send_sc_ack;
                        cyc_o <= '0';
                        stb_o <= '0';
                        we_o <= '0';
                        adr_o <= (others => '0');
                        dat_o <= (others => '0');
                        store_address <= '0';
                        store_data <= '0';
                        store_config_data <= '1';
                        rdy_cnt <= "11";
                        set_sc_data <= '0';
 
                when write_to_ddr =>
                                nextstate <= wait_for_write_ack;
                        cyc_o <= '1';
                        stb_o <= '1';
                        we_o <= '1';
                        adr_o <= adr_o_reg;
                        dat_o <= dat_o_reg;
                        store_address <= '0';
                        store_data <= '0';
                        store_config_data <= '0';
                        rdy_cnt <= "11";
                        set_sc_data <= '0';
 
                when wait_for_write_ack =>
                                if ack_i = '1' then
                                        nextstate <= send_sc_ack;
                                else
                                        nextstate <= wait_for_write_ack;
                                end if;
                        cyc_o <= '1';
                        stb_o <= '1';
                        we_o <= '1';
                        adr_o <= adr_o_reg;
                        dat_o <= dat_o_reg;
                        store_address <= '0';
                        store_data <= '0';
                        store_config_data <= '0';
                        rdy_cnt <= "11";
                        set_sc_data <= '0';
 
                when read_from_ddr =>
                                nextstate <= wait_for_read_ack;
                        cyc_o <= '1';
                        stb_o <= '1';
                        we_o <= '0';
                        adr_o <= adr_o_reg;
                        dat_o <= (others => '0');
                        store_address <= '0';
                        store_data <= '0';
                        store_config_data <= '0';
                        rdy_cnt <= "11";
                        set_sc_data <= '0';
 
                when wait_for_read_ack =>
                                if ack_i = '1' then
                                        nextstate <= send_sc_ack;
                                else
                                        nextstate <= wait_for_read_ack;
                                end if;
                        cyc_o <= '1';
                        stb_o <= '1';
                        we_o <= '0';
                        adr_o <= adr_o_reg;
                        dat_o <= (others => '0');
                        store_address <= '0';
                        store_data <= '0';
                        store_config_data <= '0';
                        rdy_cnt <= "11";
                        set_sc_data <= '0';
 
                when send_sc_ack =>
                                nextstate <= wait_for_rd_wr;
                        cyc_o <= '0';
                        stb_o <= '0';
                        we_o <= '0';
                        adr_o <= (others => '0');
                        dat_o <= (others => '0');
                        store_address <= '0';
                        store_data <= '0';
                        store_config_data <= '0';
                        rdy_cnt <= "00";
                        set_sc_data <= '0';
 
                when prepare_sc_data =>
                                nextstate <= send_sc_ack;
                        cyc_o <= '0';
                        stb_o <= '0';
                        we_o <= '0';
                        adr_o <= (others => '0');
                        dat_o <= (others => '0');
                        store_address <= '0';
                        store_data <= '0';
                        store_config_data <= '0';
                        rdy_cnt <= "11";
                        set_sc_data <= '1';
 
                when others =>
                                nextstate <= reset_state;
                        cyc_o <= '0';
                        stb_o <= '0';
                        we_o <= '0';
                        adr_o <= (others => '0');
                        dat_o <= (others => '0');
                        store_address <= '0';
                        store_data <= '0';
                        store_config_data <= '0';
                        rdy_cnt <= "11";
                        set_sc_data <= '0';
        end case;
end process;
 
process(clock,reset)
begin
        if reset = '1' then
                currentstate <= reset_state;
        elsif rising_Edge(clock) then
                currentstate <= nextstate;
        end if;
end process;
 
end Behavioral;
 

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Subversion Repositories the_wizardry_project

[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [Address Generation/] [JOP/] [sc_wizardry_fsm.vhd] - Blame information for rev 22

Line No.	Rev	Author	Line
1	22	mcwaccent	`----------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer:`
4			`--`
5			`-- Create Date: 10:02:03 01/30/2009`
6			`-- Design Name:`
7			`-- Module Name: sc_wizardry_fsm - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`----------------------------------------------------------------------------------`
20			`library IEEE;`
21			`use IEEE.STD_LOGIC_1164.ALL;`
22			`--use IEEE.STD_LOGIC_ARITH.ALL;`
23			`--use IEEE.STD_LOGIC_UNSIGNED.ALL;`
24			`use ieee.numeric_std.all;`
25			`---- Uncomment the following library declaration if instantiating`
26			`---- any Xilinx primitives in this code.`
27			`--library UNISIM;`
28			`--use UNISIM.VComponents.all;`
29
30			`entity sc_wizardry_fsm is`
31			`Port ( clock : in STD_LOGIC;`
32			`reset : in STD_LOGIC;`
33			`rd : in STD_LOGIC;`
34			`wr : in STD_LOGIC;`
35			`ack_i : in STD_LOGIC;`
36			`err_i : in STD_LOGIC;`
37			`address_reg : in STD_LOGIC_VECTOR (3 downto 0);`
38			`adr_o_reg : in std_logic_vector(21 downto 0);`
39			`dat_o_reg : in std_logic_Vector(31 downto 0);`
40			`cyc_o : out STD_LOGIC;`
41			`stb_o : out STD_LOGIC;`
42			`we_o : out STD_LOGIC;`
43			`adr_o : out STD_LOGIC_VECTOR (21 downto 0);`
44			`dat_o : out STD_LOGIC_VECTOR (31 downto 0);`
45			`store_address : out STD_LOGIC;`
46			`store_data : out STD_LOGIC;`
47			`store_config_data : out std_logic;`
48			`rdy_cnt : out unsigned (1 downto 0);`
49			`set_sc_data : out STD_LOGIC);`
50			`end sc_wizardry_fsm;`
51
52			`architecture Behavioral of sc_wizardry_fsm is`
53
54			`type statetype is (reset_state,wait_for_rd_wr,check_address_value,store_address_state,store_data_state,`
55			`write_to_ddr,read_from_ddr,send_sc_ack,wait_for_write_ack,wait_for_read_ack,`
56			`prepare_sc_data,store_config_trigger_data);`
57			`signal currentstate, nextstate : statetype;`
58
59			`begin`
60
61			`process(currentstate,rd,wr,ack_i,address_reg,adr_o_reg,dat_o_reg)`
62			`begin`
63			`case currentstate is`
64			`when reset_state =>`
65			`nextstate <= wait_for_rd_wr;`
66			`cyc_o <= '0';`
67			`stb_o <= '0';`
68			`we_o <= '0';`
69			`adr_o <= (others => '0');`
70			`dat_o <= (others => '0');`
71			`store_address <= '0';`
72			`store_data <= '0';`
73			`store_config_data <= '0';`
74			`rdy_cnt <= "00";`
75			`set_sc_data <= '0';`
76
77			`when wait_for_rd_wr =>`
78			`if wr = '1' then`
79			`nextstate <= check_address_value;`
80			`elsif rd = '1' then`
81			`nextstate <= prepare_sc_data;`
82			`else`
83			`nextstate <= wait_for_rd_wr;`
84			`end if;`
85			`cyc_o <= '0';`
86			`stb_o <= '0';`
87			`we_o <= '0';`
88			`adr_o <= (others => '0');`
89			`dat_o <= (others => '0');`
90			`store_address <= '0';`
91			`store_data <= '0';`
92			`store_config_data <= '0';`
93			`rdy_cnt <= "00";`
94			`set_sc_data <= '0';`
95
96			`when check_address_value =>`
97			`if address_reg = "0000" then`
98			`nextstate <= store_address_state;`
99			`elsif address_reg = "0001" then`
100			`nextstate <= store_data_state;`
101			`elsif address_reg = "0010" then`
102			`nextstate <= write_to_ddr;`
103			`elsif address_reg = "0011" then`
104			`nextstate <= read_from_ddr;`
105			`elsif address_reg = "0100" then`
106			`nextstate <= store_config_trigger_data;`
107			`else`
108			`nextstate <= send_sc_ack; --may need to send a sc ack (rdy_cnt);`
109			`end if;`
110			`cyc_o <= '0';`
111			`stb_o <= '0';`
112			`we_o <= '0';`
113			`adr_o <= (others => '0');`
114			`dat_o <= (others => '0');`
115			`store_address <= '0';`
116			`store_data <= '0';`
117			`store_config_data <= '0';`
118			`rdy_cnt <= "11";`
119			`set_sc_data <= '0';`
120
121			`when store_address_state =>`
122			`nextstate <= send_sc_ack;`
123			`cyc_o <= '0';`
124			`stb_o <= '0';`
125			`we_o <= '0';`
126			`adr_o <= (others => '0');`
127			`dat_o <= (others => '0');`
128			`store_address <= '1';`
129			`store_data <= '0';`
130			`store_config_data <= '0';`
131			`rdy_cnt <= "11";`
132			`set_sc_data <= '0';`
133
134			`when store_data_state =>`
135			`nextstate <= send_sc_ack;`
136			`cyc_o <= '0';`
137			`stb_o <= '0';`
138			`we_o <= '0';`
139			`adr_o <= (others => '0');`
140			`dat_o <= (others => '0');`
141			`store_address <= '0';`
142			`store_data <= '1';`
143			`store_config_data <= '0';`
144			`rdy_cnt <= "11";`
145			`set_sc_data <= '0';`
146
147			`when store_config_trigger_data =>`
148			`nextstate <= send_sc_ack;`
149			`cyc_o <= '0';`
150			`stb_o <= '0';`
151			`we_o <= '0';`
152			`adr_o <= (others => '0');`
153			`dat_o <= (others => '0');`
154			`store_address <= '0';`
155			`store_data <= '0';`
156			`store_config_data <= '1';`
157			`rdy_cnt <= "11";`
158			`set_sc_data <= '0';`
159
160			`when write_to_ddr =>`
161			`nextstate <= wait_for_write_ack;`
162			`cyc_o <= '1';`
163			`stb_o <= '1';`
164			`we_o <= '1';`
165			`adr_o <= adr_o_reg;`
166			`dat_o <= dat_o_reg;`
167			`store_address <= '0';`
168			`store_data <= '0';`
169			`store_config_data <= '0';`
170			`rdy_cnt <= "11";`
171			`set_sc_data <= '0';`
172
173			`when wait_for_write_ack =>`
174			`if ack_i = '1' then`
175			`nextstate <= send_sc_ack;`
176			`else`
177			`nextstate <= wait_for_write_ack;`
178			`end if;`
179			`cyc_o <= '1';`
180			`stb_o <= '1';`
181			`we_o <= '1';`
182			`adr_o <= adr_o_reg;`
183			`dat_o <= dat_o_reg;`
184			`store_address <= '0';`
185			`store_data <= '0';`
186			`store_config_data <= '0';`
187			`rdy_cnt <= "11";`
188			`set_sc_data <= '0';`
189
190			`when read_from_ddr =>`
191			`nextstate <= wait_for_read_ack;`
192			`cyc_o <= '1';`
193			`stb_o <= '1';`
194			`we_o <= '0';`
195			`adr_o <= adr_o_reg;`
196			`dat_o <= (others => '0');`
197			`store_address <= '0';`
198			`store_data <= '0';`
199			`store_config_data <= '0';`
200			`rdy_cnt <= "11";`
201			`set_sc_data <= '0';`
202
203			`when wait_for_read_ack =>`
204			`if ack_i = '1' then`
205			`nextstate <= send_sc_ack;`
206			`else`
207			`nextstate <= wait_for_read_ack;`
208			`end if;`
209			`cyc_o <= '1';`
210			`stb_o <= '1';`
211			`we_o <= '0';`
212			`adr_o <= adr_o_reg;`
213			`dat_o <= (others => '0');`
214			`store_address <= '0';`
215			`store_data <= '0';`
216			`store_config_data <= '0';`
217			`rdy_cnt <= "11";`
218			`set_sc_data <= '0';`
219
220			`when send_sc_ack =>`
221			`nextstate <= wait_for_rd_wr;`
222			`cyc_o <= '0';`
223			`stb_o <= '0';`
224			`we_o <= '0';`
225			`adr_o <= (others => '0');`
226			`dat_o <= (others => '0');`
227			`store_address <= '0';`
228			`store_data <= '0';`
229			`store_config_data <= '0';`
230			`rdy_cnt <= "00";`
231			`set_sc_data <= '0';`
232
233			`when prepare_sc_data =>`
234			`nextstate <= send_sc_ack;`
235			`cyc_o <= '0';`
236			`stb_o <= '0';`
237			`we_o <= '0';`
238			`adr_o <= (others => '0');`
239			`dat_o <= (others => '0');`
240			`store_address <= '0';`
241			`store_data <= '0';`
242			`store_config_data <= '0';`
243			`rdy_cnt <= "11";`
244			`set_sc_data <= '1';`
245
246			`when others =>`
247			`nextstate <= reset_state;`
248			`cyc_o <= '0';`
249			`stb_o <= '0';`
250			`we_o <= '0';`
251			`adr_o <= (others => '0');`
252			`dat_o <= (others => '0');`
253			`store_address <= '0';`
254			`store_data <= '0';`
255			`store_config_data <= '0';`
256			`rdy_cnt <= "11";`
257			`set_sc_data <= '0';`
258			`end case;`
259			`end process;`
260
261			`process(clock,reset)`
262			`begin`
263			`if reset = '1' then`
264			`currentstate <= reset_state;`
265			`elsif rising_Edge(clock) then`
266			`currentstate <= nextstate;`
267			`end if;`
268			`end process;`
269
270			`end Behavioral;`
271