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[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [Address Generation/] [JOP/] [sc_wizardry_processes.vhd] - Blame information for rev 22

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1 22 mcwaccent 
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date:    10:07:42 01/30/2009
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-- Design Name:
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-- Module Name:    sc_wizardry_processes - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity sc_wizardry_processes is
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   port(  clk : in std_logic;
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                         reset : in std_logic;
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                         rd : in std_logic;
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                         wr : in std_logic;
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                         ack_i : in std_Logic;
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                         dat_i : in std_logic_Vector(31 downto 0);
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                         address : in std_logic_Vector(3 downto 0);
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                         wr_data : in std_Logic_Vector(31 downto 0);
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                         rd_data : out std_logic_Vector(31 downto 0);
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                         store_address : in std_Logic;
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                         store_data : in std_Logic;
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                         store_config_data : in  STD_LOGIC;
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                         set_sc_data : in std_Logic;
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                         adr_o_reg : out std_logic_Vector(21 downto 0);
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                         dat_o_reg : out std_logic_Vector(31 downto 0);
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--                       config_trigger_reg : out std_logic_vector(7 downto 0);
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                         eRCP_trigger_reg : out std_logic;
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                         address_reg : out std_logic_vector(3 downto 0));
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end sc_wizardry_processes;
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architecture Behavioral of sc_wizardry_processes is
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signal adr_o_reg_s : std_logic_Vector(21 downto 0);
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signal dat_o_reg_s : std_logic_vector(31 downto 0);
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signal wr_data_reg : std_logic_vector(31 downto 0);
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signal address_reg_s : std_logic_vector(3 downto 0);
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signal rd_data_reg : std_logic_vector(31 downto 0);
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signal dat_i_reg : std_logic_vector(31 downto 0);
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signal config_trigger_reg_s : std_logic_vector(7 downto 0);
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signal eRCP_trigger_reg_s,eRCP_trigger_reg_s_1,eRCP_trigger_reg_s_2,
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                eRCP_trigger_reg_s_3: std_logic; --_vector(7 downto 0);
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begin
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process(clk,reset,set_sc_data)
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begin
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        if reset = '1' then
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                rd_data_reg <= X"075bcd15";--(others => '0');
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        elsif rising_Edge(clk) then
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                if set_sc_data = '1' then
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                        rd_data_reg <= dat_i_reg;
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                else
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                        rd_data_reg <= rd_data_reg;
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                end if;
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        end if;
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end process;
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rd_data <= rd_data_reg;
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process(clk,reset,ack_i)
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begin
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        if reset = '1' then
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                dat_i_reg <= X"075BCD14";--(others => '0');
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        elsif rising_Edge(clk) then
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                if ack_i = '1' then
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                        dat_i_reg <= dat_i;
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                else
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                        dat_i_reg <= dat_i_reg;
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                end if;
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        end if;
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end process;
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process(clk,reset,wr)
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begin
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        if reset = '1' then
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                wr_data_reg <= (others => '0');
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        elsif rising_edge(clk) then
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                if wr = '1' then
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                        wr_data_reg <= wr_data;
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                else
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                        wr_data_reg <= wr_data_reg;
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                end if;
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        end if;
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end process;
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process(clk,reset,wr,rd,address)
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begin
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        if reset = '1' then
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                address_reg_s <= (others => '0');
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        elsif rising_Edge(clk) then
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                if wr = '1' or rd = '1' then
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                        address_reg_s <= address; --(1 downto 0);
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                else
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                        address_reg_s <= address_reg_s;
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                end if;
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        end if;
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end process;
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address_reg <= address_reg_s;
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process(clk,reset,store_data)
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begin
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        if reset = '1' then
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                dat_o_reg_s <= (others => '0');
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        elsif rising_edge(clk) then
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                if store_data = '1' then
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                        dat_o_reg_s <= wr_data_reg;
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                else
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                        dat_o_reg_s <= dat_o_reg_s;
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                end if;
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        end if;
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end process;
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dat_o_reg <= dat_o_reg_s;
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process(clk,reset,store_address)
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begin
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        if reset = '1' then
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                adr_o_reg_s <= (others => '0');
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        elsif rising_edge(clk) then
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                if store_address = '1' then
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                        adr_o_reg_s <= wr_data_reg(21 downto 0);
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                else
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                        adr_o_reg_s <= adr_o_reg_s;
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                end if;
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        end if;
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end process;
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adr_o_reg <= adr_o_reg_s;
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process(clk,reset,store_config_data,eRCP_trigger_reg_s_1,eRCP_trigger_reg_s_2,
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                        eRCP_trigger_reg_s_3)
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begin
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        if reset = '1' then
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--              config_trigger_reg_s <= (others => '0');
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                eRCP_trigger_reg_s_1 <= '1';
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                eRCP_trigger_reg_s_2 <= '0';
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                eRCP_trigger_reg_s_3 <= '0';
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                eRCP_trigger_reg_s <= '0';
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        elsif rising_edge(clk) then
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                if store_config_data = '1' then
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                        eRCP_trigger_reg_s_1 <= '1';
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                        eRCP_trigger_reg_s_2 <= '0';
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                        eRCP_trigger_reg_s_3 <= '0';
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                        eRCP_trigger_reg_s <= '0';
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                else
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                        eRCP_trigger_reg_s_1 <= '0';
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                        eRCP_trigger_reg_s_2 <= eRCP_trigger_reg_s_1;
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                        eRCP_trigger_reg_s_3 <= eRCP_trigger_reg_s_2;
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                        eRCP_trigger_reg_s <= eRCP_trigger_reg_s_3;
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--                      eRCP_trigger_reg_s <= eRCP_trigger_reg_s;
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--                      eRCP_trigger_reg_s <= eRCP_trigger_reg_s;
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                end if;
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        end if;
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end process;
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eRCP_trigger_reg <= eRCP_trigger_reg_s;
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--process(clk,reset,store_config_data)
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--begin
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--      if reset = '1' then
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--              config_trigger_reg_s <= (others => '0');
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--      elsif rising_edge(clk) then
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--              if store_config_data = '1' then
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--                      config_trigger_reg_s <= wr_data_reg(7 downto 0);
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--              else
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--                      config_trigger_reg_s <= config_trigger_reg_s;
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--              end if;
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--      end if;
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--end process;
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--config_trigger_reg <= config_trigger_reg_s;
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end Behavioral;
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