OpenCores
URL https://opencores.org/ocsvn/the_wizardry_project/the_wizardry_project/trunk

Subversion Repositories the_wizardry_project

[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [Address Generation/] [JOP/] [shift.vhd] - Blame information for rev 22

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 22 mcwaccent
--
2
--
3
--  This file is a part of JOP, the Java Optimized Processor
4
--
5
--  Copyright (C) 2001-2008, Martin Schoeberl (martin@jopdesign.com)
6
--
7
--  This program is free software: you can redistribute it and/or modify
8
--  it under the terms of the GNU General Public License as published by
9
--  the Free Software Foundation, either version 3 of the License, or
10
--  (at your option) any later version.
11
--
12
--  This program is distributed in the hope that it will be useful,
13
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
14
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
--  GNU General Public License for more details.
16
--
17
--  You should have received a copy of the GNU General Public License
18
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
19
--
20
 
21
 
22
--
23
--      shift.vhd
24
--
25
--      barrel shifter
26
--      
27
--      resources on ACEX1K
28
--
29
--      
30
--              227 LCs
31
--
32
--      2001-05-14      first version
33
--
34
 
35
 
36
library ieee ;
37
use ieee.std_logic_1164.all ;
38
use ieee.numeric_std.all ;
39
 
40
 
41
entity shift is
42
 
43
generic (
44
        width           : integer := 32         -- one data word
45
);
46
 
47
port (
48
        din                     : in std_logic_vector(width-1 downto 0);
49
        off                     : in std_logic_vector(4 downto 0);
50
        shtyp           : in std_logic_vector(1 downto 0);
51
        dout            : out std_logic_vector(width-1 downto 0)
52
);
53
end shift;
54
 
55
 
56
architecture rtl of shift is
57
 
58
--
59
--      Signals
60
--
61
        signal zero32                   : std_logic_vector(width-1 downto 0);
62
 
63
 
64
begin
65
 
66
        zero32 <= (others => '0');
67
 
68
process(din, off, shtyp, zero32)
69
 
70
        variable shiftin : std_logic_vector(63 downto 0);
71
        variable shiftcnt : std_logic_vector(4 downto 0);
72
 
73
begin
74
 
75
        shiftin := zero32 & din;
76
        shiftcnt := off;
77
 
78
        if shtyp="01" then      -- sll
79
                shiftin(31 downto 0) := zero32;
80
                shiftin(63 downto 31) := '0' & din;
81
                shiftcnt := not shiftcnt;
82
        elsif shtyp="10" then   -- sra
83
                if din(31) = '1' then
84
                        shiftin(63 downto 32) := (others => '1');
85
                else
86
                        shiftin(63 downto 32) := zero32;
87
                end if;
88
        end if;
89
 
90
--
91
--      00      ushr
92
--      01      shl
93
--      10      shr
94
--      11      not used!
95
--
96
--      das geht aber nicht!!! TODO schaun warum
97
--
98
--      if shtyp(0)='1' then    -- sll
99
--              shiftin := din & zero32;
100
--              shiftcnt := not off;
101
--      else                            -- sr
102
--              shiftin(31 downto 0) := din;
103
--              shiftcnt := off;
104
--
105
--              if shtyp(1)='1' and din(31) = '1' then          -- sra
106
--                      shiftin(63 downto 32) := (others => '1');
107
--              else
108
--                      shiftin(63 downto 32) := zero32;
109
--              end if;
110
--      end if;
111
 
112
        if shiftcnt (4) = '1' then
113
                shiftin(47 downto 0) := shiftin(63 downto 16);
114
        end if;
115
        if shiftcnt (3) = '1' then
116
                shiftin(39 downto 0) := shiftin(47 downto 8);
117
        end if;
118
        if shiftcnt (2) = '1' then
119
                shiftin(35 downto 0) := shiftin(39 downto 4);
120
        end if;
121
        if shiftcnt (1) = '1' then
122
                shiftin(33 downto 0) := shiftin(35 downto 2);
123
        end if;
124
        if shiftcnt (0) = '1' then
125
                shiftin(31 downto 0) := shiftin(32 downto 1);
126
        end if;
127
 
128
        dout <= shiftin(31 downto 0);
129
 
130
end process;
131
 
132
end rtl;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.