1 |
19 |
mcwaccent |
----------------------------------------------------------------------------------
|
2 |
|
|
--
|
3 |
|
|
-- This file is a part of Technica Corporation Wizardry Project
|
4 |
|
|
--
|
5 |
|
|
-- Copyright (C) 2004-2009, Technica Corporation
|
6 |
|
|
--
|
7 |
|
|
-- This program is free software: you can redistribute it and/or modify
|
8 |
|
|
-- it under the terms of the GNU General Public License as published by
|
9 |
|
|
-- the Free Software Foundation, either version 3 of the License, or
|
10 |
|
|
-- (at your option) any later version.
|
11 |
|
|
--
|
12 |
|
|
-- This program is distributed in the hope that it will be useful,
|
13 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
14 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
15 |
|
|
-- GNU General Public License for more details.
|
16 |
|
|
--
|
17 |
|
|
-- You should have received a copy of the GNU General Public License
|
18 |
|
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
19 |
|
|
--
|
20 |
|
|
----------------------------------------------------------------------------------
|
21 |
|
|
----------------------------------------------------------------------------------
|
22 |
|
|
-- Module Name: fsm_ppt - Behavioral
|
23 |
|
|
-- Project Name: Wizardry
|
24 |
|
|
-- Target Devices: Virtex 4 ML401
|
25 |
|
|
-- Description: Keeps track of which ports have been encountered and
|
26 |
|
|
-- Revision: 1.0
|
27 |
|
|
-- Additional Comments:
|
28 |
|
|
--
|
29 |
|
|
----------------------------------------------------------------------------------
|
30 |
|
|
library IEEE;
|
31 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
32 |
|
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
33 |
|
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
34 |
|
|
use work.port_block_constants.all;
|
35 |
|
|
|
36 |
|
|
---- Uncomment the following library declaration if instantiating
|
37 |
|
|
---- any Xilinx primitives in this code.
|
38 |
|
|
--library UNISIM;
|
39 |
|
|
--use UNISIM.VComponents.all;
|
40 |
|
|
|
41 |
|
|
entity fsm_ppt is
|
42 |
|
|
Port ( clock : in STD_LOGIC;
|
43 |
|
|
reset : in STD_LOGIC;
|
44 |
|
|
frame_counters : in frame_counters_type;
|
45 |
|
|
fifo_empty : in STD_LOGIC;
|
46 |
|
|
lut_info : in lut_check;
|
47 |
|
|
lut_ptr : in integer range 0 to MAX_NUM_PORTS_2_FIND-1;
|
48 |
|
|
fifo_data_out : in STD_LOGIC_VECTOR (16 downto 0);
|
49 |
|
|
ack_i : in STD_LOGIC;
|
50 |
|
|
dat_i : in STD_LOGIC_VECTOR (31 downto 0);
|
51 |
|
|
dat_o : out STD_LOGIC_VECTOR (31 downto 0);
|
52 |
|
|
adr_o : out STD_LOGIC_VECTOR (21 downto 0);
|
53 |
|
|
cyc_o : out STD_LOGIC;
|
54 |
|
|
stb_o : out STD_LOGIC;
|
55 |
|
|
we_o : out STD_LOGIC;
|
56 |
|
|
fifo_pop : out STD_LOGIC;
|
57 |
|
|
load_lut : out STD_LOGIC;
|
58 |
|
|
enable_lut_search : out STD_LOGIC);
|
59 |
|
|
end fsm_ppt;
|
60 |
|
|
|
61 |
|
|
architecture Behavioral of fsm_ppt is
|
62 |
|
|
|
63 |
|
|
type statetype is (reset_state,idle_0_0,idle_0,idle,lut_search,read_lut,read_ddr,
|
64 |
|
|
load_lut_value,write_1_to_ddr,pop_fifo,pop_fifo_wait,
|
65 |
|
|
increment_ddr_read_data,write_inc_data_2_ddr,store_lut_2_ddr,
|
66 |
|
|
store_lut_2_ddr_0,update_counters_2_ddr,update_counters_2_ddr_0,
|
67 |
|
|
inc_counter_ptr,completed_update,store_lut_delim,store_lut_delim_0,
|
68 |
|
|
inc_counter_ptr_wait,check_counter_ptr,write_1_to_ddr_0,read_ddr_0,
|
69 |
|
|
check_fifo,write_inc_data_2_ddr_0,store_lut_delim_wait,
|
70 |
|
|
register_ddr_address,register_ddr_address_2,update_counters_2_ddr_1);
|
71 |
|
|
|
72 |
|
|
signal currentstate,nextstate : statetype;
|
73 |
|
|
signal increment_rd_data : std_logic;
|
74 |
|
|
signal frame_counters_reg : frame_counters_array_type;
|
75 |
|
|
signal dat_i_reg : std_logic_Vector(31 downto 0);
|
76 |
|
|
signal counter_snapshot : std_logic;
|
77 |
|
|
signal update_complete : std_logic;
|
78 |
|
|
signal update_counters : std_logic;
|
79 |
|
|
signal increment_counter_ptr : std_logic;
|
80 |
|
|
signal dat_i_inc_reg : std_logic_vector(31 downto 0);
|
81 |
|
|
signal counter_ptr : integer range 0 to 7;
|
82 |
|
|
signal counter_address_reg : std_logic_vector(21 downto 0);
|
83 |
|
|
signal new_counter_address_reg : std_logic_Vector(21 downto 0);
|
84 |
|
|
signal lut_port_address_reg : std_logic_vector(21 downto 0);
|
85 |
|
|
signal lut_port_delim_address_Reg : std_logic_Vector(21 downto 0);
|
86 |
|
|
signal dat_o_reg : std_logic_vector(31 downto 0);
|
87 |
|
|
signal register_address : std_logic;
|
88 |
|
|
signal frame_counter_address_reg : std_logic_vector(21 downto 0);
|
89 |
|
|
signal lut_start_address : std_logic_vector(21 downto 0);
|
90 |
|
|
|
91 |
|
|
begin
|
92 |
|
|
|
93 |
|
|
|
94 |
|
|
lut_start_address <= SHARED_MEM_LUT_SRC_START & "0000000000000";
|
95 |
|
|
|
96 |
|
|
process(clock,reset,counter_snapshot,counter_ptr)
|
97 |
|
|
begin
|
98 |
|
|
if rising_edge(clock) then
|
99 |
|
|
if reset = '1' then
|
100 |
|
|
frame_counter_address_reg <= (others => '0');
|
101 |
|
|
elsif counter_snapshot = '1' then
|
102 |
|
|
frame_counter_address_reg <= SHARED_MEM_COUNTER_START & conv_std_logic_vector(counter_ptr,13);
|
103 |
|
|
else
|
104 |
|
|
frame_counter_address_reg <= frame_counter_address_reg;
|
105 |
|
|
end if;
|
106 |
|
|
end if;
|
107 |
|
|
end process;
|
108 |
|
|
|
109 |
|
|
process(clock,register_address)
|
110 |
|
|
begin
|
111 |
|
|
if rising_edge(clock) then
|
112 |
|
|
if register_address = '1' then
|
113 |
|
|
dat_o_reg <= conv_std_logic_vector(lut_ptr-1,15) & fifo_data_out(16 downto 0);
|
114 |
|
|
else
|
115 |
|
|
dat_o_reg <= dat_o_reg;
|
116 |
|
|
end if;
|
117 |
|
|
end if;
|
118 |
|
|
end process;
|
119 |
|
|
|
120 |
|
|
process(clock,reset,register_address,lut_info)
|
121 |
|
|
begin
|
122 |
|
|
if rising_Edge(clock) then
|
123 |
|
|
if reset = '1' then
|
124 |
|
|
counter_address_reg <= (others => '0');
|
125 |
|
|
elsif (register_address = '1' and lut_info.in_lut = true )then
|
126 |
|
|
counter_address_reg <= SHARED_MEM_PREFIX_SOURCE & conv_std_logic_vector(lut_info.lut_pointer,13);
|
127 |
|
|
else
|
128 |
|
|
counter_address_reg <= counter_address_reg;
|
129 |
|
|
end if;
|
130 |
|
|
end if;
|
131 |
|
|
end process;
|
132 |
|
|
|
133 |
|
|
process(clock,reset,register_address,lut_ptr)
|
134 |
|
|
begin
|
135 |
|
|
if rising_edge(clock) then
|
136 |
|
|
if reset = '1' then
|
137 |
|
|
new_counter_address_reg <= (others => '0');
|
138 |
|
|
elsif register_address = '1' then
|
139 |
|
|
new_counter_address_reg <= SHARED_MEM_PREFIX_SOURCE & conv_std_logic_Vector(lut_ptr,13);
|
140 |
|
|
else
|
141 |
|
|
new_counter_address_reg <= new_counter_address_reg;
|
142 |
|
|
end if;
|
143 |
|
|
end if;
|
144 |
|
|
end process;
|
145 |
|
|
|
146 |
|
|
process(clock,reset,register_address,lut_ptr)
|
147 |
|
|
begin
|
148 |
|
|
if rising_edge(clock) then
|
149 |
|
|
if reset = '1' then
|
150 |
|
|
lut_port_address_reg <= (others => '0');
|
151 |
|
|
elsif register_address = '1' then
|
152 |
|
|
lut_port_address_reg <= SHARED_MEM_LUT_SRC_START & conv_std_logic_vector(lut_ptr-1,13);
|
153 |
|
|
else
|
154 |
|
|
lut_port_address_reg <= lut_port_address_reg;
|
155 |
|
|
end if;
|
156 |
|
|
end if;
|
157 |
|
|
end process;
|
158 |
|
|
|
159 |
|
|
process(clock,reset,register_address,lut_ptr)
|
160 |
|
|
begin
|
161 |
|
|
if rising_edge(clock) then
|
162 |
|
|
if reset = '1' then
|
163 |
|
|
lut_port_delim_address_reg <= (others => '0');
|
164 |
|
|
elsif register_address = '1' then
|
165 |
|
|
lut_port_delim_address_reg <= SHARED_MEM_LUT_SRC_START & conv_std_logic_Vector(lut_ptr, 13);
|
166 |
|
|
else
|
167 |
|
|
lut_port_delim_address_reg <= lut_port_delim_address_reg;
|
168 |
|
|
end if;
|
169 |
|
|
end if;
|
170 |
|
|
end process;
|
171 |
|
|
|
172 |
|
|
process(clock,ack_i)
|
173 |
|
|
begin
|
174 |
|
|
if rising_edge(clock) then
|
175 |
|
|
if ack_i = '1' then
|
176 |
|
|
dat_i_reg <= dat_i;
|
177 |
|
|
else
|
178 |
|
|
dat_i_reg <= dat_i_reg;
|
179 |
|
|
end if;
|
180 |
|
|
end if;
|
181 |
|
|
end process;
|
182 |
|
|
|
183 |
|
|
process(clock,reset,increment_rd_data,dat_i_reg)
|
184 |
|
|
begin
|
185 |
|
|
if rising_edge(clock) then
|
186 |
|
|
if reset = '1' then
|
187 |
|
|
dat_i_inc_reg <= (others => '0');
|
188 |
|
|
else
|
189 |
|
|
if increment_rd_data = '1' then
|
190 |
|
|
dat_i_inc_reg <= dat_i_reg + 1;
|
191 |
|
|
else
|
192 |
|
|
dat_i_inc_reg <= dat_i_inc_reg;
|
193 |
|
|
end if;
|
194 |
|
|
end if;
|
195 |
|
|
end if;
|
196 |
|
|
end process;
|
197 |
|
|
|
198 |
|
|
snapshot:process(clock,reset,counter_snapshot)
|
199 |
|
|
begin
|
200 |
|
|
if rising_edge(clock) then
|
201 |
|
|
if reset = '1' then
|
202 |
|
|
-- for i in 0 to 6 loop
|
203 |
|
|
frame_counters_reg(0) <= (others => '0');
|
204 |
|
|
frame_counters_reg(1) <= (others => '0');
|
205 |
|
|
frame_counters_reg(2) <= (others => '0');
|
206 |
|
|
frame_counters_reg(3) <= (others => '0');
|
207 |
|
|
frame_counters_reg(4) <= (others => '0');
|
208 |
|
|
frame_counters_reg(5) <= (others => '0');
|
209 |
|
|
frame_counters_reg(6) <= (others => '0');
|
210 |
|
|
frame_counters_reg(7) <= (others => '0');
|
211 |
|
|
-- end loop;
|
212 |
|
|
elsif counter_snapshot = '1' then
|
213 |
|
|
-- for i in 0 to 6 loop
|
214 |
|
|
frame_counters_reg(0) <= frame_counters.count0;
|
215 |
|
|
frame_counters_reg(1) <= frame_counters.count1;
|
216 |
|
|
frame_counters_reg(2) <= frame_counters.count2;
|
217 |
|
|
frame_counters_reg(3) <= frame_counters.count3;
|
218 |
|
|
frame_counters_reg(4) <= frame_counters.count4;
|
219 |
|
|
frame_counters_reg(5) <= frame_counters.count5;
|
220 |
|
|
frame_counters_reg(6) <= frame_counters.count6;
|
221 |
|
|
frame_counters_reg(7) <= frame_counters.count7;
|
222 |
|
|
-- end loop;
|
223 |
|
|
else
|
224 |
|
|
-- for i in 0 to 6 loop
|
225 |
|
|
frame_counters_reg(0) <= frame_counters_reg(0);
|
226 |
|
|
frame_counters_reg(1) <= frame_counters_reg(1);
|
227 |
|
|
frame_counters_reg(2) <= frame_counters_reg(2);
|
228 |
|
|
frame_counters_reg(3) <= frame_counters_reg(3);
|
229 |
|
|
frame_counters_reg(4) <= frame_counters_reg(4);
|
230 |
|
|
frame_counters_reg(5) <= frame_counters_reg(5);
|
231 |
|
|
frame_counters_reg(6) <= frame_counters_reg(6);
|
232 |
|
|
frame_counters_reg(7) <= frame_counters_reg(7);
|
233 |
|
|
-- end loop;
|
234 |
|
|
end if;
|
235 |
|
|
end if;
|
236 |
|
|
end process;
|
237 |
|
|
|
238 |
|
|
update_timer:
|
239 |
|
|
process(clock,reset,update_complete)
|
240 |
|
|
variable counter : integer range 0 to 100000000;
|
241 |
|
|
begin
|
242 |
|
|
if rising_edge(clock) then
|
243 |
|
|
if reset = '1' then
|
244 |
|
|
update_counters <= '1';
|
245 |
|
|
counter := 100000000;
|
246 |
|
|
else
|
247 |
|
|
if update_complete = '1' then
|
248 |
|
|
update_counters <= '0';
|
249 |
|
|
counter := 0;
|
250 |
|
|
elsif counter = 100000000 then
|
251 |
|
|
update_counters <= '1';
|
252 |
|
|
counter := 100000000;
|
253 |
|
|
else
|
254 |
|
|
update_counters <= '0';
|
255 |
|
|
counter := counter + 1;
|
256 |
|
|
end if;
|
257 |
|
|
end if;
|
258 |
|
|
end if;
|
259 |
|
|
end process;
|
260 |
|
|
|
261 |
|
|
process(clock,reset,increment_counter_ptr,update_complete)
|
262 |
|
|
begin
|
263 |
|
|
if rising_Edge(clock) then
|
264 |
|
|
if reset = '1' then
|
265 |
|
|
counter_ptr <= 0;
|
266 |
|
|
else
|
267 |
|
|
if increment_counter_ptr = '1' then
|
268 |
|
|
counter_ptr <= counter_ptr + 1;
|
269 |
|
|
elsif update_complete = '1' then
|
270 |
|
|
counter_ptr <= 0;
|
271 |
|
|
else
|
272 |
|
|
counter_ptr <= counter_ptr;
|
273 |
|
|
end if;
|
274 |
|
|
end if;
|
275 |
|
|
end if;
|
276 |
|
|
end process;
|
277 |
|
|
|
278 |
|
|
nxtstate_log:process(currentstate,fifo_empty,ack_i,lut_info.in_lut,update_counters,counter_ptr,
|
279 |
|
|
fifo_data_out,lut_ptr,lut_info.lut_pointer,dat_i_inc_reg,frame_counters_reg,
|
280 |
|
|
dat_o_reg,lut_port_address_reg,lut_port_delim_address_reg,new_counter_address_reg,
|
281 |
|
|
counter_address_reg,frame_counter_address_reg)
|
282 |
|
|
begin
|
283 |
|
|
case currentstate is
|
284 |
|
|
|
285 |
|
|
when reset_state =>
|
286 |
|
|
nextstate <= idle_0_0;
|
287 |
|
|
cyc_o <= '0';
|
288 |
|
|
stb_o <= '0';
|
289 |
|
|
we_o <= '0';
|
290 |
|
|
adr_o <= (others => '0');
|
291 |
|
|
dat_o <= (others => '0');
|
292 |
|
|
fifo_pop <= '0';
|
293 |
|
|
load_lut <= '0';
|
294 |
|
|
enable_lut_search <= '0';
|
295 |
|
|
increment_rd_data <= '0';
|
296 |
|
|
increment_counter_ptr <= '0';
|
297 |
|
|
update_complete <= '0';
|
298 |
|
|
counter_snapshot <= '0';
|
299 |
|
|
register_address <= '0';
|
300 |
|
|
|
301 |
|
|
when idle_0_0 =>
|
302 |
|
|
nextstate <= idle_0;
|
303 |
|
|
cyc_o <= '1';
|
304 |
|
|
stb_o <= '1';
|
305 |
|
|
we_o <= '1';
|
306 |
|
|
adr_o <= lut_start_address;--SHARED_MEM_LUT_SRC_START & "0000000000000";
|
307 |
|
|
dat_o <= X"12345678";
|
308 |
|
|
fifo_pop <= '0';
|
309 |
|
|
load_lut <= '0';
|
310 |
|
|
enable_lut_search <= '0';
|
311 |
|
|
increment_rd_data <= '0';
|
312 |
|
|
increment_counter_ptr <= '0';
|
313 |
|
|
update_complete <= '0';
|
314 |
|
|
counter_snapshot <= '0';
|
315 |
|
|
register_address <= '0';
|
316 |
|
|
|
317 |
|
|
when idle_0 =>
|
318 |
|
|
if ack_i = '1' then
|
319 |
|
|
nextstate <= idle;
|
320 |
|
|
else
|
321 |
|
|
nextstate <= idle_0;
|
322 |
|
|
end if;
|
323 |
|
|
cyc_o <= '1';
|
324 |
|
|
stb_o <= '1';
|
325 |
|
|
we_o <= '1';
|
326 |
|
|
adr_o <= lut_start_address;--SHARED_MEM_LUT_SRC_START & "0000000000000";--conv_std_logic_vector(active_ptr,13);
|
327 |
|
|
dat_o <= X"12345678";
|
328 |
|
|
fifo_pop <= '0';
|
329 |
|
|
load_lut <= '0';
|
330 |
|
|
enable_lut_search <= '0';
|
331 |
|
|
increment_rd_data <= '0';
|
332 |
|
|
increment_counter_ptr <= '0';
|
333 |
|
|
update_complete <= '0';
|
334 |
|
|
counter_snapshot <= '0';
|
335 |
|
|
register_address <= '0';
|
336 |
|
|
|
337 |
|
|
when idle =>
|
338 |
|
|
if update_counters = '1' then
|
339 |
|
|
nextstate <= update_counters_2_ddr;
|
340 |
|
|
elsif fifo_empty = '0' then
|
341 |
|
|
nextstate <= pop_fifo;--lut_search;
|
342 |
|
|
-- if fifo_empty = '0' then --and update_counters = '0' then
|
343 |
|
|
-- nextstate <= lut_search;
|
344 |
|
|
-- elsif update_counters = '1' then
|
345 |
|
|
-- nextstate <= update_counters_2_ddr;
|
346 |
|
|
else
|
347 |
|
|
nextstate <= idle;
|
348 |
|
|
end if;
|
349 |
|
|
cyc_o <= '0';
|
350 |
|
|
stb_o <= '0';
|
351 |
|
|
we_o <= '0';
|
352 |
|
|
dat_o <= (others => '0');
|
353 |
|
|
adr_o <= (others => '0');
|
354 |
|
|
fifo_pop <= '0';
|
355 |
|
|
load_lut <= '0';
|
356 |
|
|
enable_lut_search <= '0';
|
357 |
|
|
increment_rd_data <= '0';
|
358 |
|
|
increment_counter_ptr <= '0';
|
359 |
|
|
update_complete <= '0';
|
360 |
|
|
counter_snapshot <= '0';
|
361 |
|
|
register_address <= '0';
|
362 |
|
|
|
363 |
|
|
when lut_search =>
|
364 |
|
|
nextstate <= register_ddr_address;--read_lut;
|
365 |
|
|
cyc_o <= '0';
|
366 |
|
|
stb_o <= '0';
|
367 |
|
|
we_o <= '0';
|
368 |
|
|
dat_o <= (others => '0');
|
369 |
|
|
adr_o <= (others => '0');
|
370 |
|
|
fifo_pop <= '0';
|
371 |
|
|
load_lut <= '0';
|
372 |
|
|
enable_lut_search <= '1';
|
373 |
|
|
increment_rd_data <= '0';
|
374 |
|
|
increment_counter_ptr <= '0';
|
375 |
|
|
update_complete <= '0';
|
376 |
|
|
counter_snapshot <= '0';
|
377 |
|
|
register_address <= '0';
|
378 |
|
|
|
379 |
|
|
when register_ddr_address =>
|
380 |
|
|
nextstate <= read_lut;
|
381 |
|
|
cyc_o <= '0';
|
382 |
|
|
stb_o <= '0';
|
383 |
|
|
we_o <= '0';
|
384 |
|
|
dat_o <= (others => '0');
|
385 |
|
|
adr_o <= (others => '0');
|
386 |
|
|
fifo_pop <= '0';
|
387 |
|
|
load_lut <= '0';
|
388 |
|
|
enable_lut_search <= '0';
|
389 |
|
|
increment_rd_data <= '0';
|
390 |
|
|
increment_counter_ptr <= '0';
|
391 |
|
|
update_complete <= '0';
|
392 |
|
|
counter_snapshot <= '0';
|
393 |
|
|
register_address <= '1';
|
394 |
|
|
|
395 |
|
|
when read_lut =>
|
396 |
|
|
if lut_info.in_lut = true then
|
397 |
|
|
nextstate <= read_ddr;
|
398 |
|
|
else
|
399 |
|
|
nextstate <= write_1_to_ddr;--load_lut_value;
|
400 |
|
|
end if;
|
401 |
|
|
cyc_o <= '0';
|
402 |
|
|
stb_o <= '0';
|
403 |
|
|
we_o <= '0';
|
404 |
|
|
dat_o <= (others => '0');
|
405 |
|
|
adr_o <= (others => '0');
|
406 |
|
|
fifo_pop <= '0';
|
407 |
|
|
load_lut <= '0';
|
408 |
|
|
enable_lut_search <= '0';
|
409 |
|
|
increment_rd_data <= '0';
|
410 |
|
|
increment_counter_ptr <= '0';
|
411 |
|
|
update_complete <= '0';
|
412 |
|
|
counter_snapshot <= '0';
|
413 |
|
|
register_address <= '0';
|
414 |
|
|
|
415 |
|
|
when load_lut_value =>
|
416 |
|
|
nextstate <= register_ddr_address_2;--store_lut_2_ddr;--pop_fifo;--write_1_to_ddr;
|
417 |
|
|
cyc_o <= '0';
|
418 |
|
|
stb_o <= '0';
|
419 |
|
|
we_o <= '0';
|
420 |
|
|
dat_o <= (others => '0');
|
421 |
|
|
adr_o <= (others => '0');
|
422 |
|
|
fifo_pop <= '0';
|
423 |
|
|
load_lut <= '1';
|
424 |
|
|
enable_lut_search <= '0';
|
425 |
|
|
increment_rd_data <= '0';
|
426 |
|
|
increment_counter_ptr <= '0';
|
427 |
|
|
update_complete <= '0';
|
428 |
|
|
counter_snapshot <= '0';
|
429 |
|
|
register_address <= '0';
|
430 |
|
|
|
431 |
|
|
when register_ddr_address_2 =>
|
432 |
|
|
nextstate <= store_lut_2_ddr;
|
433 |
|
|
cyc_o <= '0';
|
434 |
|
|
stb_o <= '0';
|
435 |
|
|
we_o <= '0';
|
436 |
|
|
dat_o <= (others => '0');
|
437 |
|
|
adr_o <= (others => '0');
|
438 |
|
|
fifo_pop <= '0';
|
439 |
|
|
load_lut <= '0';
|
440 |
|
|
enable_lut_search <= '0';
|
441 |
|
|
increment_rd_data <= '0';
|
442 |
|
|
increment_counter_ptr <= '0';
|
443 |
|
|
update_complete <= '0';
|
444 |
|
|
counter_snapshot <= '0';
|
445 |
|
|
register_address <= '1';
|
446 |
|
|
|
447 |
|
|
when store_lut_2_ddr =>
|
448 |
|
|
-- if ack_i = '1' then
|
449 |
|
|
-- nextstate <= store_lut_delim;--pop_fifo;
|
450 |
|
|
-- else
|
451 |
|
|
nextstate <= store_lut_2_ddr_0;
|
452 |
|
|
-- end if;
|
453 |
|
|
cyc_o <= '1';
|
454 |
|
|
stb_o <= '1';
|
455 |
|
|
we_o <= '1';
|
456 |
|
|
dat_o <= dat_o_reg;--conv_std_logic_vector(lut_ptr-1,15) & fifo_data_out(16 downto 0);
|
457 |
|
|
adr_o <= lut_port_address_reg;--SHARED_MEM_LUT_SRC_START & conv_std_logic_vector((lut_ptr-1),13);
|
458 |
|
|
fifo_pop <= '0';
|
459 |
|
|
load_lut <= '0';
|
460 |
|
|
enable_lut_search <= '0';
|
461 |
|
|
increment_rd_data <= '0';
|
462 |
|
|
increment_counter_ptr <= '0';
|
463 |
|
|
update_complete <= '0';
|
464 |
|
|
counter_snapshot <= '0';
|
465 |
|
|
register_address <= '0';
|
466 |
|
|
|
467 |
|
|
when store_lut_2_ddr_0 =>
|
468 |
|
|
if ack_i = '1' then
|
469 |
|
|
nextstate <= store_lut_delim_wait;--pop_fifo;
|
470 |
|
|
else
|
471 |
|
|
nextstate <= store_lut_2_ddr_0;
|
472 |
|
|
end if;
|
473 |
|
|
cyc_o <= '1';
|
474 |
|
|
stb_o <= '1';
|
475 |
|
|
we_o <= '1';
|
476 |
|
|
dat_o <= dat_o_reg;--conv_std_logic_vector(lut_ptr-1,15) & fifo_data_out(16 downto 0);
|
477 |
|
|
adr_o <= lut_port_address_reg;--SHARED_MEM_LUT_SRC_START & conv_std_logic_vector((lut_ptr-1),13);
|
478 |
|
|
fifo_pop <= '0';
|
479 |
|
|
load_lut <= '0';
|
480 |
|
|
enable_lut_search <= '0';
|
481 |
|
|
increment_rd_data <= '0';
|
482 |
|
|
increment_counter_ptr <= '0';
|
483 |
|
|
update_complete <= '0';
|
484 |
|
|
counter_snapshot <= '0';
|
485 |
|
|
register_address <= '0';
|
486 |
|
|
|
487 |
|
|
when store_lut_delim_wait =>
|
488 |
|
|
nextstate <= store_lut_delim;
|
489 |
|
|
cyc_o <= '0';
|
490 |
|
|
stb_o <= '0';
|
491 |
|
|
we_o <= '0';
|
492 |
|
|
dat_o <= (others => '0');
|
493 |
|
|
adr_o <= (others => '0');
|
494 |
|
|
fifo_pop <= '0';
|
495 |
|
|
load_lut <= '0';
|
496 |
|
|
enable_lut_search <= '0';
|
497 |
|
|
increment_rd_data <= '0';
|
498 |
|
|
increment_counter_ptr <= '0';
|
499 |
|
|
update_complete <= '0';
|
500 |
|
|
counter_snapshot <= '0';
|
501 |
|
|
register_address <= '0';
|
502 |
|
|
|
503 |
|
|
when store_lut_delim =>
|
504 |
|
|
-- if ack_i = '1' then
|
505 |
|
|
-- nextstate <= pop_fifo;
|
506 |
|
|
-- else
|
507 |
|
|
nextstate <= store_lut_delim_0;
|
508 |
|
|
-- end if;
|
509 |
|
|
cyc_o <= '1';
|
510 |
|
|
stb_o <= '1';
|
511 |
|
|
we_o <= '1';
|
512 |
|
|
dat_o <= X"12345678";
|
513 |
|
|
adr_o <= lut_port_delim_address_reg;--SHARED_MEM_LUT_SRC_START & conv_std_logic_vector((lut_ptr),13);
|
514 |
|
|
fifo_pop <= '0';
|
515 |
|
|
load_lut <= '0';
|
516 |
|
|
enable_lut_search <= '0';
|
517 |
|
|
increment_rd_data <= '0';
|
518 |
|
|
increment_counter_ptr <= '0';
|
519 |
|
|
update_complete <= '0';
|
520 |
|
|
counter_snapshot <= '0';
|
521 |
|
|
register_address <= '0';
|
522 |
|
|
|
523 |
|
|
when store_lut_delim_0 =>
|
524 |
|
|
if ack_i = '1' then
|
525 |
|
|
nextstate <= idle;--pop_fifo;
|
526 |
|
|
else
|
527 |
|
|
nextstate <= store_lut_delim_0;
|
528 |
|
|
end if;
|
529 |
|
|
cyc_o <= '1';
|
530 |
|
|
stb_o <= '1';
|
531 |
|
|
we_o <= '1';
|
532 |
|
|
dat_o <= X"12345678";
|
533 |
|
|
adr_o <= lut_port_delim_address_reg;--SHARED_MEM_LUT_SRC_START & conv_std_logic_vector((lut_ptr),13);
|
534 |
|
|
fifo_pop <= '0';
|
535 |
|
|
load_lut <= '0';
|
536 |
|
|
enable_lut_search <= '0';
|
537 |
|
|
increment_rd_data <= '0';
|
538 |
|
|
increment_counter_ptr <= '0';
|
539 |
|
|
update_complete <= '0';
|
540 |
|
|
counter_snapshot <= '0';
|
541 |
|
|
register_address <= '0';
|
542 |
|
|
|
543 |
|
|
when write_1_to_ddr =>
|
544 |
|
|
-- if ack_i = '1' then
|
545 |
|
|
-- nextstate <= load_lut_value;--pop_fifo;
|
546 |
|
|
-- else
|
547 |
|
|
nextstate <= write_1_to_ddr_0;
|
548 |
|
|
-- end if;
|
549 |
|
|
cyc_o <= '1';
|
550 |
|
|
stb_o <= '1';
|
551 |
|
|
we_o <= '1';
|
552 |
|
|
dat_o <= X"00000001";
|
553 |
|
|
adr_o <= new_counter_address_reg;--SHARED_MEM_PREFIX_SOURCE & conv_std_logic_vector(lut_ptr,13);
|
554 |
|
|
fifo_pop <= '0';
|
555 |
|
|
load_lut <= '0';
|
556 |
|
|
enable_lut_search <= '0';
|
557 |
|
|
increment_rd_data <= '0';
|
558 |
|
|
increment_counter_ptr <= '0';
|
559 |
|
|
update_complete <= '0';
|
560 |
|
|
counter_snapshot <= '0';
|
561 |
|
|
register_address <= '0';
|
562 |
|
|
|
563 |
|
|
when write_1_to_ddr_0 =>
|
564 |
|
|
if ack_i = '1' then
|
565 |
|
|
nextstate <= load_lut_value;--pop_fifo;
|
566 |
|
|
else
|
567 |
|
|
nextstate <= write_1_to_ddr_0;
|
568 |
|
|
end if;
|
569 |
|
|
cyc_o <= '1';
|
570 |
|
|
stb_o <= '1';
|
571 |
|
|
we_o <= '1';
|
572 |
|
|
dat_o <= X"00000001";
|
573 |
|
|
adr_o <= new_counter_address_reg;--SHARED_MEM_PREFIX_SOURCE & conv_std_logic_vector(lut_ptr,13);
|
574 |
|
|
fifo_pop <= '0';
|
575 |
|
|
load_lut <= '0';
|
576 |
|
|
enable_lut_search <= '0';
|
577 |
|
|
increment_rd_data <= '0';
|
578 |
|
|
increment_counter_ptr <= '0';
|
579 |
|
|
update_complete <= '0';
|
580 |
|
|
counter_snapshot <= '0';
|
581 |
|
|
register_address <= '0';
|
582 |
|
|
|
583 |
|
|
|
584 |
|
|
when pop_fifo =>
|
585 |
|
|
nextstate <= pop_fifo_wait;--idle;
|
586 |
|
|
cyc_o <= '0';
|
587 |
|
|
stb_o <= '0';
|
588 |
|
|
we_o <= '0';
|
589 |
|
|
dat_o <= (others => '0');
|
590 |
|
|
adr_o <= (others => '0');
|
591 |
|
|
fifo_pop <= '1';
|
592 |
|
|
load_lut <= '0';
|
593 |
|
|
enable_lut_search <= '0';
|
594 |
|
|
increment_rd_data <= '0';
|
595 |
|
|
increment_counter_ptr <= '0';
|
596 |
|
|
update_complete <= '0';
|
597 |
|
|
counter_snapshot <= '0';
|
598 |
|
|
register_address <= '0';
|
599 |
|
|
|
600 |
|
|
when pop_fifo_wait =>
|
601 |
|
|
nextstate <= lut_search;
|
602 |
|
|
cyc_o <= '0';
|
603 |
|
|
stb_o <= '0';
|
604 |
|
|
we_o <= '0';
|
605 |
|
|
dat_o <= (others => '0');
|
606 |
|
|
adr_o <= (others => '0');
|
607 |
|
|
fifo_pop <= '0';
|
608 |
|
|
load_lut <= '0';
|
609 |
|
|
enable_lut_search <= '0';
|
610 |
|
|
increment_rd_data <= '0';
|
611 |
|
|
increment_counter_ptr <= '0';
|
612 |
|
|
update_complete <= '0';
|
613 |
|
|
counter_snapshot <= '0';
|
614 |
|
|
register_address <= '0';
|
615 |
|
|
when read_ddr =>
|
616 |
|
|
-- if ack_i = '1' then
|
617 |
|
|
-- nextstate <= increment_ddr_read_data;
|
618 |
|
|
-- else
|
619 |
|
|
nextstate <= read_ddr_0;
|
620 |
|
|
-- end if;
|
621 |
|
|
cyc_o <= '1';
|
622 |
|
|
stb_o <= '1';
|
623 |
|
|
we_o <= '0';
|
624 |
|
|
dat_o <= (others => '0');
|
625 |
|
|
adr_o <= counter_address_reg;--SHARED_MEM_PREFIX_SOURCE & conv_std_logic_vector(lut_info.lut_pointer,13);
|
626 |
|
|
fifo_pop <= '0';
|
627 |
|
|
load_lut <= '0';
|
628 |
|
|
enable_lut_search <= '0';
|
629 |
|
|
increment_rd_data <= '0';
|
630 |
|
|
increment_counter_ptr <= '0';
|
631 |
|
|
update_complete <= '0';
|
632 |
|
|
counter_snapshot <= '0';
|
633 |
|
|
register_address <= '0';
|
634 |
|
|
|
635 |
|
|
when read_ddr_0 =>
|
636 |
|
|
if ack_i = '1' then
|
637 |
|
|
nextstate <= increment_ddr_read_data;
|
638 |
|
|
else
|
639 |
|
|
nextstate <= read_ddr_0;
|
640 |
|
|
end if;
|
641 |
|
|
cyc_o <= '1';
|
642 |
|
|
stb_o <= '1';
|
643 |
|
|
we_o <= '0';
|
644 |
|
|
dat_o <= (others => '0');
|
645 |
|
|
adr_o <= counter_address_reg;--SHARED_MEM_PREFIX_SOURCE & conv_std_logic_vector(lut_info.lut_pointer,13);
|
646 |
|
|
fifo_pop <= '0';
|
647 |
|
|
load_lut <= '0';
|
648 |
|
|
enable_lut_search <= '0';
|
649 |
|
|
increment_rd_data <= '0';
|
650 |
|
|
increment_counter_ptr <= '0';
|
651 |
|
|
update_complete <= '0';
|
652 |
|
|
counter_snapshot <= '0';
|
653 |
|
|
register_address <= '0';
|
654 |
|
|
|
655 |
|
|
when increment_ddr_read_data =>
|
656 |
|
|
nextstate <= write_inc_data_2_ddr;
|
657 |
|
|
cyc_o <= '0';
|
658 |
|
|
stb_o <= '0';
|
659 |
|
|
we_o <= '0';
|
660 |
|
|
dat_o <= (others => '0');
|
661 |
|
|
adr_o <= (others => '0');
|
662 |
|
|
fifo_pop <= '0';
|
663 |
|
|
load_lut <= '0';
|
664 |
|
|
enable_lut_search <= '0';
|
665 |
|
|
increment_rd_data <= '1';
|
666 |
|
|
increment_counter_ptr <= '0';
|
667 |
|
|
update_complete <= '0';
|
668 |
|
|
counter_snapshot <= '0';
|
669 |
|
|
register_address <= '0';
|
670 |
|
|
|
671 |
|
|
when write_inc_data_2_ddr =>
|
672 |
|
|
-- if ack_i = '1' then
|
673 |
|
|
-- nextstate <= pop_fifo;
|
674 |
|
|
-- else
|
675 |
|
|
nextstate <= write_inc_data_2_ddr_0;
|
676 |
|
|
-- end if;
|
677 |
|
|
cyc_o <= '1';
|
678 |
|
|
stb_o <= '1';
|
679 |
|
|
we_o <= '1';
|
680 |
|
|
dat_o <= dat_i_inc_reg;--dat_i_reg + 1;--counter_data;
|
681 |
|
|
adr_o <= counter_address_reg;--SHARED_MEM_PREFIX_SOURCE & conv_std_logic_vector(lut_info.lut_pointer,13);
|
682 |
|
|
fifo_pop <= '0';
|
683 |
|
|
load_lut <= '0';
|
684 |
|
|
enable_lut_search <= '0';
|
685 |
|
|
increment_rd_data <= '0';
|
686 |
|
|
increment_counter_ptr <= '0';
|
687 |
|
|
update_complete <= '0';
|
688 |
|
|
counter_snapshot <= '0';
|
689 |
|
|
register_address <= '0';
|
690 |
|
|
|
691 |
|
|
when write_inc_data_2_ddr_0 =>
|
692 |
|
|
if ack_i = '1' then
|
693 |
|
|
nextstate <= idle;--pop_fifo;
|
694 |
|
|
else
|
695 |
|
|
nextstate <= write_inc_data_2_ddr_0;
|
696 |
|
|
end if;
|
697 |
|
|
cyc_o <= '1';
|
698 |
|
|
stb_o <= '1';
|
699 |
|
|
we_o <= '1';
|
700 |
|
|
dat_o <= dat_i_inc_reg;--dat_i_reg + 1;--counter_data;
|
701 |
|
|
adr_o <= counter_address_reg;--SHARED_MEM_PREFIX_SOURCE & conv_std_logic_vector(lut_info.lut_pointer,13);
|
702 |
|
|
fifo_pop <= '0';
|
703 |
|
|
load_lut <= '0';
|
704 |
|
|
enable_lut_search <= '0';
|
705 |
|
|
increment_rd_data <= '0';
|
706 |
|
|
increment_counter_ptr <= '0';
|
707 |
|
|
update_complete <= '0';
|
708 |
|
|
counter_snapshot <= '0';
|
709 |
|
|
register_address <= '0';
|
710 |
|
|
|
711 |
|
|
when update_counters_2_ddr =>
|
712 |
|
|
nextstate <= update_counters_2_ddr_0;
|
713 |
|
|
cyc_o <= '0';
|
714 |
|
|
stb_o <= '0';
|
715 |
|
|
we_o <= '0';
|
716 |
|
|
dat_o <= (others => '0');
|
717 |
|
|
adr_o <= (others => '0');
|
718 |
|
|
fifo_pop <= '0';
|
719 |
|
|
load_lut <= '0';
|
720 |
|
|
enable_lut_search <= '0';
|
721 |
|
|
increment_rd_data <= '0';
|
722 |
|
|
increment_counter_ptr <= '0';
|
723 |
|
|
update_complete <= '0';
|
724 |
|
|
counter_snapshot <= '1';
|
725 |
|
|
register_address <= '0';
|
726 |
|
|
|
727 |
|
|
when update_counters_2_ddr_0 =>
|
728 |
|
|
-- if ack_i = '1' then
|
729 |
|
|
-- nextstate <= check_counter_ptr;--inc_counter_ptr;
|
730 |
|
|
-- else
|
731 |
|
|
nextstate <= update_counters_2_ddr_1;
|
732 |
|
|
-- end if;
|
733 |
|
|
cyc_o <= '1';
|
734 |
|
|
stb_o <= '1';
|
735 |
|
|
we_o <= '1';
|
736 |
|
|
dat_o <= frame_counters_reg(counter_ptr);
|
737 |
|
|
adr_o <= frame_counter_address_reg;--SHARED_MEM_COUNTER_START & conv_std_logic_vector(counter_ptr,13);
|
738 |
|
|
fifo_pop <= '0';
|
739 |
|
|
load_lut <= '0';
|
740 |
|
|
enable_lut_search <= '0';
|
741 |
|
|
increment_rd_data <= '0';
|
742 |
|
|
increment_counter_ptr <= '0';
|
743 |
|
|
update_complete <= '0';
|
744 |
|
|
counter_snapshot <= '0';
|
745 |
|
|
register_address <= '0';
|
746 |
|
|
|
747 |
|
|
when update_counters_2_ddr_1 =>
|
748 |
|
|
if ack_i = '1' then
|
749 |
|
|
nextstate <= check_counter_ptr;--inc_counter_ptr;
|
750 |
|
|
else
|
751 |
|
|
nextstate <= update_counters_2_ddr_1;
|
752 |
|
|
end if;
|
753 |
|
|
cyc_o <= '1';
|
754 |
|
|
stb_o <= '1';
|
755 |
|
|
we_o <= '1';
|
756 |
|
|
dat_o <= frame_counters_reg(counter_ptr);
|
757 |
|
|
adr_o <= frame_counter_address_reg;--SHARED_MEM_COUNTER_START & conv_std_logic_vector(counter_ptr,13);
|
758 |
|
|
fifo_pop <= '0';
|
759 |
|
|
load_lut <= '0';
|
760 |
|
|
enable_lut_search <= '0';
|
761 |
|
|
increment_rd_data <= '0';
|
762 |
|
|
increment_counter_ptr <= '0';
|
763 |
|
|
update_complete <= '0';
|
764 |
|
|
counter_snapshot <= '0';
|
765 |
|
|
register_address <= '0';
|
766 |
|
|
|
767 |
|
|
when check_counter_ptr =>
|
768 |
|
|
if counter_ptr = MAX_NUM_FRAME_COUNTERS-1 then
|
769 |
|
|
nextstate <= completed_update;
|
770 |
|
|
else
|
771 |
|
|
nextstate <= inc_counter_ptr;
|
772 |
|
|
end if;
|
773 |
|
|
cyc_o <= '0';
|
774 |
|
|
stb_o <= '0';
|
775 |
|
|
we_o <= '0';
|
776 |
|
|
dat_o <= (others => '0');
|
777 |
|
|
adr_o <= (others => '0');
|
778 |
|
|
fifo_pop <= '0';
|
779 |
|
|
load_lut <= '0';
|
780 |
|
|
enable_lut_search <='0';
|
781 |
|
|
increment_rd_data <= '0';
|
782 |
|
|
increment_counter_ptr <= '0';
|
783 |
|
|
update_complete <= '0';
|
784 |
|
|
counter_snapshot <= '0';
|
785 |
|
|
register_address <= '0';
|
786 |
|
|
|
787 |
|
|
when inc_counter_ptr =>
|
788 |
|
|
-- if counter_ptr = 6 then
|
789 |
|
|
-- nextstate <= completed_update;
|
790 |
|
|
-- else
|
791 |
|
|
nextstate <= inc_counter_ptr_wait;--update_counters_2_ddr;
|
792 |
|
|
-- end if;
|
793 |
|
|
cyc_o <= '0';
|
794 |
|
|
stb_o <= '0';
|
795 |
|
|
we_o <= '0';
|
796 |
|
|
dat_o <= (others => '0');
|
797 |
|
|
adr_o <= (others => '0');
|
798 |
|
|
fifo_pop <= '0';
|
799 |
|
|
load_lut <= '0';
|
800 |
|
|
enable_lut_search <= '0';
|
801 |
|
|
increment_rd_data <= '0';
|
802 |
|
|
increment_counter_ptr <= '1';
|
803 |
|
|
update_complete <= '0';
|
804 |
|
|
counter_snapshot <= '0';
|
805 |
|
|
register_address <= '0';
|
806 |
|
|
|
807 |
|
|
when inc_counter_ptr_wait =>
|
808 |
|
|
nextstate <= update_counters_2_ddr;
|
809 |
|
|
cyc_o <= '0';
|
810 |
|
|
stb_o <= '0';
|
811 |
|
|
we_o <= '0';
|
812 |
|
|
dat_o <= (others => '0');
|
813 |
|
|
adr_o <= (others => '0');
|
814 |
|
|
fifo_pop <= '0';
|
815 |
|
|
load_lut <= '0';
|
816 |
|
|
enable_lut_search <= '0';
|
817 |
|
|
increment_rd_data <= '0';
|
818 |
|
|
increment_counter_ptr <= '0';
|
819 |
|
|
update_complete <= '0';
|
820 |
|
|
counter_snapshot <= '0';
|
821 |
|
|
register_address <= '0';
|
822 |
|
|
|
823 |
|
|
when completed_update =>
|
824 |
|
|
nextstate <= idle;
|
825 |
|
|
cyc_o <= '0';
|
826 |
|
|
stb_o <= '0';
|
827 |
|
|
we_o <= '0';
|
828 |
|
|
dat_o <= (others => '0');
|
829 |
|
|
adr_o <= (others => '0');
|
830 |
|
|
fifo_pop <= '0';
|
831 |
|
|
load_lut <= '0';
|
832 |
|
|
enable_lut_search <= '0';
|
833 |
|
|
increment_rd_data <= '0';
|
834 |
|
|
increment_counter_ptr <= '0';
|
835 |
|
|
update_complete <= '1';
|
836 |
|
|
counter_snapshot <= '0';
|
837 |
|
|
register_address <= '0';
|
838 |
|
|
|
839 |
|
|
when others =>
|
840 |
|
|
nextstate <= idle;
|
841 |
|
|
cyc_o <= '0';
|
842 |
|
|
stb_o <= '0';
|
843 |
|
|
we_o <= '0';
|
844 |
|
|
dat_o <= (others => '0');
|
845 |
|
|
adr_o <= (others => '0');
|
846 |
|
|
fifo_pop <= '0';
|
847 |
|
|
load_lut <= '0';
|
848 |
|
|
enable_lut_search <= '0';
|
849 |
|
|
increment_rd_data <= '0';
|
850 |
|
|
increment_counter_ptr <= '0';
|
851 |
|
|
update_complete <= '0';
|
852 |
|
|
counter_snapshot <= '0';
|
853 |
|
|
register_address <= '0';
|
854 |
|
|
end case;
|
855 |
|
|
end process;
|
856 |
|
|
|
857 |
|
|
curstate_log:process(clock,reset,nextstate)
|
858 |
|
|
begin
|
859 |
|
|
if (clock'event AND clock = '1') then
|
860 |
|
|
if reset = '1' then
|
861 |
|
|
currentstate <= reset_state;
|
862 |
|
|
else
|
863 |
|
|
currentstate <= nextstate;
|
864 |
|
|
end if;
|
865 |
|
|
|
866 |
|
|
end if;
|
867 |
|
|
end process;
|
868 |
|
|
|
869 |
|
|
end Behavioral;
|
870 |
|
|
|