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[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [Address Generation/] [RDIC/] [Arbitration_Path.vhd] - Blame information for rev 21

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----------------------------------------------------------------------------------
--
--  This file is a part of Technica Corporation Wizardry Project
--
--  Copyright (C) 2004-2009, Technica Corporation  
--
--  This program is free software: you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation, either version 3 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Module Name: Arbitration_Path - Behavioral 
-- Project Name: Wizardry
-- Target Devices: Virtex 4 ML401
-- Description: Behavioral description for memory access arbitration scheme.
-- Revision: 1.0
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.MAC_Constants.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity Arbitration_Path is
    Port ( clock : in  STD_LOGIC;
           reset : in  STD_LOGIC;
                          FIFO_full : in  STD_LOGIC;
                          FIFO_empty : in std_logic;
--                        burst_full : in std_logic_vector(num_of_ports downto 0);
                          read_request : in std_logic_vector(num_of_ports downto 0);
                          write_request : in std_logic_vector(num_of_ports downto 0);
--                        burst_empty : in std_logic_vector(num_of_ports downto 0);
                          priority_signals : in priority_type;
--           Memory_Access_out : out  Memory_Access_Port_out;
                          read_acknowledge : in std_logic_vector(num_of_ports downto 0);
                          read_enable_in : out  std_logic_vector(num_of_ports downto 0);
                          write_enable_in : out  std_logic_vector(num_of_ports downto 0)
                          );
end Arbitration_Path;
 
architecture Behavioral of Arbitration_Path is
 
 
type StateType is (reset_state, idle_0, idle_1, idle_2, idle_3,
                access_requested, access_requested_check,
                inc_counter, increment_index_i, check_request_vector,
                increment_index_j,check_priority, check_access_type,
                check_access_type_1,check_access_type_2,check_access_type_3,
                grant_write_access_1,
                pre_inc_index_j, check_request_vector_0,
                grant_write_access, grant_read_access,
                check_index_j, pre_clear_index_j,
                increment_index_i_0, increment_access_count, check_i_j,
                clear_j, increment_req_index_i
 
 
                        );
signal CurrentState,NextState: StateType;
signal request, read_flag_a : std_logic_vector(num_of_ports downto 0);
signal access_count : std_logic_vector(7 downto 0);
signal index_i : integer range 0 to 7;
signal index_j : integer range 0 to num_of_ports;
signal read_access_out,write_access_out : std_logic_vector(num_of_ports downto 0);
signal inc_count, inc_index_i, inc_index_j, read_enable,write_enable,
clear_index_i,clear_index_j : std_logic;
 
begin
 
Generate_Access_Signals : process(clock,write_request,read_request)--,read_flag_a)
--variable : integer range (0 to num_of_ports-1);
begin
        for i in 0 to (num_of_ports) loop
                request(i) <= write_request(i) OR (read_request(i));-- AND ( read_flag_a(i)) );
        end loop;
end process;
 
--toggle_read : process(clock,reset)
--variable flag : std_logic;
--begin
--      if clock='1' and clock'event then
--      if reset='1' then 
--                      read_flag_a <= "111111111";
--              else
--                      for i in 0 to (num_of_ports) loop
--                      flag := read_acknowledge(i) XOR read_access_out(i);
--                              if(flag = '1') then
--                                      read_flag_a(i) <= not read_flag_a(i);
--                              else
--                                      read_flag_a(i) <= read_flag_a(i);
--                              end if;
--                      end loop;
--              end if;
--      end if;
--end process;
 
 
access_counter : process (clock)
begin
   if clock='1' and clock'event then
      if reset='1' then
         access_count <= (others => '0');
      elsif inc_count = '1' then
         access_count <= access_count + 1;
      end if;
   end if;
end process;
 
Index_i_counter : process (clock)
begin
   if clock='1' and clock'event then
      if reset='1' then
         index_i <= 0;
      elsif inc_index_i = '1' then
         index_i <= index_i + 1;
                elsif clear_index_i = '1' then
                        index_i <= 0;
      end if;
   end if;
end process;
 
Index_j_counter : process (clock)
begin
   if clock='1' and clock'event then
      if reset='1' then
         index_j <= 0;
      elsif inc_index_j = '1' then
         index_j <= index_j + 1;
                elsif clear_index_j = '1' then
                        index_j <= 0;
      end if;
   end if;
end process;
 
set_access_outputs : process (clock,reset,read_enable,write_enable,read_access_out,write_access_out)
--variable read_access_out,write_access_out : std_logic_vector(num_of_ports -1 downto 0);
begin
   if clock='1' and clock'event then
      if reset='1' then
         read_access_out <= "000000000";
                        write_access_out <= "000000000";
      elsif read_enable = '1' then
         read_access_out(index_j) <=  '1';
                        write_access_out <= "000000000";
                elsif write_enable = '1' then
         write_access_out(index_j) <=  '1';
                        read_access_out <= "000000000";
                else
                        read_access_out <= "000000000";
                        write_access_out <= "000000000";
      end if;
   end if;
        read_enable_in <= read_access_out;
        write_enable_in <= write_access_out;
end process;
 
--set_access_outputs : process (clock,reset,read_enable,write_enable) 
--variable read_access_out,write_access_out : std_logic_vector(num_of_ports -1 downto 0);
--begin
--   if clock='1' and clock'event then
--      if reset='1' then 
--         read_access_out := "00000000";
--                      write_access_out := "00000000";
--      elsif read_enable = '1' then
--         read_access_out(index_j) :=  '1';
--                      write_access_out := "00000000";
--              elsif write_enable = '1' then
--         write_access_out(index_j) :=  '1';
--                      read_access_out := "00000000";
--              else
--                      read_access_out := "00000000";
--                      write_access_out := "00000000";
--      end if;
--   end if;
--      read_enable_in <= read_access_out;
--      write_enable_in <= write_access_out;
--end process;
 
--set_write_acknowledge_outputs : process (clock,reset,write_enable) 
--variable ack_write_out : std_logic_vector(num_of_ports downto 0);
--begin
--   if clock='1' and clock'event then
--      if reset='1' then 
--         ack_write_out := "000000000";
--              elsif write_enable = '1' then
--         ack_write_out(index_j) :=  '1';
--              else
--                      ack_write_out := "000000000";
--      end if;
--   end if;
--      Memory_Access_out.ack_o <= ack_write_out;
--end process;
 
 
--access_vector : process (clock) 
----variable cnt : std_logic_vector(5 downto 0);
--begin
--      if reset='1' then 
--         access_count <= (others => '0');
--      elsif inc_count = '1' then
--         access_count <= access_count + 1;
--      end if;
--   end if;
--end process;
 
 
arbitration_algorithm: process(CurrentState,request,index_j,index_i,access_count,FIFO_full,FIFO_empty,read_request,write_request,priority_signals)--,Memory_access_in)
 
   begin
                case (CurrentState) is
                        when reset_state =>
                                                NextState <= idle_0;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
                        when idle_0 =>
                                                NextState <= idle_1;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
                        when idle_1 =>
                                                NextState <= idle_2;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
                        when idle_2 =>
                                                NextState <= idle_3;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
                        when idle_3 =>
                                if(request = "00000000") then
                                                NextState <= inc_counter;
                                else
                                                NextState <= access_requested;
                                end if;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
                        when inc_counter =>
                                                NextState <= idle_0;
                                inc_count <= '1';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
------------------------------------------------------------------------------------
-- Access Counter Loop
 
                        when access_requested =>
                                                NextState <= access_requested_check;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
                        when access_requested_check =>
                        if(access_count(index_i) = '0') then
                                                NextState <= increment_index_i;
                        else
                                                NextState <= check_request_vector;
                        end if;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
                        when increment_index_i =>
                        if(index_i = 7) then
                                                NextState <= increment_access_count;
                        else
                                                NextState <= increment_index_i_0;
                        end if;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
 
                        when increment_index_i_0 =>
                                                NextState <= access_requested_check;
                                inc_count <= '0';
                                inc_index_i <= '1';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
-------------------------------------------------------------------------------------
--  Request Vector Loop
 
                        when check_request_vector =>
--                      if(index_j = 7 AND index_i = 7) then
--                                              NextState <= increment_access_count;
--                      elsif(index_j = 7) then
--                                              NextState <= pre_clear_index_j;
--                      else
                                                NextState <= check_request_vector_0;
--                      end if;         
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
                        when pre_clear_index_j =>
                                                NextState <= access_requested;
                                inc_count <= '0';
                                inc_index_i <= '1';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '1';
                                read_enable <= '0';
                                write_enable <= '0';
 
 
                        when check_request_vector_0 =>
                        if((request(index_j) = '0') AND (index_j = num_of_ports)) then
                                                NextState <= increment_access_count;
                        elsif(request(index_j) = '0') then
                                                NextState <= increment_index_j;
                        else
                                                NextState <= check_priority;
                        end if;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
                        when increment_index_j =>
                                                NextState <= check_request_vector;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '1';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
-------------------------------------------------------------------------------------
--  Check Priority
 
                        when check_priority =>
                        if(priority_signals(index_j)(index_i) = '1') then
                                                NextState <= check_access_type;
                        else
                                                NextState <= check_index_j;
                        end if;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
                        when check_index_j =>
                        if(index_j = num_of_ports AND index_i = 7) then
                                                NextState <= increment_access_count;
                        elsif(index_j = num_of_ports) then
                                                NextState <= pre_clear_index_j;
                        else
                                                NextState <= pre_inc_index_j;
                        end if;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
                        when pre_inc_index_j =>
                                                NextState <= check_request_vector;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '1';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
 
 
----------------------------------------------------------------------------------------
--  Check Access Type
 
                        when check_access_type =>
                                                NextState <= check_access_type_1;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
 
 
                when check_access_type_1 =>
                                                NextState <= check_access_type_2;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
                        when check_access_type_2 =>
                                                NextState <= check_access_type_3;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
 
 
 
                        when check_access_type_3 =>
                        if(FIFO_full = '1') then
                                                NextState <= check_access_type_3;
                        elsif(write_request(index_j) = '1') then
                                                NextState <= grant_write_access;
                        else
                                                NextState <= grant_read_access;
                        end if;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
----------------------------------------------------------------------------------------
--  Grant Access
 
--                      when grant_write_access =>
--                              if(FIFO_empty = '1' AND burst_full(index_j) = '1') then
--                                              NextState <= grant_write_access_1;
--                              else
--                                              NextState <= grant_write_access;
--                              end if;
--                              inc_count <= '0';
--                              inc_index_i <= '0';
--                              inc_index_j <= '0';
--                              clear_index_i <= '0';
--                              clear_index_j <= '0';
--                              read_enable <= '0';
--                              write_enable <= '0';
 
                        when grant_write_access =>
                                if(FIFO_empty = '1') then
                                                NextState <= grant_write_access_1;
                                else
                                                NextState <= grant_write_access;
                                end if;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
                        when grant_write_access_1 =>
                                                NextState <= check_i_j;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '1';
 
 
                        when grant_read_access =>
                                                NextState <= check_i_j;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '1';
                                write_enable <= '0';
 
                        when check_i_j =>
                        if(index_i = 7 AND index_j = num_of_ports) then
                                                NextState <= increment_access_count;
                        elsif(index_j = num_of_ports) then
                                                NextState <= clear_j;
                        else
                                                NextState <= increment_req_index_i;
                        end if;
 
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
 
                        when increment_req_index_i =>
                                                NextState <= access_requested;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '1';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
 
 
                        when clear_j =>
                                                NextState <= access_requested;
                                inc_count <= '0';
                                inc_index_i <= '1';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '1';
                                read_enable <= '0';
                                write_enable <= '0';
 
 
 
                        when increment_access_count =>
                                                NextState <= reset_state;
                                inc_count <= '1';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '1';
                                clear_index_j <= '1';
                                read_enable <= '0';
                                write_enable <= '0';
 
 
                        when others =>
                                                NextState <= reset_state;
                                inc_count <= '0';
                                inc_index_i <= '0';
                                inc_index_j <= '0';
                                clear_index_i <= '0';
                                clear_index_j <= '0';
                                read_enable <= '0';
                                write_enable <= '0';
                        end case;
        end process Arbitration_algorithm;
 
        nextstatelogic: process
        begin
                        wait until clock'EVENT and clock = '1'; --WAIT FOR RISING EDGE
                        -- INITIALIZATION
                        if (Reset = '1') then
                                CurrentState <= reset_state;
                        else
                                CurrentState <= NextState;
                        end if;
end process nextstatelogic;
end Behavioral;
 
 
 
--                      when access_requested_check =>
--                      if((request(index_i) = '1')  AND Memory_Access_in.priority_i(index_j)(index_k) = access_count(index_i)) then
--                                              NextState <= idle_0;
--                      else
--                                              NextState <= idle_0;
--                      end if;
--                                              
--                              inc_count <= '1';

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Subversion Repositories the_wizardry_project

[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [Address Generation/] [RDIC/] [Arbitration_Path.vhd] - Blame information for rev 21

Line No.	Rev	Author	Line
1	21	mcwaccent	`----------------------------------------------------------------------------------`
2			`--`
3			`-- This file is a part of Technica Corporation Wizardry Project`
4			`--`
5			`-- Copyright (C) 2004-2009, Technica Corporation`
6			`--`
7			`-- This program is free software: you can redistribute it and/or modify`
8			`-- it under the terms of the GNU General Public License as published by`
9			`-- the Free Software Foundation, either version 3 of the License, or`
10			`-- (at your option) any later version.`
11			`--`
12			`-- This program is distributed in the hope that it will be useful,`
13			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
15			`-- GNU General Public License for more details.`
16			`--`
17			`-- You should have received a copy of the GNU General Public License`
18			`-- along with this program. If not, see <http://www.gnu.org/licenses/>.`
19			`--`
20			`----------------------------------------------------------------------------------`
21			`----------------------------------------------------------------------------------`
22			`-- Module Name: Arbitration_Path - Behavioral`
23			`-- Project Name: Wizardry`
24			`-- Target Devices: Virtex 4 ML401`
25			`-- Description: Behavioral description for memory access arbitration scheme.`
26			`-- Revision: 1.0`
27			`-- Additional Comments:`
28			`--`
29			`----------------------------------------------------------------------------------`
30			`library IEEE;`
31			`use IEEE.STD_LOGIC_1164.ALL;`
32			`use IEEE.STD_LOGIC_ARITH.ALL;`
33			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
34			`use work.MAC_Constants.all;`
35
36			`---- Uncomment the following library declaration if instantiating`
37			`---- any Xilinx primitives in this code.`
38			`--library UNISIM;`
39			`--use UNISIM.VComponents.all;`
40
41			`entity Arbitration_Path is`
42			`Port ( clock : in STD_LOGIC;`
43			`reset : in STD_LOGIC;`
44			`FIFO_full : in STD_LOGIC;`
45			`FIFO_empty : in std_logic;`
46			`-- burst_full : in std_logic_vector(num_of_ports downto 0);`
47			`read_request : in std_logic_vector(num_of_ports downto 0);`
48			`write_request : in std_logic_vector(num_of_ports downto 0);`
49			`-- burst_empty : in std_logic_vector(num_of_ports downto 0);`
50			`priority_signals : in priority_type;`
51			`-- Memory_Access_out : out Memory_Access_Port_out;`
52			`read_acknowledge : in std_logic_vector(num_of_ports downto 0);`
53			`read_enable_in : out std_logic_vector(num_of_ports downto 0);`
54			`write_enable_in : out std_logic_vector(num_of_ports downto 0)`
55			`);`
56			`end Arbitration_Path;`
57
58			`architecture Behavioral of Arbitration_Path is`
59
60
61			`type StateType is (reset_state, idle_0, idle_1, idle_2, idle_3,`
62			`access_requested, access_requested_check,`
63			`inc_counter, increment_index_i, check_request_vector,`
64			`increment_index_j,check_priority, check_access_type,`
65			`check_access_type_1,check_access_type_2,check_access_type_3,`
66			`grant_write_access_1,`
67			`pre_inc_index_j, check_request_vector_0,`
68			`grant_write_access, grant_read_access,`
69			`check_index_j, pre_clear_index_j,`
70			`increment_index_i_0, increment_access_count, check_i_j,`
71			`clear_j, increment_req_index_i`
72
73
74			`);`
75			`signal CurrentState,NextState: StateType;`
76			`signal request, read_flag_a : std_logic_vector(num_of_ports downto 0);`
77			`signal access_count : std_logic_vector(7 downto 0);`
78			`signal index_i : integer range 0 to 7;`
79			`signal index_j : integer range 0 to num_of_ports;`
80			`signal read_access_out,write_access_out : std_logic_vector(num_of_ports downto 0);`
81			`signal inc_count, inc_index_i, inc_index_j, read_enable,write_enable,`
82			`clear_index_i,clear_index_j : std_logic;`
83
84			`begin`
85
86			`Generate_Access_Signals : process(clock,write_request,read_request)--,read_flag_a)`
87			`--variable : integer range (0 to num_of_ports-1);`
88			`begin`
89			`for i in 0 to (num_of_ports) loop`
90			`request(i) <= write_request(i) OR (read_request(i));-- AND ( read_flag_a(i)) );`
91			`end loop;`
92			`end process;`
93
94			`--toggle_read : process(clock,reset)`
95			`--variable flag : std_logic;`
96			`--begin`
97			`-- if clock='1' and clock'event then`
98			`-- if reset='1' then`
99			`-- read_flag_a <= "111111111";`
100			`-- else`
101			`-- for i in 0 to (num_of_ports) loop`
102			`-- flag := read_acknowledge(i) XOR read_access_out(i);`
103			`-- if(flag = '1') then`
104			`-- read_flag_a(i) <= not read_flag_a(i);`
105			`-- else`
106			`-- read_flag_a(i) <= read_flag_a(i);`
107			`-- end if;`
108			`-- end loop;`
109			`-- end if;`
110			`-- end if;`
111			`--end process;`
112
113
114			`access_counter : process (clock)`
115			`begin`
116			`if clock='1' and clock'event then`
117			`if reset='1' then`
118			`access_count <= (others => '0');`
119			`elsif inc_count = '1' then`
120			`access_count <= access_count + 1;`
121			`end if;`
122			`end if;`
123			`end process;`
124
125			`Index_i_counter : process (clock)`
126			`begin`
127			`if clock='1' and clock'event then`
128			`if reset='1' then`
129			`index_i <= 0;`
130			`elsif inc_index_i = '1' then`
131			`index_i <= index_i + 1;`
132			`elsif clear_index_i = '1' then`
133			`index_i <= 0;`
134			`end if;`
135			`end if;`
136			`end process;`
137
138			`Index_j_counter : process (clock)`
139			`begin`
140			`if clock='1' and clock'event then`
141			`if reset='1' then`
142			`index_j <= 0;`
143			`elsif inc_index_j = '1' then`
144			`index_j <= index_j + 1;`
145			`elsif clear_index_j = '1' then`
146			`index_j <= 0;`
147			`end if;`
148			`end if;`
149			`end process;`
150
151			`set_access_outputs : process (clock,reset,read_enable,write_enable,read_access_out,write_access_out)`
152			`--variable read_access_out,write_access_out : std_logic_vector(num_of_ports -1 downto 0);`
153			`begin`
154			`if clock='1' and clock'event then`
155			`if reset='1' then`
156			`read_access_out <= "000000000";`
157			`write_access_out <= "000000000";`
158			`elsif read_enable = '1' then`
159			`read_access_out(index_j) <= '1';`
160			`write_access_out <= "000000000";`
161			`elsif write_enable = '1' then`
162			`write_access_out(index_j) <= '1';`
163			`read_access_out <= "000000000";`
164			`else`
165			`read_access_out <= "000000000";`
166			`write_access_out <= "000000000";`
167			`end if;`
168			`end if;`
169			`read_enable_in <= read_access_out;`
170			`write_enable_in <= write_access_out;`
171			`end process;`
172
173			`--set_access_outputs : process (clock,reset,read_enable,write_enable)`
174			`--variable read_access_out,write_access_out : std_logic_vector(num_of_ports -1 downto 0);`
175			`--begin`
176			`-- if clock='1' and clock'event then`
177			`-- if reset='1' then`
178			`-- read_access_out := "00000000";`
179			`-- write_access_out := "00000000";`
180			`-- elsif read_enable = '1' then`
181			`-- read_access_out(index_j) := '1';`
182			`-- write_access_out := "00000000";`
183			`-- elsif write_enable = '1' then`
184			`-- write_access_out(index_j) := '1';`
185			`-- read_access_out := "00000000";`
186			`-- else`
187			`-- read_access_out := "00000000";`
188			`-- write_access_out := "00000000";`
189			`-- end if;`
190			`-- end if;`
191			`-- read_enable_in <= read_access_out;`
192			`-- write_enable_in <= write_access_out;`
193			`--end process;`
194
195			`--set_write_acknowledge_outputs : process (clock,reset,write_enable)`
196			`--variable ack_write_out : std_logic_vector(num_of_ports downto 0);`
197			`--begin`
198			`-- if clock='1' and clock'event then`
199			`-- if reset='1' then`
200			`-- ack_write_out := "000000000";`
201			`-- elsif write_enable = '1' then`
202			`-- ack_write_out(index_j) := '1';`
203			`-- else`
204			`-- ack_write_out := "000000000";`
205			`-- end if;`
206			`-- end if;`
207			`-- Memory_Access_out.ack_o <= ack_write_out;`
208			`--end process;`
209
210
211			`--access_vector : process (clock)`
212			`----variable cnt : std_logic_vector(5 downto 0);`
213			`--begin`
214			`-- if reset='1' then`
215			`-- access_count <= (others => '0');`
216			`-- elsif inc_count = '1' then`
217			`-- access_count <= access_count + 1;`
218			`-- end if;`
219			`-- end if;`
220			`--end process;`
221
222
223			`arbitration_algorithm: process(CurrentState,request,index_j,index_i,access_count,FIFO_full,FIFO_empty,read_request,write_request,priority_signals)--,Memory_access_in)`
224
225			`begin`
226			`case (CurrentState) is`
227			`when reset_state =>`
228			`NextState <= idle_0;`
229			`inc_count <= '0';`
230			`inc_index_i <= '0';`
231			`inc_index_j <= '0';`
232			`clear_index_i <= '0';`
233			`clear_index_j <= '0';`
234			`read_enable <= '0';`
235			`write_enable <= '0';`
236
237			`when idle_0 =>`
238			`NextState <= idle_1;`
239			`inc_count <= '0';`
240			`inc_index_i <= '0';`
241			`inc_index_j <= '0';`
242			`clear_index_i <= '0';`
243			`clear_index_j <= '0';`
244			`read_enable <= '0';`
245			`write_enable <= '0';`
246
247			`when idle_1 =>`
248			`NextState <= idle_2;`
249			`inc_count <= '0';`
250			`inc_index_i <= '0';`
251			`inc_index_j <= '0';`
252			`clear_index_i <= '0';`
253			`clear_index_j <= '0';`
254			`read_enable <= '0';`
255			`write_enable <= '0';`
256
257			`when idle_2 =>`
258			`NextState <= idle_3;`
259			`inc_count <= '0';`
260			`inc_index_i <= '0';`
261			`inc_index_j <= '0';`
262			`clear_index_i <= '0';`
263			`clear_index_j <= '0';`
264			`read_enable <= '0';`
265			`write_enable <= '0';`
266
267			`when idle_3 =>`
268			`if(request = "00000000") then`
269			`NextState <= inc_counter;`
270			`else`
271			`NextState <= access_requested;`
272			`end if;`
273			`inc_count <= '0';`
274			`inc_index_i <= '0';`
275			`inc_index_j <= '0';`
276			`clear_index_i <= '0';`
277			`clear_index_j <= '0';`
278			`read_enable <= '0';`
279			`write_enable <= '0';`
280
281			`when inc_counter =>`
282			`NextState <= idle_0;`
283			`inc_count <= '1';`
284			`inc_index_i <= '0';`
285			`inc_index_j <= '0';`
286			`clear_index_i <= '0';`
287			`clear_index_j <= '0';`
288			`read_enable <= '0';`
289			`write_enable <= '0';`
290
291			`------------------------------------------------------------------------------------`
292			`-- Access Counter Loop`
293
294			`when access_requested =>`
295			`NextState <= access_requested_check;`
296			`inc_count <= '0';`
297			`inc_index_i <= '0';`
298			`inc_index_j <= '0';`
299			`clear_index_i <= '0';`
300			`clear_index_j <= '0';`
301			`read_enable <= '0';`
302			`write_enable <= '0';`
303
304			`when access_requested_check =>`
305			`if(access_count(index_i) = '0') then`
306			`NextState <= increment_index_i;`
307			`else`
308			`NextState <= check_request_vector;`
309			`end if;`
310			`inc_count <= '0';`
311			`inc_index_i <= '0';`
312			`inc_index_j <= '0';`
313			`clear_index_i <= '0';`
314			`clear_index_j <= '0';`
315			`read_enable <= '0';`
316			`write_enable <= '0';`
317
318			`when increment_index_i =>`
319			`if(index_i = 7) then`
320			`NextState <= increment_access_count;`
321			`else`
322			`NextState <= increment_index_i_0;`
323			`end if;`
324			`inc_count <= '0';`
325			`inc_index_i <= '0';`
326			`inc_index_j <= '0';`
327			`clear_index_i <= '0';`
328			`clear_index_j <= '0';`
329			`read_enable <= '0';`
330			`write_enable <= '0';`
331
332
333			`when increment_index_i_0 =>`
334			`NextState <= access_requested_check;`
335			`inc_count <= '0';`
336			`inc_index_i <= '1';`
337			`inc_index_j <= '0';`
338			`clear_index_i <= '0';`
339			`clear_index_j <= '0';`
340			`read_enable <= '0';`
341			`write_enable <= '0';`
342
343			`-------------------------------------------------------------------------------------`
344			`-- Request Vector Loop`
345
346			`when check_request_vector =>`
347			`-- if(index_j = 7 AND index_i = 7) then`
348			`-- NextState <= increment_access_count;`
349			`-- elsif(index_j = 7) then`
350			`-- NextState <= pre_clear_index_j;`
351			`-- else`
352			`NextState <= check_request_vector_0;`
353			`-- end if;`
354			`inc_count <= '0';`
355			`inc_index_i <= '0';`
356			`inc_index_j <= '0';`
357			`clear_index_i <= '0';`
358			`clear_index_j <= '0';`
359			`read_enable <= '0';`
360			`write_enable <= '0';`
361
362			`when pre_clear_index_j =>`
363			`NextState <= access_requested;`
364			`inc_count <= '0';`
365			`inc_index_i <= '1';`
366			`inc_index_j <= '0';`
367			`clear_index_i <= '0';`
368			`clear_index_j <= '1';`
369			`read_enable <= '0';`
370			`write_enable <= '0';`
371
372
373			`when check_request_vector_0 =>`
374			`if((request(index_j) = '0') AND (index_j = num_of_ports)) then`
375			`NextState <= increment_access_count;`
376			`elsif(request(index_j) = '0') then`
377			`NextState <= increment_index_j;`
378			`else`
379			`NextState <= check_priority;`
380			`end if;`
381			`inc_count <= '0';`
382			`inc_index_i <= '0';`
383			`inc_index_j <= '0';`
384			`clear_index_i <= '0';`
385			`clear_index_j <= '0';`
386			`read_enable <= '0';`
387			`write_enable <= '0';`
388
389			`when increment_index_j =>`
390			`NextState <= check_request_vector;`
391			`inc_count <= '0';`
392			`inc_index_i <= '0';`
393			`inc_index_j <= '1';`
394			`clear_index_i <= '0';`
395			`clear_index_j <= '0';`
396			`read_enable <= '0';`
397			`write_enable <= '0';`
398
399			`-------------------------------------------------------------------------------------`
400			`-- Check Priority`
401
402			`when check_priority =>`
403			`if(priority_signals(index_j)(index_i) = '1') then`
404			`NextState <= check_access_type;`
405			`else`
406			`NextState <= check_index_j;`
407			`end if;`
408			`inc_count <= '0';`
409			`inc_index_i <= '0';`
410			`inc_index_j <= '0';`
411			`clear_index_i <= '0';`
412			`clear_index_j <= '0';`
413			`read_enable <= '0';`
414			`write_enable <= '0';`
415
416			`when check_index_j =>`
417			`if(index_j = num_of_ports AND index_i = 7) then`
418			`NextState <= increment_access_count;`
419			`elsif(index_j = num_of_ports) then`
420			`NextState <= pre_clear_index_j;`
421			`else`
422			`NextState <= pre_inc_index_j;`
423			`end if;`
424			`inc_count <= '0';`
425			`inc_index_i <= '0';`
426			`inc_index_j <= '0';`
427			`clear_index_i <= '0';`
428			`clear_index_j <= '0';`
429			`read_enable <= '0';`
430			`write_enable <= '0';`
431
432			`when pre_inc_index_j =>`
433			`NextState <= check_request_vector;`
434			`inc_count <= '0';`
435			`inc_index_i <= '0';`
436			`inc_index_j <= '1';`
437			`clear_index_i <= '0';`
438			`clear_index_j <= '0';`
439			`read_enable <= '0';`
440			`write_enable <= '0';`
441
442
443
444			`----------------------------------------------------------------------------------------`
445			`-- Check Access Type`
446
447			`when check_access_type =>`
448			`NextState <= check_access_type_1;`
449			`inc_count <= '0';`
450			`inc_index_i <= '0';`
451			`inc_index_j <= '0';`
452			`clear_index_i <= '0';`
453			`clear_index_j <= '0';`
454			`read_enable <= '0';`
455			`write_enable <= '0';`
456
457
458
459			`when check_access_type_1 =>`
460			`NextState <= check_access_type_2;`
461			`inc_count <= '0';`
462			`inc_index_i <= '0';`
463			`inc_index_j <= '0';`
464			`clear_index_i <= '0';`
465			`clear_index_j <= '0';`
466			`read_enable <= '0';`
467			`write_enable <= '0';`
468
469			`when check_access_type_2 =>`
470			`NextState <= check_access_type_3;`
471			`inc_count <= '0';`
472			`inc_index_i <= '0';`
473			`inc_index_j <= '0';`
474			`clear_index_i <= '0';`
475			`clear_index_j <= '0';`
476			`read_enable <= '0';`
477			`write_enable <= '0';`
478
479
480
481
482			`when check_access_type_3 =>`
483			`if(FIFO_full = '1') then`
484			`NextState <= check_access_type_3;`
485			`elsif(write_request(index_j) = '1') then`
486			`NextState <= grant_write_access;`
487			`else`
488			`NextState <= grant_read_access;`
489			`end if;`
490			`inc_count <= '0';`
491			`inc_index_i <= '0';`
492			`inc_index_j <= '0';`
493			`clear_index_i <= '0';`
494			`clear_index_j <= '0';`
495			`read_enable <= '0';`
496			`write_enable <= '0';`
497
498			`----------------------------------------------------------------------------------------`
499			`-- Grant Access`
500
501			`-- when grant_write_access =>`
502			`-- if(FIFO_empty = '1' AND burst_full(index_j) = '1') then`
503			`-- NextState <= grant_write_access_1;`
504			`-- else`
505			`-- NextState <= grant_write_access;`
506			`-- end if;`
507			`-- inc_count <= '0';`
508			`-- inc_index_i <= '0';`
509			`-- inc_index_j <= '0';`
510			`-- clear_index_i <= '0';`
511			`-- clear_index_j <= '0';`
512			`-- read_enable <= '0';`
513			`-- write_enable <= '0';`
514
515			`when grant_write_access =>`
516			`if(FIFO_empty = '1') then`
517			`NextState <= grant_write_access_1;`
518			`else`
519			`NextState <= grant_write_access;`
520			`end if;`
521			`inc_count <= '0';`
522			`inc_index_i <= '0';`
523			`inc_index_j <= '0';`
524			`clear_index_i <= '0';`
525			`clear_index_j <= '0';`
526			`read_enable <= '0';`
527			`write_enable <= '0';`
528
529			`when grant_write_access_1 =>`
530			`NextState <= check_i_j;`
531			`inc_count <= '0';`
532			`inc_index_i <= '0';`
533			`inc_index_j <= '0';`
534			`clear_index_i <= '0';`
535			`clear_index_j <= '0';`
536			`read_enable <= '0';`
537			`write_enable <= '1';`
538
539
540			`when grant_read_access =>`
541			`NextState <= check_i_j;`
542			`inc_count <= '0';`
543			`inc_index_i <= '0';`
544			`inc_index_j <= '0';`
545			`clear_index_i <= '0';`
546			`clear_index_j <= '0';`
547			`read_enable <= '1';`
548			`write_enable <= '0';`
549
550			`when check_i_j =>`
551			`if(index_i = 7 AND index_j = num_of_ports) then`
552			`NextState <= increment_access_count;`
553			`elsif(index_j = num_of_ports) then`
554			`NextState <= clear_j;`
555			`else`
556			`NextState <= increment_req_index_i;`
557			`end if;`
558
559			`inc_count <= '0';`
560			`inc_index_i <= '0';`
561			`inc_index_j <= '0';`
562			`clear_index_i <= '0';`
563			`clear_index_j <= '0';`
564			`read_enable <= '0';`
565			`write_enable <= '0';`
566
567
568			`when increment_req_index_i =>`
569			`NextState <= access_requested;`
570			`inc_count <= '0';`
571			`inc_index_i <= '0';`
572			`inc_index_j <= '1';`
573			`clear_index_i <= '0';`
574			`clear_index_j <= '0';`
575			`read_enable <= '0';`
576			`write_enable <= '0';`
577
578
579			`when clear_j =>`
580			`NextState <= access_requested;`
581			`inc_count <= '0';`
582			`inc_index_i <= '1';`
583			`inc_index_j <= '0';`
584			`clear_index_i <= '0';`
585			`clear_index_j <= '1';`
586			`read_enable <= '0';`
587			`write_enable <= '0';`
588
589
590
591			`when increment_access_count =>`
592			`NextState <= reset_state;`
593			`inc_count <= '1';`
594			`inc_index_i <= '0';`
595			`inc_index_j <= '0';`
596			`clear_index_i <= '1';`
597			`clear_index_j <= '1';`
598			`read_enable <= '0';`
599			`write_enable <= '0';`
600
601
602			`when others =>`
603			`NextState <= reset_state;`
604			`inc_count <= '0';`
605			`inc_index_i <= '0';`
606			`inc_index_j <= '0';`
607			`clear_index_i <= '0';`
608			`clear_index_j <= '0';`
609			`read_enable <= '0';`
610			`write_enable <= '0';`
611			`end case;`
612			`end process Arbitration_algorithm;`
613
614			`nextstatelogic: process`
615			`begin`
616			`wait until clock'EVENT and clock = '1'; --WAIT FOR RISING EDGE`
617			`-- INITIALIZATION`
618			`if (Reset = '1') then`
619			`CurrentState <= reset_state;`
620			`else`
621			`CurrentState <= NextState;`
622			`end if;`
623			`end process nextstatelogic;`
624			`end Behavioral;`
625
626
627
628			`-- when access_requested_check =>`
629			`-- if((request(index_i) = '1') AND Memory_Access_in.priority_i(index_j)(index_k) = access_count(index_i)) then`
630			`-- NextState <= idle_0;`
631			`-- else`
632			`-- NextState <= idle_0;`
633			`-- end if;`
634			`--`
635			`-- inc_count <= '1';`