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[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [Address Generation/] [RDIC/] [Burst_data_Buffer.vhd] - Blame information for rev 21

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----------------------------------------------------------------------------------
--
--  This file is a part of Technica Corporation Wizardry Project
--
--  Copyright (C) 2004-2009, Technica Corporation  
--
--  This program is free software: you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation, either version 3 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Module Name: Burst_data_Buffer - Behavioral 
-- Project Name: Wizardry
-- Target Devices: Virtex 4 ML401
-- Description: Behavioral description for burst data buffer.
-- Revision: 1.0
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.MAC_Constants.all;
 
entity Burst_data_Buffer is
    Port (clock : in  STD_LOGIC;
                        device_clock : in  STD_LOGIC;
                        reset : in std_logic;
                        we_i : in std_logic;
                        data_in : in std_logic_vector(data_width -1 downto 0);
                        address_in : in std_logic_vector(virtual_address_width -1 downto 0);
                        data_out : out std_logic_vector((data_width + virtual_address_width)-1 downto 0);
                        read_address : out std_logic_vector(virtual_address_width -1 downto 0);
                        pop : in std_logic;
                        cyc_i : in std_logic;
                        stb_i : in std_logic;
                        lock_i : in std_logic;
                        read_err_i : in std_logic;
                        write_err_i : in std_logic;
                        err_o : out std_logic;
                        read_buffer_full : in std_logic;
                        read_serviced : in std_logic;
                        read_acknowledge : in std_logic;
                        reset_pop_count_in : in std_logic;
                        buffer_full : out std_logic;
                        buffer_empty : out std_logic;
                        write_enable_out : out std_logic;
                        read_enable_out : out std_logic;
                        acknowledge : out std_logic;
                        reset_buffer : out std_logic;
                        acknowledge_read_data : out std_logic
                        );
end Burst_data_Buffer;
 
architecture Behavioral of Burst_data_Buffer is
 
--type Burst_Data_Array is
--      array (0 to burst_length -1) of std_logic_vector((data_width + virtual_address_width) -1 downto 0);
signal full_s,empty_s,push_s,clear_push_count: std_logic;
signal address_in_s, read_address_s : std_logic_vector(virtual_address_width -1 downto 0);
signal buffer_input_data_s : std_logic_vector((data_width + virtual_address_width) -1 downto 0);
type StateType is (idle,pull_data,check_lock,check_buff_status,send_data,check_full,acknowledge_data,
        send_data_0,check_buff_status_0,send_acknowledge,send_acknowledge_wait,single_write,write_error_0);
     signal CurrentState,NextState: StateType;
 
type StateType_read is (reset_idle,assert_read_enable,check_lock_and_bits,check_lock_and_bits_1,clear_buffer,
        wait_buffer_full,acknowledge_single_read,acknowledge_block_read,error_state,acknowledge_single_read_0);
     signal CurrentState_read,NextState_read: StateType_read;
 
signal var_a, var_b : integer range 0 to burst_length -1 := 0;
signal Data_array_v : burst_data_array;
signal push_count,pop_count : std_logic_vector(2 downto 0) := "000";
 
begin
buffer_input_data : process(clock, reset,cyc_i, stb_i,data_in,address_in,read_acknowledge,read_address_s)
variable buffer_input_data_v : std_logic_vector((data_width + virtual_address_width) -1 downto 0);
variable address_in_v : std_logic_vector(virtual_address_width -1 downto 0);
begin
if clock='1' and clock'event then
        if(reset = '1' OR read_acknowledge = '1') then
                address_in_v := "0000000000000000000000";
                read_address_s <= (others => '0');
        elsif(cyc_i = '1' AND stb_i = '1') then
                if(we_i = '1') then
--                      buffer_input_data_v := data_in & address_in;
                        buffer_input_data_s <= data_in & address_in;
                        address_in_v := address_in;
                        read_address_s <= read_address_s;
                elsif(we_i = '0')then
                        buffer_input_data_s <= (others => '0');
                        address_in_v := address_in;
                        read_address_s <= address_in;
                end if;
        else
                buffer_input_data_s <= buffer_input_data_s;
                address_in_v := address_in_v;
                read_address_s <= read_address_s;
        end if;
 
end if;
--buffer_input_data_s <= buffer_input_data_v;
address_in_s <= address_in_v;
read_address <= read_address_s;
end process buffer_input_data;
 
 
process(clock,read_err_i,write_err_i)
begin
if clock='1' and clock'event then
        for i in 0 to num_of_ports loop
                if(read_err_i = '1') then
                        err_o <= '1';
                elsif(write_err_i = '1') then
                        err_o <= '1';
                else
                        err_o <= '0';
                end if;
        end loop;
end if;
end process;
 
 
read_communication: process(CurrentState_read, lock_i, cyc_i, stb_i, read_buffer_full,read_serviced,read_address_s,we_i,read_err_i)
 
   begin
 
                case (CurrentState_read) is
                        when reset_idle =>
                                if (we_i = '0' AND cyc_i = '1' AND stb_i = '1') then
                                        NextState_read <= assert_read_enable;
                                else
                                        NextState_read <= reset_idle;
                                end if;
 
                        reset_buffer <= '1';
                        acknowledge_read_data <= '0';
                        read_enable_out <= '0';
--                      err_o   <= '0';
--                      read_address <= (others => '0');
 
                        when assert_read_enable =>
                                if (read_serviced = '1') then
                                        NextState_read <= wait_buffer_full;
                                else
                                        NextState_read <= assert_read_enable;
                                end if;
 
                        reset_buffer <= '0';
                        acknowledge_read_data <= '0';
                        read_enable_out <= '1';
--                      err_o   <= '0';
--                      read_address <= read_address_s;
 
 
                        when wait_buffer_full =>
                                if (read_buffer_full = '1') then
                                        NextState_read <= check_lock_and_bits;
                                elsif(read_err_i = '1') then
                                        NextState_read <= error_state;
                                else
                                        NextState_read <= wait_buffer_full;
                                end if;
 
                        reset_buffer <= '0';
                        acknowledge_read_data <= '0';
                        read_enable_out <= '0';
--                      err_o   <= '0';
--                      read_address <= read_address_s;
 
                        when check_lock_and_bits =>
                                if (lock_i = '0') then
                                        NextState_read <= acknowledge_single_read;
                                elsif(read_address_s(1 downto 0) = "11") then
                                        NextState_read <= acknowledge_single_read;
                                else
                                        NextState_read <= acknowledge_block_read;
                                end if;
 
                        reset_buffer <= '0';
                        acknowledge_read_data <= '0';
                        read_enable_out <= '0';
--                      err_o   <= '0';
--                      read_address <= (others => '0');
 
                        when acknowledge_single_read =>
                                        NextState_read <= acknowledge_single_read_0;
 
                        reset_buffer <= '0';
                        acknowledge_read_data <= '1';
                        read_enable_out <= '0';
--                      err_o   <= '0';
--                      read_address <= (others => '0');
 
                        when acknowledge_single_read_0 =>
                                        NextState_read <= reset_idle;
 
                        reset_buffer <= '0';
                        acknowledge_read_data <= '0';
                        read_enable_out <= '0';
--                      err_o   <= '0';
--                      read_address <= (others => '0');
 
                        when acknowledge_block_read =>
                                        NextState_read <= check_lock_and_bits_1;
 
                        reset_buffer <= '0';
                        acknowledge_read_data <= '1';
                        read_enable_out <= '0';
--                      err_o   <= '0';
--                      read_address <= (others => '0');
 
                        when check_lock_and_bits_1 =>
                                if (we_i = '0' AND cyc_i = '1' AND stb_i = '1' AND lock_i = '1') then
                                        NextState_read <= check_lock_and_bits;
                                elsif (we_i = '0' AND cyc_i = '0' AND stb_i = '0' AND lock_i = '1') then
                                        NextState_read <= check_lock_and_bits_1;
                                elsif (we_i = '0' AND cyc_i = '1' AND stb_i = '1' AND lock_i = '0') then
                                        NextState_read <= clear_buffer;
                                else
                                        NextState_read <= reset_idle;
                                end if;
 
                        reset_buffer <= '0';
                        acknowledge_read_data <= '0';
                        read_enable_out <= '0';
--                      err_o   <= '0';
--                      read_address <= (others => '0');
 
                        when error_state =>
                                        NextState_read <= reset_idle;
 
                        reset_buffer <= '0';
                        acknowledge_read_data <= '0';
                        read_enable_out <= '0';
--                      err_o   <= '1';
--                      read_address <= (others => '0');
 
                        when clear_buffer =>
                                        NextState_read <= assert_read_enable;
 
                        reset_buffer <= '1';
                        acknowledge_read_data <= '0';
                        read_enable_out <= '0';
--                      err_o   <= '0';
--                      read_address <= (others => '0');
 
                        when others =>
                                        NextState_read <= reset_idle;
                        reset_buffer <= '0';
                        acknowledge_read_data <= '0';
                        read_enable_out <= '0';
--                      err_o   <= '0';
--                      read_address <= (others => '0');
 
        end case;
 
end process read_communication;
 
nextstatelogic_read: process
--(clock,reset)
        begin
                        wait until device_clock'EVENT and device_clock = '1'; --WAIT FOR RISING EDGE
--      if(rising_edge(clock)) then
                -- INITIALIZATION
                if (Reset = '1') then
                        CurrentState_read <= reset_idle;
                else
                                        CurrentState_read <= NextState_read;
                end if;
--      end if;
end process nextstatelogic_read;
 
 
buffer_communication: process(CurrentState, lock_i, cyc_i, stb_i, empty_s, we_i,full_s,write_err_i)
 
   begin
 
                case (CurrentState) is
                        when idle=>
                                if (we_i = '1' AND lock_i = '1' AND cyc_i = '1' AND stb_i = '1') then
                                        NextState <= pull_data;
                                elsif (we_i = '1' AND cyc_i = '1' AND stb_i = '1') then
                                        NextState <= single_write;
                                else
                                        NextState <= idle;
                                end if;
 
                        push_s <= '0';
                        acknowledge <= '0';
                        write_enable_out <= '0';
                        clear_push_count <= '0';
--                      clear_pop_count <= '0';
 
                        when pull_data =>
                                        NextState <= check_full;
 
                        push_s <= '1';
                        acknowledge <= '0';
                        write_enable_out <= '0';
                        clear_push_count <= '0';
--                      clear_pop_count <= '0';
 
                        when check_full =>
                                if(full_s = '1') then
                                        NextState <= send_data_0;
                                else
                                        NextState <= acknowledge_data;
                                end if;
                        push_s <= '0';
                        acknowledge <= '0';
                        write_enable_out <= '0';
                        clear_push_count <= '0';
--                      clear_pop_count <= '0';
 
                        when acknowledge_data =>
                                        NextState <= check_lock;
                        push_s <= '0';
                        acknowledge <= '1';
                        write_enable_out <= '0';
                        clear_push_count <= '0';
--                      clear_pop_count <= '0';
 
                        when check_lock =>
                                if (lock_i = '0') then
                                        NextState <= send_data;
                                else
                                        NextState <= idle;
                                end if;
 
                        push_s <= '0';
                        acknowledge <= '0';
                        write_enable_out <= '0';
                        clear_push_count <= '0';
--                      clear_pop_count <= '0';
 
 
                        when send_data =>
                                        NextState <= check_buff_status;
 
                        push_s <= '0';
                        acknowledge <= '0';
                        write_enable_out <= '1';
                        clear_push_count <= '0';
--                      clear_pop_count <= '0';
 
                        when send_data_0 =>
                                        NextState <= check_buff_status_0;
 
                        push_s <= '0';
                        acknowledge <= '0';
                        write_enable_out <= '1';
                        clear_push_count <= '0';
--                      clear_pop_count <= '0';
 
                        when check_buff_status =>
                                if (empty_s = '1') then
                                        NextState <= idle;
                                else
                                        NextState <= check_buff_status;
                                end if;
 
                        push_s <= '0';
                        acknowledge <= '0';
                        write_enable_out <= '1';
                        clear_push_count <= '0';
--                      clear_pop_count <= '0';
 
                        when check_buff_status_0 =>
                                if (empty_s = '1') then
                                        NextState <= send_acknowledge;
                                elsif (write_err_i = '1') then
                                        NextState <= write_error_0;
                                else
                                        NextState <= check_buff_status_0;
                                end if;
 
                        push_s <= '0';
                        acknowledge <= '0';
                        write_enable_out <= '1';
                        clear_push_count <= '0';
--                      clear_pop_count <= '0';
 
                        when write_error_0 =>
                                        NextState <= send_acknowledge_wait;
 
                        push_s <= '0';
                        acknowledge <= '0';
                        write_enable_out <= '0';
                        clear_push_count <= '1';
 
                        when send_acknowledge =>
                                        NextState <= send_acknowledge_wait;
 
                        push_s <= '0';
                        acknowledge <= '1';
                        write_enable_out <= '0';
                        clear_push_count <= '1';
--                      clear_pop_count <= '1';
 
                        when send_acknowledge_wait =>
                                        NextState <= idle;
 
                        push_s <= '0';
                        acknowledge <= '0';
                        write_enable_out <= '0';
                        clear_push_count <= '0';
--                      clear_pop_count <= '1';
 
                        when single_write =>
                                        NextState <= send_data_0;
 
                        push_s <= '1';
                        acknowledge <= '0';
                        write_enable_out <= '0';
                        clear_push_count <= '0';
--                      clear_pop_count <= '0';
 
                        when others =>
                                        NextState <= idle;
                        push_s <= '0';
                        acknowledge <= '0';
                        write_enable_out <= '0';
                        clear_push_count <= '0';
--                      clear_pop_count <= '0';
 
        end case;
 
end process buffer_communication;
 
nextstatelogic: process
--(clock,reset)
        begin
                        wait until device_clock'EVENT and device_clock = '1'; --WAIT FOR RISING EDGE
--      if(rising_edge(clock)) then
                -- INITIALIZATION
                if (Reset = '1') then
                        CurrentState <= idle;
                else
                                        CurrentState <= NextState;
                end if;
--      end if;
end process nextstatelogic;
 
pop_buffer_burst_data : process(clock,reset,pop,push_s,address_in,pop_count,data_array_v,reset_pop_count_in)
--variable Data_array_v : burst_data_array;
--variable var_a, var_b : integer range 0 to burst_length -1;
--variable count_v : std_logic_vector(2 downto 0);
begin
if (clock='1' and clock'event) then
 
      if reset='1' then
--                      var_a <= 0;
--                      var_b <= 0;
--                      count_v <= "000";
--                      for i in 0 to (burst_length -1) loop
--                              data_array_v(i) <= (others => '0');
--                      end loop;
                else
 
--                      if(push_s = '1') then -- AND full_s = '0') then
--                              if(count_v < "100") then
--                                      Data_array_v(var_a) <= buffer_input_data_s;
--                                      count_v <= count_v +1;
--                                      if(var_a = burst_length -1) then
--                                              var_a <= 0;
--                                      else
--                                              var_a <= var_a +1;
--                                      end if;
--                              end if;
 
--                      els
                        if(reset_pop_count_in = '1') then
                                pop_count <= "000";
 
                        elsif(pop = '1' AND push_s = '0') then -- AND empty_s = '0') then
                                if(empty_s = '0') then
--                                      if(pop_count = "011") then
--                                              pop_count <= "000";
--                                      else
                                                pop_count <= pop_count +1;
--                                      end if;
                                        if(var_b = burst_length -1) then
                                                var_b <= 0;
                                        else
                                                var_b <= var_b +1;
                                        end if;
                                end if;
                        else
                                pop_count <= pop_count;
--                              var_a <= var_a;
                                var_b <= var_b;
                        end if;
                end if;
end if;
 
data_out <= Data_array_v(var_b);
 
end process pop_buffer_burst_data;
 
 
 
 
 
 
push_buffer_burst_data : process(device_clock,reset,push_s,address_in,push_count,buffer_input_data_s,clear_push_count)
--variable Data_array_v : burst_data_array;
--variable var_a, var_b : integer range 0 to burst_length -1;
--variable count_v : std_logic_vector(2 downto 0);
begin
if (device_clock='1' and device_clock'event) then
 
      if reset='1' then
--                      var_a <= 0;
--                      var_b <= 0;
--                      count_v <= "000";
--                      for i in 0 to (burst_length -1) loop
--                              data_array_v(i) <= (others => '0');
--                      end loop;
                else
--                      if(pop = '1') then
 
--                      if(push_count = "100") then
--                              push_count <= "000";
--                      els
                        if(clear_push_count = '1') then
                                push_count <= "000";
 
                        elsif(push_s = '1' and pop = '0') then -- AND full_s = '0') then
--                              if(count_v < "100") then
                                if(push_count = "100") then
                                        push_count <= "000";
                                else
                                        push_count <= push_count +1;
                                end if;
                                Data_array_v(var_a) <= buffer_input_data_s;
                                        if(var_a = burst_length -1) then
                                                var_a <= 0;
                                        else
                                                var_a <= var_a +1;
--                                      end if;
                                end if;
 
--                      elsif(pop = '1') then -- AND empty_s = '0') then
--                              if(empty_s = '0') then
--                                      count_v <= count_v -1;
--                                      if(var_b = burst_length -1) then
--                                              var_b <= 0;
--                                      else
--                                              var_b <= var_b +1;
--                                      end if;
--                              end if;
                        else
                                push_count <= push_count;
                                var_a <= var_a;
--                              var_b <= var_b;
                        end if;
                end if;
end if;
 
--count_v_s <= count_v;
--data_out <= Data_array_v(var_b); 
--
end process push_buffer_burst_data;
 
 
 
 
 
FULL_s      <=  '1' when ((conv_integer(push_count) = 1) OR (Data_array_v(var_b)(1 downto 0) = "11")
                                                OR (address_in_s(1 downto 0) = "11" AND empty_s = '0')) else '0';
EMPTY_s     <=  '1' when (pop_count = "100" OR pop_count = push_count) else '0';
 
--FULL_s      <=  '1' when ((conv_integer(push_count) = stack_depth) OR (Data_array_v(var_b)(1 downto 0) = "11") 
--                                              OR (address_in_s(1 downto 0) = "11" AND empty_s = '0')) else '0';
--EMPTY_s     <=  '1' when (pop_count = "100" OR pop_count = push_count) else '0';
 
 
buffer_full <= full_s;
buffer_empty <= empty_s;
 
 
 
end Behavioral;
 

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Subversion Repositories the_wizardry_project

[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [Address Generation/] [RDIC/] [Burst_data_Buffer.vhd] - Blame information for rev 21

Line No.	Rev	Author	Line
1	21	mcwaccent	`----------------------------------------------------------------------------------`
2			`--`
3			`-- This file is a part of Technica Corporation Wizardry Project`
4			`--`
5			`-- Copyright (C) 2004-2009, Technica Corporation`
6			`--`
7			`-- This program is free software: you can redistribute it and/or modify`
8			`-- it under the terms of the GNU General Public License as published by`
9			`-- the Free Software Foundation, either version 3 of the License, or`
10			`-- (at your option) any later version.`
11			`--`
12			`-- This program is distributed in the hope that it will be useful,`
13			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
15			`-- GNU General Public License for more details.`
16			`--`
17			`-- You should have received a copy of the GNU General Public License`
18			`-- along with this program. If not, see <http://www.gnu.org/licenses/>.`
19			`--`
20			`----------------------------------------------------------------------------------`
21			`----------------------------------------------------------------------------------`
22			`-- Module Name: Burst_data_Buffer - Behavioral`
23			`-- Project Name: Wizardry`
24			`-- Target Devices: Virtex 4 ML401`
25			`-- Description: Behavioral description for burst data buffer.`
26			`-- Revision: 1.0`
27			`-- Additional Comments:`
28			`--`
29			`----------------------------------------------------------------------------------`
30			`library IEEE;`
31			`use IEEE.STD_LOGIC_1164.ALL;`
32			`use IEEE.STD_LOGIC_ARITH.ALL;`
33			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
34			`use work.MAC_Constants.all;`
35
36			`entity Burst_data_Buffer is`
37			`Port (clock : in STD_LOGIC;`
38			`device_clock : in STD_LOGIC;`
39			`reset : in std_logic;`
40			`we_i : in std_logic;`
41			`data_in : in std_logic_vector(data_width -1 downto 0);`
42			`address_in : in std_logic_vector(virtual_address_width -1 downto 0);`
43			`data_out : out std_logic_vector((data_width + virtual_address_width)-1 downto 0);`
44			`read_address : out std_logic_vector(virtual_address_width -1 downto 0);`
45			`pop : in std_logic;`
46			`cyc_i : in std_logic;`
47			`stb_i : in std_logic;`
48			`lock_i : in std_logic;`
49			`read_err_i : in std_logic;`
50			`write_err_i : in std_logic;`
51			`err_o : out std_logic;`
52			`read_buffer_full : in std_logic;`
53			`read_serviced : in std_logic;`
54			`read_acknowledge : in std_logic;`
55			`reset_pop_count_in : in std_logic;`
56			`buffer_full : out std_logic;`
57			`buffer_empty : out std_logic;`
58			`write_enable_out : out std_logic;`
59			`read_enable_out : out std_logic;`
60			`acknowledge : out std_logic;`
61			`reset_buffer : out std_logic;`
62			`acknowledge_read_data : out std_logic`
63			`);`
64			`end Burst_data_Buffer;`
65
66			`architecture Behavioral of Burst_data_Buffer is`
67
68			`--type Burst_Data_Array is`
69			`-- array (0 to burst_length -1) of std_logic_vector((data_width + virtual_address_width) -1 downto 0);`
70			`signal full_s,empty_s,push_s,clear_push_count: std_logic;`
71			`signal address_in_s, read_address_s : std_logic_vector(virtual_address_width -1 downto 0);`
72			`signal buffer_input_data_s : std_logic_vector((data_width + virtual_address_width) -1 downto 0);`
73			`type StateType is (idle,pull_data,check_lock,check_buff_status,send_data,check_full,acknowledge_data,`
74			`send_data_0,check_buff_status_0,send_acknowledge,send_acknowledge_wait,single_write,write_error_0);`
75			`signal CurrentState,NextState: StateType;`
76
77			`type StateType_read is (reset_idle,assert_read_enable,check_lock_and_bits,check_lock_and_bits_1,clear_buffer,`
78			`wait_buffer_full,acknowledge_single_read,acknowledge_block_read,error_state,acknowledge_single_read_0);`
79			`signal CurrentState_read,NextState_read: StateType_read;`
80
81			`signal var_a, var_b : integer range 0 to burst_length -1 := 0;`
82			`signal Data_array_v : burst_data_array;`
83			`signal push_count,pop_count : std_logic_vector(2 downto 0) := "000";`
84
85			`begin`
86			`buffer_input_data : process(clock, reset,cyc_i, stb_i,data_in,address_in,read_acknowledge,read_address_s)`
87			`variable buffer_input_data_v : std_logic_vector((data_width + virtual_address_width) -1 downto 0);`
88			`variable address_in_v : std_logic_vector(virtual_address_width -1 downto 0);`
89			`begin`
90			`if clock='1' and clock'event then`
91			`if(reset = '1' OR read_acknowledge = '1') then`
92			`address_in_v := "0000000000000000000000";`
93			`read_address_s <= (others => '0');`
94			`elsif(cyc_i = '1' AND stb_i = '1') then`
95			`if(we_i = '1') then`
96			`-- buffer_input_data_v := data_in & address_in;`
97			`buffer_input_data_s <= data_in & address_in;`
98			`address_in_v := address_in;`
99			`read_address_s <= read_address_s;`
100			`elsif(we_i = '0')then`
101			`buffer_input_data_s <= (others => '0');`
102			`address_in_v := address_in;`
103			`read_address_s <= address_in;`
104			`end if;`
105			`else`
106			`buffer_input_data_s <= buffer_input_data_s;`
107			`address_in_v := address_in_v;`
108			`read_address_s <= read_address_s;`
109			`end if;`
110
111			`end if;`
112			`--buffer_input_data_s <= buffer_input_data_v;`
113			`address_in_s <= address_in_v;`
114			`read_address <= read_address_s;`
115			`end process buffer_input_data;`
116
117
118			`process(clock,read_err_i,write_err_i)`
119			`begin`
120			`if clock='1' and clock'event then`
121			`for i in 0 to num_of_ports loop`
122			`if(read_err_i = '1') then`
123			`err_o <= '1';`
124			`elsif(write_err_i = '1') then`
125			`err_o <= '1';`
126			`else`
127			`err_o <= '0';`
128			`end if;`
129			`end loop;`
130			`end if;`
131			`end process;`
132
133
134			`read_communication: process(CurrentState_read, lock_i, cyc_i, stb_i, read_buffer_full,read_serviced,read_address_s,we_i,read_err_i)`
135
136			`begin`
137
138			`case (CurrentState_read) is`
139			`when reset_idle =>`
140			`if (we_i = '0' AND cyc_i = '1' AND stb_i = '1') then`
141			`NextState_read <= assert_read_enable;`
142			`else`
143			`NextState_read <= reset_idle;`
144			`end if;`
145
146			`reset_buffer <= '1';`
147			`acknowledge_read_data <= '0';`
148			`read_enable_out <= '0';`
149			`-- err_o <= '0';`
150			`-- read_address <= (others => '0');`
151
152			`when assert_read_enable =>`
153			`if (read_serviced = '1') then`
154			`NextState_read <= wait_buffer_full;`
155			`else`
156			`NextState_read <= assert_read_enable;`
157			`end if;`
158
159			`reset_buffer <= '0';`
160			`acknowledge_read_data <= '0';`
161			`read_enable_out <= '1';`
162			`-- err_o <= '0';`
163			`-- read_address <= read_address_s;`
164
165
166			`when wait_buffer_full =>`
167			`if (read_buffer_full = '1') then`
168			`NextState_read <= check_lock_and_bits;`
169			`elsif(read_err_i = '1') then`
170			`NextState_read <= error_state;`
171			`else`
172			`NextState_read <= wait_buffer_full;`
173			`end if;`
174
175			`reset_buffer <= '0';`
176			`acknowledge_read_data <= '0';`
177			`read_enable_out <= '0';`
178			`-- err_o <= '0';`
179			`-- read_address <= read_address_s;`
180
181			`when check_lock_and_bits =>`
182			`if (lock_i = '0') then`
183			`NextState_read <= acknowledge_single_read;`
184			`elsif(read_address_s(1 downto 0) = "11") then`
185			`NextState_read <= acknowledge_single_read;`
186			`else`
187			`NextState_read <= acknowledge_block_read;`
188			`end if;`
189
190			`reset_buffer <= '0';`
191			`acknowledge_read_data <= '0';`
192			`read_enable_out <= '0';`
193			`-- err_o <= '0';`
194			`-- read_address <= (others => '0');`
195
196			`when acknowledge_single_read =>`
197			`NextState_read <= acknowledge_single_read_0;`
198
199			`reset_buffer <= '0';`
200			`acknowledge_read_data <= '1';`
201			`read_enable_out <= '0';`
202			`-- err_o <= '0';`
203			`-- read_address <= (others => '0');`
204
205			`when acknowledge_single_read_0 =>`
206			`NextState_read <= reset_idle;`
207
208			`reset_buffer <= '0';`
209			`acknowledge_read_data <= '0';`
210			`read_enable_out <= '0';`
211			`-- err_o <= '0';`
212			`-- read_address <= (others => '0');`
213
214			`when acknowledge_block_read =>`
215			`NextState_read <= check_lock_and_bits_1;`
216
217			`reset_buffer <= '0';`
218			`acknowledge_read_data <= '1';`
219			`read_enable_out <= '0';`
220			`-- err_o <= '0';`
221			`-- read_address <= (others => '0');`
222
223			`when check_lock_and_bits_1 =>`
224			`if (we_i = '0' AND cyc_i = '1' AND stb_i = '1' AND lock_i = '1') then`
225			`NextState_read <= check_lock_and_bits;`
226			`elsif (we_i = '0' AND cyc_i = '0' AND stb_i = '0' AND lock_i = '1') then`
227			`NextState_read <= check_lock_and_bits_1;`
228			`elsif (we_i = '0' AND cyc_i = '1' AND stb_i = '1' AND lock_i = '0') then`
229			`NextState_read <= clear_buffer;`
230			`else`
231			`NextState_read <= reset_idle;`
232			`end if;`
233
234			`reset_buffer <= '0';`
235			`acknowledge_read_data <= '0';`
236			`read_enable_out <= '0';`
237			`-- err_o <= '0';`
238			`-- read_address <= (others => '0');`
239
240			`when error_state =>`
241			`NextState_read <= reset_idle;`
242
243			`reset_buffer <= '0';`
244			`acknowledge_read_data <= '0';`
245			`read_enable_out <= '0';`
246			`-- err_o <= '1';`
247			`-- read_address <= (others => '0');`
248
249			`when clear_buffer =>`
250			`NextState_read <= assert_read_enable;`
251
252			`reset_buffer <= '1';`
253			`acknowledge_read_data <= '0';`
254			`read_enable_out <= '0';`
255			`-- err_o <= '0';`
256			`-- read_address <= (others => '0');`
257
258			`when others =>`
259			`NextState_read <= reset_idle;`
260			`reset_buffer <= '0';`
261			`acknowledge_read_data <= '0';`
262			`read_enable_out <= '0';`
263			`-- err_o <= '0';`
264			`-- read_address <= (others => '0');`
265
266			`end case;`
267
268			`end process read_communication;`
269
270			`nextstatelogic_read: process`
271			`--(clock,reset)`
272			`begin`
273			`wait until device_clock'EVENT and device_clock = '1'; --WAIT FOR RISING EDGE`
274			`-- if(rising_edge(clock)) then`
275			`-- INITIALIZATION`
276			`if (Reset = '1') then`
277			`CurrentState_read <= reset_idle;`
278			`else`
279			`CurrentState_read <= NextState_read;`
280			`end if;`
281			`-- end if;`
282			`end process nextstatelogic_read;`
283
284
285			`buffer_communication: process(CurrentState, lock_i, cyc_i, stb_i, empty_s, we_i,full_s,write_err_i)`
286
287			`begin`
288
289			`case (CurrentState) is`
290			`when idle=>`
291			`if (we_i = '1' AND lock_i = '1' AND cyc_i = '1' AND stb_i = '1') then`
292			`NextState <= pull_data;`
293			`elsif (we_i = '1' AND cyc_i = '1' AND stb_i = '1') then`
294			`NextState <= single_write;`
295			`else`
296			`NextState <= idle;`
297			`end if;`
298
299			`push_s <= '0';`
300			`acknowledge <= '0';`
301			`write_enable_out <= '0';`
302			`clear_push_count <= '0';`
303			`-- clear_pop_count <= '0';`
304
305			`when pull_data =>`
306			`NextState <= check_full;`
307
308			`push_s <= '1';`
309			`acknowledge <= '0';`
310			`write_enable_out <= '0';`
311			`clear_push_count <= '0';`
312			`-- clear_pop_count <= '0';`
313
314			`when check_full =>`
315			`if(full_s = '1') then`
316			`NextState <= send_data_0;`
317			`else`
318			`NextState <= acknowledge_data;`
319			`end if;`
320			`push_s <= '0';`
321			`acknowledge <= '0';`
322			`write_enable_out <= '0';`
323			`clear_push_count <= '0';`
324			`-- clear_pop_count <= '0';`
325
326			`when acknowledge_data =>`
327			`NextState <= check_lock;`
328			`push_s <= '0';`
329			`acknowledge <= '1';`
330			`write_enable_out <= '0';`
331			`clear_push_count <= '0';`
332			`-- clear_pop_count <= '0';`
333
334			`when check_lock =>`
335			`if (lock_i = '0') then`
336			`NextState <= send_data;`
337			`else`
338			`NextState <= idle;`
339			`end if;`
340
341			`push_s <= '0';`
342			`acknowledge <= '0';`
343			`write_enable_out <= '0';`
344			`clear_push_count <= '0';`
345			`-- clear_pop_count <= '0';`
346
347
348			`when send_data =>`
349			`NextState <= check_buff_status;`
350
351			`push_s <= '0';`
352			`acknowledge <= '0';`
353			`write_enable_out <= '1';`
354			`clear_push_count <= '0';`
355			`-- clear_pop_count <= '0';`
356
357			`when send_data_0 =>`
358			`NextState <= check_buff_status_0;`
359
360			`push_s <= '0';`
361			`acknowledge <= '0';`
362			`write_enable_out <= '1';`
363			`clear_push_count <= '0';`
364			`-- clear_pop_count <= '0';`
365
366			`when check_buff_status =>`
367			`if (empty_s = '1') then`
368			`NextState <= idle;`
369			`else`
370			`NextState <= check_buff_status;`
371			`end if;`
372
373			`push_s <= '0';`
374			`acknowledge <= '0';`
375			`write_enable_out <= '1';`
376			`clear_push_count <= '0';`
377			`-- clear_pop_count <= '0';`
378
379			`when check_buff_status_0 =>`
380			`if (empty_s = '1') then`
381			`NextState <= send_acknowledge;`
382			`elsif (write_err_i = '1') then`
383			`NextState <= write_error_0;`
384			`else`
385			`NextState <= check_buff_status_0;`
386			`end if;`
387
388			`push_s <= '0';`
389			`acknowledge <= '0';`
390			`write_enable_out <= '1';`
391			`clear_push_count <= '0';`
392			`-- clear_pop_count <= '0';`
393
394			`when write_error_0 =>`
395			`NextState <= send_acknowledge_wait;`
396
397			`push_s <= '0';`
398			`acknowledge <= '0';`
399			`write_enable_out <= '0';`
400			`clear_push_count <= '1';`
401
402			`when send_acknowledge =>`
403			`NextState <= send_acknowledge_wait;`
404
405			`push_s <= '0';`
406			`acknowledge <= '1';`
407			`write_enable_out <= '0';`
408			`clear_push_count <= '1';`
409			`-- clear_pop_count <= '1';`
410
411			`when send_acknowledge_wait =>`
412			`NextState <= idle;`
413
414			`push_s <= '0';`
415			`acknowledge <= '0';`
416			`write_enable_out <= '0';`
417			`clear_push_count <= '0';`
418			`-- clear_pop_count <= '1';`
419
420			`when single_write =>`
421			`NextState <= send_data_0;`
422
423			`push_s <= '1';`
424			`acknowledge <= '0';`
425			`write_enable_out <= '0';`
426			`clear_push_count <= '0';`
427			`-- clear_pop_count <= '0';`
428
429			`when others =>`
430			`NextState <= idle;`
431			`push_s <= '0';`
432			`acknowledge <= '0';`
433			`write_enable_out <= '0';`
434			`clear_push_count <= '0';`
435			`-- clear_pop_count <= '0';`
436
437			`end case;`
438
439			`end process buffer_communication;`
440
441			`nextstatelogic: process`
442			`--(clock,reset)`
443			`begin`
444			`wait until device_clock'EVENT and device_clock = '1'; --WAIT FOR RISING EDGE`
445			`-- if(rising_edge(clock)) then`
446			`-- INITIALIZATION`
447			`if (Reset = '1') then`
448			`CurrentState <= idle;`
449			`else`
450			`CurrentState <= NextState;`
451			`end if;`
452			`-- end if;`
453			`end process nextstatelogic;`
454
455			`pop_buffer_burst_data : process(clock,reset,pop,push_s,address_in,pop_count,data_array_v,reset_pop_count_in)`
456			`--variable Data_array_v : burst_data_array;`
457			`--variable var_a, var_b : integer range 0 to burst_length -1;`
458			`--variable count_v : std_logic_vector(2 downto 0);`
459			`begin`
460			`if (clock='1' and clock'event) then`
461
462			`if reset='1' then`
463			`-- var_a <= 0;`
464			`-- var_b <= 0;`
465			`-- count_v <= "000";`
466			`-- for i in 0 to (burst_length -1) loop`
467			`-- data_array_v(i) <= (others => '0');`
468			`-- end loop;`
469			`else`
470
471			`-- if(push_s = '1') then -- AND full_s = '0') then`
472			`-- if(count_v < "100") then`
473			`-- Data_array_v(var_a) <= buffer_input_data_s;`
474			`-- count_v <= count_v +1;`
475			`-- if(var_a = burst_length -1) then`
476			`-- var_a <= 0;`
477			`-- else`
478			`-- var_a <= var_a +1;`
479			`-- end if;`
480			`-- end if;`
481
482			`-- els`
483			`if(reset_pop_count_in = '1') then`
484			`pop_count <= "000";`
485
486			`elsif(pop = '1' AND push_s = '0') then -- AND empty_s = '0') then`
487			`if(empty_s = '0') then`
488			`-- if(pop_count = "011") then`
489			`-- pop_count <= "000";`
490			`-- else`
491			`pop_count <= pop_count +1;`
492			`-- end if;`
493			`if(var_b = burst_length -1) then`
494			`var_b <= 0;`
495			`else`
496			`var_b <= var_b +1;`
497			`end if;`
498			`end if;`
499			`else`
500			`pop_count <= pop_count;`
501			`-- var_a <= var_a;`
502			`var_b <= var_b;`
503			`end if;`
504			`end if;`
505			`end if;`
506
507			`data_out <= Data_array_v(var_b);`
508
509			`end process pop_buffer_burst_data;`
510
511
512
513
514
515
516			`push_buffer_burst_data : process(device_clock,reset,push_s,address_in,push_count,buffer_input_data_s,clear_push_count)`
517			`--variable Data_array_v : burst_data_array;`
518			`--variable var_a, var_b : integer range 0 to burst_length -1;`
519			`--variable count_v : std_logic_vector(2 downto 0);`
520			`begin`
521			`if (device_clock='1' and device_clock'event) then`
522
523			`if reset='1' then`
524			`-- var_a <= 0;`
525			`-- var_b <= 0;`
526			`-- count_v <= "000";`
527			`-- for i in 0 to (burst_length -1) loop`
528			`-- data_array_v(i) <= (others => '0');`
529			`-- end loop;`
530			`else`
531			`-- if(pop = '1') then`
532
533			`-- if(push_count = "100") then`
534			`-- push_count <= "000";`
535			`-- els`
536			`if(clear_push_count = '1') then`
537			`push_count <= "000";`
538
539			`elsif(push_s = '1' and pop = '0') then -- AND full_s = '0') then`
540			`-- if(count_v < "100") then`
541			`if(push_count = "100") then`
542			`push_count <= "000";`
543			`else`
544			`push_count <= push_count +1;`
545			`end if;`
546			`Data_array_v(var_a) <= buffer_input_data_s;`
547			`if(var_a = burst_length -1) then`
548			`var_a <= 0;`
549			`else`
550			`var_a <= var_a +1;`
551			`-- end if;`
552			`end if;`
553
554			`-- elsif(pop = '1') then -- AND empty_s = '0') then`
555			`-- if(empty_s = '0') then`
556			`-- count_v <= count_v -1;`
557			`-- if(var_b = burst_length -1) then`
558			`-- var_b <= 0;`
559			`-- else`
560			`-- var_b <= var_b +1;`
561			`-- end if;`
562			`-- end if;`
563			`else`
564			`push_count <= push_count;`
565			`var_a <= var_a;`
566			`-- var_b <= var_b;`
567			`end if;`
568			`end if;`
569			`end if;`
570
571			`--count_v_s <= count_v;`
572			`--data_out <= Data_array_v(var_b);`
573			`--`
574			`end process push_buffer_burst_data;`
575
576
577
578
579
580			`FULL_s <= '1' when ((conv_integer(push_count) = 1) OR (Data_array_v(var_b)(1 downto 0) = "11")`
581			`OR (address_in_s(1 downto 0) = "11" AND empty_s = '0')) else '0';`
582			`EMPTY_s <= '1' when (pop_count = "100" OR pop_count = push_count) else '0';`
583
584			`--FULL_s <= '1' when ((conv_integer(push_count) = stack_depth) OR (Data_array_v(var_b)(1 downto 0) = "11")`
585			`-- OR (address_in_s(1 downto 0) = "11" AND empty_s = '0')) else '0';`
586			`--EMPTY_s <= '1' when (pop_count = "100" OR pop_count = push_count) else '0';`
587
588
589			`buffer_full <= full_s;`
590			`buffer_empty <= empty_s;`
591
592
593
594			`end Behavioral;`
595