1 |
21 |
mcwaccent |
----------------------------------------------------------------------------------
|
2 |
|
|
--
|
3 |
|
|
-- This file is a part of Technica Corporation Wizardry Project
|
4 |
|
|
--
|
5 |
|
|
-- Copyright (C) 2004-2009, Technica Corporation
|
6 |
|
|
--
|
7 |
|
|
-- This program is free software: you can redistribute it and/or modify
|
8 |
|
|
-- it under the terms of the GNU General Public License as published by
|
9 |
|
|
-- the Free Software Foundation, either version 3 of the License, or
|
10 |
|
|
-- (at your option) any later version.
|
11 |
|
|
--
|
12 |
|
|
-- This program is distributed in the hope that it will be useful,
|
13 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
14 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
15 |
|
|
-- GNU General Public License for more details.
|
16 |
|
|
--
|
17 |
|
|
-- You should have received a copy of the GNU General Public License
|
18 |
|
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
19 |
|
|
--
|
20 |
|
|
----------------------------------------------------------------------------------
|
21 |
|
|
----------------------------------------------------------------------------------
|
22 |
|
|
-- Module Name: read_address_decoder - Behavioral
|
23 |
|
|
-- Project Name: Wizardry
|
24 |
|
|
-- Target Devices: Virtex 4 ML401
|
25 |
|
|
-- Description: Behavioral description for read address decoder.
|
26 |
|
|
-- Revision: 1.0
|
27 |
|
|
-- Additional Comments:
|
28 |
|
|
--
|
29 |
|
|
----------------------------------------------------------------------------------
|
30 |
|
|
library IEEE;
|
31 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
32 |
|
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
33 |
|
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
34 |
|
|
use work.MAC_Constants.all;
|
35 |
|
|
|
36 |
|
|
---- Uncomment the following library declaration if instantiating
|
37 |
|
|
---- any Xilinx primitives in this code.
|
38 |
|
|
--library UNISIM;
|
39 |
|
|
--use UNISIM.VComponents.all;
|
40 |
|
|
|
41 |
|
|
entity read_address_decoder is
|
42 |
|
|
Port ( reset : in std_logic;
|
43 |
|
|
clock : in STD_LOGIC;
|
44 |
|
|
read_enable_in : in STD_LOGIC_VECTOR (num_of_ports downto 0);
|
45 |
|
|
adr_i : in v_adr_i;
|
46 |
|
|
id_i : in ID_type;
|
47 |
|
|
read_index : out integer range 0 to num_of_ports;
|
48 |
|
|
decoded_read_address_out : out STD_LOGIC_VECTOR(physical_address_width -1 downto 0);
|
49 |
|
|
err_o : out STD_LOGIC_VECTOR (num_of_ports downto 0);
|
50 |
|
|
read_enable_out : out STD_LOGIC);
|
51 |
|
|
end read_address_decoder;
|
52 |
|
|
|
53 |
|
|
architecture Behavioral of read_address_decoder is
|
54 |
|
|
type StateType is (reset_state,idle_0,read_requested,check_availability,
|
55 |
|
|
check_type, error_state,local_read, shared_read,
|
56 |
|
|
check_availability_1, find_port, find_port_0, send_read, send_read_0);
|
57 |
|
|
signal CurrentState,NextState: StateType;
|
58 |
|
|
signal store_index,store_port,send_error : std_logic;
|
59 |
|
|
signal index_i_v, port_i_v : integer range 0 to num_of_ports;
|
60 |
|
|
signal read_enable_in_v : STD_LOGIC_VECTOR (num_of_ports downto 0);
|
61 |
|
|
signal BA,BA_0 : std_logic_vector(2 downto 0);
|
62 |
|
|
|
63 |
|
|
begin
|
64 |
|
|
|
65 |
|
|
--store_index_value : process(clock,read_enable_in) --(clock,store_index) --reset_index,store_index)
|
66 |
|
|
--begin
|
67 |
|
|
-- case(read_enable_in) is
|
68 |
|
|
-- when "00000001" => index_i_v <= 0;
|
69 |
|
|
-- when "00000010" => index_i_v <= 1;
|
70 |
|
|
-- when "00000100" => index_i_v <= 2;
|
71 |
|
|
-- when "00001000" => index_i_v <= 3;
|
72 |
|
|
-- when "00010000" => index_i_v <= 4;
|
73 |
|
|
-- when "00100000" => index_i_v <= 5;
|
74 |
|
|
-- when "01000000" => index_i_v <= 6;
|
75 |
|
|
-- when "10000000" => index_i_v <= 7;
|
76 |
|
|
-- when others => index_i_v <= 0;
|
77 |
|
|
-- end case;
|
78 |
|
|
--end process;
|
79 |
|
|
|
80 |
|
|
store_index_value : process(clock,store_index,read_enable_in) --(clock,store_index) --reset_index,store_index)
|
81 |
|
|
variable index_i_v_v : integer range 0 to num_of_ports;
|
82 |
|
|
--variable read_enable_in_v : STD_LOGIC_VECTOR (num_of_ports -1 downto 0);
|
83 |
|
|
begin
|
84 |
|
|
-- if(clock'event and clock = '1') then
|
85 |
|
|
if(rising_edge(clock)) then
|
86 |
|
|
read_enable_in_v <= read_enable_in;
|
87 |
|
|
if(store_index = '1') then
|
88 |
|
|
index_i_v_v := find_high_bit(read_enable_in_v);
|
89 |
|
|
else
|
90 |
|
|
index_i_v_v := index_i_v_v;
|
91 |
|
|
end if;
|
92 |
|
|
end if;
|
93 |
|
|
index_i_v <= index_i_v_v;
|
94 |
|
|
end process;
|
95 |
|
|
|
96 |
|
|
--store_index_value : process(clock,store_index,read_enable_in) --(clock,store_index) --reset_index,store_index)
|
97 |
|
|
--begin
|
98 |
|
|
---- if(clock'event and clock = '1') then
|
99 |
|
|
-- if(rising_edge(clock)) then
|
100 |
|
|
-- read_enable_in_v <= read_enable_in;
|
101 |
|
|
-- if(store_index = '1') then
|
102 |
|
|
-- index_i_v <= find_high_bit(read_enable_in_v);
|
103 |
|
|
-- else
|
104 |
|
|
-- index_i_v <= index_i_v;
|
105 |
|
|
-- end if;
|
106 |
|
|
-- end if;
|
107 |
|
|
--end process;
|
108 |
|
|
|
109 |
|
|
save_port: process(clock,store_port,adr_i,index_i_v,id_i)
|
110 |
|
|
begin
|
111 |
|
|
-- if(clock'event and clock = '1') then
|
112 |
|
|
if(rising_edge(clock)) then
|
113 |
|
|
if(store_port = '1') then
|
114 |
|
|
port_i_v <= check_ID(adr_i,index_i_v, id_i).return_port;
|
115 |
|
|
else
|
116 |
|
|
port_i_v <= port_i_v;
|
117 |
|
|
end if;
|
118 |
|
|
end if;
|
119 |
|
|
end process;
|
120 |
|
|
|
121 |
|
|
assert_error: process(clock,send_error)
|
122 |
|
|
begin
|
123 |
|
|
-- if(clock'event and clock = '1') then
|
124 |
|
|
if(rising_edge(clock)) then
|
125 |
|
|
if(send_error = '1') then
|
126 |
|
|
err_o(index_i_v) <= '1';
|
127 |
|
|
else
|
128 |
|
|
err_o <= "000000000";
|
129 |
|
|
end if;
|
130 |
|
|
end if;
|
131 |
|
|
end process;
|
132 |
|
|
|
133 |
|
|
decode_adr : process(clock,port_i_v,adr_i) --FOR SHARED READS
|
134 |
|
|
begin
|
135 |
|
|
--if(rising_edge(clock)) then
|
136 |
|
|
--if(port_i_v < 7) then
|
137 |
|
|
--dummy_vector <= "11110";
|
138 |
|
|
case(port_i_v) is
|
139 |
|
|
when 0 => BA <= "000"; --11110";
|
140 |
|
|
when 1 => BA <= "001"; --11110";
|
141 |
|
|
when 2 => BA <= "010"; --11110";
|
142 |
|
|
when 3 => BA <= "011"; --11110";
|
143 |
|
|
when 4 => BA <= "100"; --11110";
|
144 |
|
|
when 5 => BA <= "101"; --11110";
|
145 |
|
|
when 6 => BA <= "110"; --11110";
|
146 |
|
|
when 7 => BA <= "111"; --11110";
|
147 |
|
|
when others => BA <= "000";
|
148 |
|
|
end case;
|
149 |
|
|
--else
|
150 |
|
|
--dummy_vector <= "11110";
|
151 |
|
|
-- case (adr_i(8)(18 downto 16)) is
|
152 |
|
|
-- when "000" => BA <= "000" ;--& decoded_addresses(num_of_ports)(15 downto 0);
|
153 |
|
|
-- when "001" => BA <= "001" ;--& decoded_addresses(num_of_ports)(15 downto 0);
|
154 |
|
|
-- when "010" => BA <= "010" ;--& decoded_addresses(num_of_ports)(15 downto 0);
|
155 |
|
|
-- when "011" => BA <= "011" ;--& decoded_addresses(num_of_ports)(15 downto 0);
|
156 |
|
|
-- when "100" => BA <= "100" ;--& decoded_addresses(num_of_ports)(15 downto 0);
|
157 |
|
|
-- when "101" => BA <= "101" ;--& decoded_addresses(num_of_ports)(15 downto 0);
|
158 |
|
|
-- when "110" => BA <= "110" ;--& decoded_addresses(num_of_ports)(15 downto 0);
|
159 |
|
|
-- when "111" => BA <= "111" ;--& decoded_addresses(num_of_ports)(15 downto 0);
|
160 |
|
|
-- when others => BA <= "000";
|
161 |
|
|
-- end case;
|
162 |
|
|
--end if;
|
163 |
|
|
end process;
|
164 |
|
|
|
165 |
|
|
decode_adr_0 : process(clock,read_enable_in) --FOR LOCAL READS
|
166 |
|
|
begin
|
167 |
|
|
if(rising_edge(clock)) then
|
168 |
|
|
--if(port_i_v < 7) then
|
169 |
|
|
--dummy_vector <= "11110";
|
170 |
|
|
case(read_enable_in) is
|
171 |
|
|
when "000000001" => BA_0 <= "000"; --11110";
|
172 |
|
|
when "000000010" => BA_0 <= "001"; --11110";
|
173 |
|
|
when "000000100" => BA_0 <= "010"; --11110";
|
174 |
|
|
when "000001000" => BA_0 <= "011"; --11110";
|
175 |
|
|
when "000010000" => BA_0 <= "100"; --11110";
|
176 |
|
|
when "000100000" => BA_0 <= "101"; --11110";
|
177 |
|
|
when "001000000" => BA_0 <= "110"; --11110";
|
178 |
|
|
when "010000000" => BA_0 <= "111"; --11110";
|
179 |
|
|
when others => BA_0 <= BA_0;
|
180 |
|
|
end case;
|
181 |
|
|
end if;
|
182 |
|
|
END PROCESS;
|
183 |
|
|
|
184 |
|
|
|
185 |
|
|
|
186 |
|
|
|
187 |
|
|
read_acces_process: process(CurrentState,read_enable_in,adr_i,index_i_v,id_i,BA,BA_0)--,Memory_access_in)
|
188 |
|
|
|
189 |
|
|
begin
|
190 |
|
|
case (CurrentState) is
|
191 |
|
|
when reset_state =>
|
192 |
|
|
NextState <= idle_0;
|
193 |
|
|
|
194 |
|
|
read_enable_out <= '0';
|
195 |
|
|
store_index <= '0';
|
196 |
|
|
store_port <= '0';
|
197 |
|
|
decoded_read_address_out <= (others => '0');
|
198 |
|
|
read_index <= 0;
|
199 |
|
|
send_error <= '0';
|
200 |
|
|
|
201 |
|
|
when idle_0 =>
|
202 |
|
|
if(read_enable_in = "00000000") then
|
203 |
|
|
NextState <= idle_0;
|
204 |
|
|
else
|
205 |
|
|
NextState <= read_requested;
|
206 |
|
|
end if;
|
207 |
|
|
|
208 |
|
|
read_enable_out <= '0';
|
209 |
|
|
store_index <= '0';
|
210 |
|
|
store_port <= '0';
|
211 |
|
|
decoded_read_address_out <= (others => '0');
|
212 |
|
|
read_index <= 0;
|
213 |
|
|
send_error <= '0';
|
214 |
|
|
|
215 |
|
|
when read_requested =>
|
216 |
|
|
NextState <= check_type;
|
217 |
|
|
|
218 |
|
|
read_enable_out <= '0';
|
219 |
|
|
store_index <= '1';
|
220 |
|
|
store_port <= '0';
|
221 |
|
|
decoded_read_address_out <= (others => '0');
|
222 |
|
|
read_index <= 0;
|
223 |
|
|
send_error <= '0';
|
224 |
|
|
|
225 |
|
|
when check_availability =>
|
226 |
|
|
|
227 |
|
|
NextState <= check_availability_1;
|
228 |
|
|
|
229 |
|
|
read_enable_out <= '0';
|
230 |
|
|
store_index <= '0';
|
231 |
|
|
store_port <= '0';
|
232 |
|
|
decoded_read_address_out <= (others => '0');
|
233 |
|
|
read_index <= 0;
|
234 |
|
|
send_error <= '0';
|
235 |
|
|
|
236 |
|
|
when check_availability_1 =>
|
237 |
|
|
if(check_ID(adr_i,index_i_v, id_i).id_avail) then
|
238 |
|
|
NextState <= shared_read;
|
239 |
|
|
else
|
240 |
|
|
NextState <= error_state;
|
241 |
|
|
end if;
|
242 |
|
|
|
243 |
|
|
read_enable_out <= '0';
|
244 |
|
|
store_index <= '0';
|
245 |
|
|
store_port <= '0';
|
246 |
|
|
decoded_read_address_out <= (others => '0');
|
247 |
|
|
read_index <= 0;
|
248 |
|
|
send_error <= '0';
|
249 |
|
|
|
250 |
|
|
when check_type =>
|
251 |
|
|
if(adr_i(index_i_v)(21) = '0') then
|
252 |
|
|
NextState <= local_read;
|
253 |
|
|
else
|
254 |
|
|
NextState <= check_availability;
|
255 |
|
|
end if;
|
256 |
|
|
|
257 |
|
|
read_enable_out <= '0';
|
258 |
|
|
store_index <= '0';
|
259 |
|
|
store_port <= '0';
|
260 |
|
|
decoded_read_address_out <= (others => '0');
|
261 |
|
|
read_index <= 0;
|
262 |
|
|
send_error <= '0';
|
263 |
|
|
|
264 |
|
|
when local_read =>
|
265 |
|
|
|
266 |
|
|
NextState <= find_port_0;
|
267 |
|
|
|
268 |
|
|
read_enable_out <= '0';
|
269 |
|
|
store_index <= '0';
|
270 |
|
|
store_port <= '0';
|
271 |
|
|
decoded_read_address_out <= (others => '0');
|
272 |
|
|
read_index <= 0;
|
273 |
|
|
send_error <= '0';
|
274 |
|
|
|
275 |
|
|
when find_port =>
|
276 |
|
|
|
277 |
|
|
NextState <= send_read;
|
278 |
|
|
|
279 |
|
|
read_enable_out <= '0';
|
280 |
|
|
store_index <= '0';
|
281 |
|
|
store_port <= '1';
|
282 |
|
|
decoded_read_address_out <= (others => '0');
|
283 |
|
|
read_index <= 0;
|
284 |
|
|
send_error <= '0';
|
285 |
|
|
|
286 |
|
|
when find_port_0 =>
|
287 |
|
|
|
288 |
|
|
NextState <= send_read_0;
|
289 |
|
|
|
290 |
|
|
read_enable_out <= '0';
|
291 |
|
|
store_index <= '0';
|
292 |
|
|
store_port <= '1';
|
293 |
|
|
decoded_read_address_out <= (others => '0');
|
294 |
|
|
read_index <= 0;
|
295 |
|
|
send_error <= '0';
|
296 |
|
|
|
297 |
|
|
-- when decode_address
|
298 |
|
|
-- NextState <= idle_0;
|
299 |
|
|
--
|
300 |
|
|
-- read_enable_out <= '0';
|
301 |
|
|
-- store_index <= '0';
|
302 |
|
|
-- store_port <= '0';
|
303 |
|
|
|
304 |
|
|
when send_read =>
|
305 |
|
|
NextState <= idle_0;
|
306 |
|
|
|
307 |
|
|
read_enable_out <= '1';
|
308 |
|
|
store_index <= '0';
|
309 |
|
|
store_port <= '0';
|
310 |
|
|
decoded_read_address_out <= BA & "11011" & adr_i(index_i_v) (15 downto 0);
|
311 |
|
|
read_index <= index_i_v;
|
312 |
|
|
send_error <= '0';
|
313 |
|
|
|
314 |
|
|
when send_read_0 =>
|
315 |
|
|
NextState <= idle_0;
|
316 |
|
|
|
317 |
|
|
read_enable_out <= '1';
|
318 |
|
|
store_index <= '0';
|
319 |
|
|
store_port <= '0';
|
320 |
|
|
decoded_read_address_out <= BA_0 & adr_i(index_i_v)(20 downto 0) ;
|
321 |
|
|
read_index <= index_i_v;
|
322 |
|
|
send_error <= '0';
|
323 |
|
|
|
324 |
|
|
when shared_read =>
|
325 |
|
|
|
326 |
|
|
NextState <= find_port;
|
327 |
|
|
|
328 |
|
|
read_enable_out <= '0';
|
329 |
|
|
store_index <= '0';
|
330 |
|
|
store_port <= '0';
|
331 |
|
|
decoded_read_address_out <= (others => '0');
|
332 |
|
|
read_index <= 0;
|
333 |
|
|
send_error <= '0';
|
334 |
|
|
|
335 |
|
|
when error_state =>
|
336 |
|
|
|
337 |
|
|
NextState <= reset_state;
|
338 |
|
|
|
339 |
|
|
read_enable_out <= '0';
|
340 |
|
|
store_index <= '0';
|
341 |
|
|
store_port <= '0';
|
342 |
|
|
decoded_read_address_out <= (others => '0');
|
343 |
|
|
read_index <= 0;
|
344 |
|
|
send_error <= '1';
|
345 |
|
|
|
346 |
|
|
when others =>
|
347 |
|
|
NextState <= reset_state;
|
348 |
|
|
|
349 |
|
|
read_enable_out <= '0';
|
350 |
|
|
store_index <= '0';
|
351 |
|
|
store_port <= '0';
|
352 |
|
|
decoded_read_address_out <= (others => '0');
|
353 |
|
|
read_index <= 0;
|
354 |
|
|
send_error <= '0';
|
355 |
|
|
|
356 |
|
|
end case;
|
357 |
|
|
end process read_acces_process;
|
358 |
|
|
|
359 |
|
|
nextstatelogic: process
|
360 |
|
|
begin
|
361 |
|
|
wait until clock'EVENT and clock = '1'; --WAIT FOR RISING EDGE
|
362 |
|
|
if (Reset = '1') then
|
363 |
|
|
CurrentState <= reset_state;
|
364 |
|
|
else
|
365 |
|
|
CurrentState <= NextState;
|
366 |
|
|
end if;
|
367 |
|
|
end process nextstatelogic;
|
368 |
|
|
|
369 |
|
|
|
370 |
|
|
end Behavioral;
|
371 |
|
|
|