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[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [Address Generation/] [RDIC/] [read_data_buffer.vhd] - Blame information for rev 21

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1 21 mcwaccent
----------------------------------------------------------------------------------
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--
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--  This file is a part of Technica Corporation Wizardry Project
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--
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--  Copyright (C) 2004-2009, Technica Corporation  
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--
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--  This program is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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-- Module Name: read_data_buffer - Behavioral 
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-- Project Name: Wizardry
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-- Target Devices: Virtex 4 ML401
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-- Description: Behavioral description for read data buffer.
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-- Revision: 1.0
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use work.MAC_Constants.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity read_data_buffer is
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    Port ( clock : in  STD_LOGIC;
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           reset : in  STD_LOGIC;
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                          clear_buffer : in STD_LOGIC;
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           push : in  STD_LOGIC;
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           pop : in  STD_LOGIC;
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           data_in : in  STD_LOGIC_VECTOR(data_width -1 downto 0);
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           data_out : out  STD_LOGIC_VECTOR(data_width -1 downto 0);
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                          buffer_full : out std_logic;
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                          buffer_empty : out std_logic
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                          );
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end read_data_buffer;
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architecture Behavioral of read_data_buffer is
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signal data_array_v : burst_read_data_array;
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signal var_a, var_b : integer range 0 to burst_length -1;
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signal count_v : std_logic_vector(2 downto 0);
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signal empty_s, full_s : std_logic;
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signal count_v_s : std_logic_vector(2 downto 0);
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begin
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read_burst_data : process(clock,reset,pop,push,count_v,data_array_v,clear_buffer)
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begin
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if clock='1' and clock'event then
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      if (reset='1' OR clear_buffer = '1') then
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                        var_a <= 0;
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                        var_b <= 0;
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                        count_v <= "000";
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                        for i in 0 to (burst_length -1) loop
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                                data_array_v(i) <= (others => '0');
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                        end loop;
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                else
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                        if(push = '1') then -- AND full_s = '0') then
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                                if(count_v < "100") then
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                                        Data_array_v(var_a) <= data_in;
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                                        count_v <= count_v +1;
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                                        if(var_a = burst_length -1) then
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                                                var_a <= 0;
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                                        else
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                                                var_a <= var_a +1;
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                                        end if;
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                                end if;
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                        elsif(pop = '1') then -- AND empty_s = '0') then
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                                if(empty_s = '0') then
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                                        count_v <= count_v -1;
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                                        if(var_b = burst_length -1) then
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                                                var_b <= 0;
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                                        else
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                                                var_b <= var_b +1;
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                                        end if;
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                                end if;
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                        else
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                                count_v <= count_v;
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                                var_a <= var_a;
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                                var_b <= var_b;
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                        end if;
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                end if;
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end if;
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count_v_s <= count_v;
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data_out <= Data_array_v(var_b);
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end process read_burst_data;
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--FULL_s      <=  '1' when (conv_integer(count_v_s) = stack_depth)  else '0';
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FULL_s      <=  '1' when (conv_integer(count_v_s) = 1)  else '0';
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EMPTY_s     <=  '1' when (conv_integer(count_v_s) = 0) else '0';
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buffer_full <= full_s;
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buffer_empty <= empty_s;
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end Behavioral;
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