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mcwaccent |
----------------------------------------------------------------------------------
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--
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-- This file is a part of Technica Corporation Wizardry Project
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--
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-- Copyright (C) 2004-2009, Technica Corporation
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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-- Module Name: write_address_decoder - Behavioral
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-- Project Name: Wizardry
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-- Target Devices: Virtex 4 ML401
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-- Description: Behavioral description for write address decoder.
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-- Revision: 1.0
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use work.MAC_Constants.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity write_address_decoder is
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Port ( clock : std_logic;
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ports_in : memory_access_port_in;
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burst_addresses : v_adr_i;
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write_enable_in : in STD_LOGIC_VECTOR (num_of_ports downto 0);
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decoded_write_address : out STD_LOGIC_VECTOR (physical_address_width -1 downto 0);
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write_enable_out : out STD_LOGIC_VECTOR (num_of_ports downto 0);
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write_error_out : out STD_LOGIC_VECTOR (num_of_ports downto 0)
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);
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end write_address_decoder;
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architecture Behavioral of write_address_decoder is
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signal decoded_addresses : v_adr_i;
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begin
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decode_write_addresses : process(clock,ports_in.adr_i)
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variable decoded_addresses_v : v_adr_i;
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begin
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if(clock'event and clock = '1') then
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for i in 0 to (num_of_ports) loop
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decoded_addresses_v(i) := burst_addresses(i);
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end loop;
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decoded_addresses <= decoded_addresses_v;
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end if;
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end process;
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--transmit_write_enables : process(clock,ports_in.adr_i,write_enable_in)
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--variable write_enable_out_v : STD_LOGIC_VECTOR (8 downto 0);
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--begin
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-- if(clock'event and clock = '1') then
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-- for i in 0 to (num_of_ports -1) loop
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-- if(ports_in.adr_i(i) < "0111110000000000000000" AND write_enable_in(i) = '1') then
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-- write_enable_out_v(i) := '1';
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-- else
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-- write_enable_out_v(i) := '0';
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-- end if;
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-- end loop;
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-- if(ports_in.adr_i(num_of_ports) < "0010000000000000000000" AND write_enable_in(num_of_ports) = '1') then
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-- write_enable_out_v(num_of_ports) := '1';
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-- else
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-- write_enable_out_v(num_of_ports) := '0';
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-- end if;
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---- write_enable_out <= write_enable_out_v;
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-- end if;
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-- write_enable_out <= write_enable_out_v;
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--end process;
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transmit_write_enables : process(clock,burst_addresses,write_enable_in)
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variable write_enable_out_v : STD_LOGIC_VECTOR (8 downto 0);
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begin
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if(clock'event and clock = '1') then
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if(write_enable_in(0) = '1') then
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if(decoded_addresses(0)(20 downto 18) < "111") then
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write_enable_out_v(0) := '1';
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end if;
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elsif(write_enable_in(1) = '1') then
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if(decoded_addresses(1)(20 downto 18) < "111") then
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write_enable_out_v(1) := '1';
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end if;
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elsif(write_enable_in(2) = '1') then
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if(decoded_addresses(2)(20 downto 18) < "111") then
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write_enable_out_v(2) := '1';
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end if;
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elsif(write_enable_in(3) = '1') then
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if(decoded_addresses(3)(20 downto 18) < "111") then
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write_enable_out_v(3) := '1';
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end if;
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elsif(write_enable_in(4) = '1') then
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if(decoded_addresses(4)(20 downto 18) < "111") then
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write_enable_out_v(4) := '1';
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end if;
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elsif(write_enable_in(5) = '1') then
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if(decoded_addresses(5)(20 downto 18) < "111") then
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write_enable_out_v(5) := '1';
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end if;
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elsif(write_enable_in(6) = '1') then
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if(decoded_addresses(6)(20 downto 18) < "111") then
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write_enable_out_v(6) := '1';
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end if;
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elsif(write_enable_in(7) = '1') then
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if(decoded_addresses(7)(20 downto 18) < "111") then
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write_enable_out_v(7) := '1';
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end if;
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elsif(write_enable_in(8) = '1') then
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-- if(burst_addresses(num_of_ports) < "0010000000000000000000") then
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write_enable_out_v(8) := '1';
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-- else
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-- write_enable_out_v(8) := '0';
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-- end if;
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else
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write_enable_out_v := "000000000";
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end if;
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-- if(burst_addresses(num_of_ports) < "0010000000000000000000" AND write_enable_in(num_of_ports) = '1') then
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-- write_enable_out_v(num_of_ports) := '1';
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-- else
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-- write_enable_out_v(num_of_ports) := '0';
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-- end if;
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write_enable_out <= write_enable_out_v;
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end if;
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-- write_enable_out <= write_enable_out_v;
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end process;
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select_write_enable : process(clock,write_enable_in,decoded_addresses)
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begin
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if(clock'event and clock = '1') then
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if(write_enable_in < "100000000") then
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case write_enable_in is
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when "000000001" => decoded_write_address <= "000" & decoded_addresses(0)(20 downto 0);
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when "000000010" => decoded_write_address <= "001" & decoded_addresses(1)(20 downto 0);
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when "000000100" => decoded_write_address <= "010" & decoded_addresses(2)(20 downto 0);
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when "000001000" => decoded_write_address <= "011" & decoded_addresses(3)(20 downto 0);
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when "000010000" => decoded_write_address <= "100" & decoded_addresses(4)(20 downto 0);
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when "000100000" => decoded_write_address <= "101" & decoded_addresses(5)(20 downto 0);
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when "001000000" => decoded_write_address <= "110" & decoded_addresses(6)(20 downto 0);
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when "010000000" => decoded_write_address <= "111" & decoded_addresses(7)(20 downto 0);
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when others => decoded_write_address <= "000000000000000000000000";
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end case;
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else
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case (decoded_addresses(8)(18 downto 16)) is
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when "000" => decoded_write_address <= "00011" & decoded_addresses(num_of_ports)(18 downto 0);
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when "001" => decoded_write_address <= "00111" & decoded_addresses(num_of_ports)(18 downto 0);
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when "010" => decoded_write_address <= "01011" & decoded_addresses(num_of_ports)(18 downto 0);
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when "011" => decoded_write_address <= "01111" & decoded_addresses(num_of_ports)(18 downto 0);
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when "100" => decoded_write_address <= "10011" & decoded_addresses(num_of_ports)(18 downto 0);
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when "101" => decoded_write_address <= "10111" & decoded_addresses(num_of_ports)(18 downto 0);
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when "110" => decoded_write_address <= "11011" & decoded_addresses(num_of_ports)(18 downto 0);
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when "111" => decoded_write_address <= "11111" & decoded_addresses(num_of_ports)(18 downto 0);
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when others => decoded_write_address <= "000000000000000000000000";
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end case;
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end if;
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end if;
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end process select_write_enable;
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transmit_errors : process(clock,write_enable_in,decoded_addresses)
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begin
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if(clock'event and clock = '1') then
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for i in 0 to (num_of_ports -1) loop
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if(write_enable_in(i) = '1') then
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if(decoded_addresses(i)(20 downto 18) = "111") then
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write_error_out(i) <= '1';
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end if;
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else
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write_error_out(i) <= '0';
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end if;
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end loop;
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write_error_out(num_of_ports) <= '0';
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end if;
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end process transmit_errors;
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end Behavioral;
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