| 1 |
21 |
mcwaccent |
----------------------------------------------------------------------------------
|
| 2 |
|
|
--
|
| 3 |
|
|
-- This file is a part of Technica Corporation Wizardry Project
|
| 4 |
|
|
--
|
| 5 |
|
|
-- Copyright (C) 2004-2009, Technica Corporation
|
| 6 |
|
|
--
|
| 7 |
|
|
-- This program is free software: you can redistribute it and/or modify
|
| 8 |
|
|
-- it under the terms of the GNU General Public License as published by
|
| 9 |
|
|
-- the Free Software Foundation, either version 3 of the License, or
|
| 10 |
|
|
-- (at your option) any later version.
|
| 11 |
|
|
--
|
| 12 |
|
|
-- This program is distributed in the hope that it will be useful,
|
| 13 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 14 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 15 |
|
|
-- GNU General Public License for more details.
|
| 16 |
|
|
--
|
| 17 |
|
|
-- You should have received a copy of the GNU General Public License
|
| 18 |
|
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
| 19 |
|
|
--
|
| 20 |
|
|
----------------------------------------------------------------------------------
|
| 21 |
|
|
----------------------------------------------------------------------------------
|
| 22 |
|
|
-- Module Name: Write_read_FIFO - Behavioral
|
| 23 |
|
|
-- Project Name: Wizardry
|
| 24 |
|
|
-- Target Devices: Virtex 4 ML401
|
| 25 |
|
|
-- Description: Behavioral description for read and write access.
|
| 26 |
|
|
-- Revision: 1.0
|
| 27 |
|
|
-- Additional Comments:
|
| 28 |
|
|
--
|
| 29 |
|
|
----------------------------------------------------------------------------------
|
| 30 |
|
|
library IEEE;
|
| 31 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
| 32 |
|
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
| 33 |
|
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
| 34 |
|
|
use work.MAC_Constants.all;
|
| 35 |
|
|
|
| 36 |
|
|
---- Uncomment the following library declaration if instantiating
|
| 37 |
|
|
---- any Xilinx primitives in this code.
|
| 38 |
|
|
--library UNISIM;
|
| 39 |
|
|
--use UNISIM.VComponents.all;
|
| 40 |
|
|
|
| 41 |
|
|
entity write_read_FIFO is
|
| 42 |
|
|
Port ( clock : in STD_LOGIC;
|
| 43 |
|
|
reset : in STD_LOGIC;
|
| 44 |
|
|
DAT_I : in v_data_i;
|
| 45 |
|
|
SEL_I : in v_sel_i;
|
| 46 |
|
|
Read_Enable : in STD_LOGIC;
|
| 47 |
|
|
Write_Enable : in std_logic_vector(num_of_ports downto 0);
|
| 48 |
|
|
decoded_write_address : in std_logic_vector(physical_address_width -1 downto 0);
|
| 49 |
|
|
decoded_read_address : in std_logic_vector(physical_address_width -1 downto 0);
|
| 50 |
|
|
Acknowledge_in : in STD_LOGIC;
|
| 51 |
|
|
Write_data_out : out std_logic_vector(data_width -1 downto 0);
|
| 52 |
|
|
address_out : out std_logic_vector(physical_address_width -1 downto 0);
|
| 53 |
|
|
write_enable_out : out STD_LOGIC;
|
| 54 |
|
|
read_enable_out : out STD_LOGIC;
|
| 55 |
|
|
FIFO_empty : out STD_LOGIC;
|
| 56 |
|
|
FIFO_full : out STD_LOGIC);
|
| 57 |
|
|
end write_read_FIFO;
|
| 58 |
|
|
|
| 59 |
|
|
architecture Behavioral of write_read_FIFO is
|
| 60 |
|
|
type Data_Array is
|
| 61 |
|
|
array (0 to stack_depth -1) of std_logic_vector(WR_FIFO_witdh -1 downto 0);
|
| 62 |
|
|
signal full_s,empty_s : std_logic;
|
| 63 |
|
|
signal count_v_s : std_logic_vector(2 downto 0);
|
| 64 |
|
|
signal decoded_write_address_s : std_logic_vector(physical_address_width -1 downto 0);
|
| 65 |
|
|
|
| 66 |
|
|
begin
|
| 67 |
|
|
counter : process(clock,decoded_write_address) --(clock,store_index) --reset_index,store_index)
|
| 68 |
|
|
--variable index_i_v_v : integer range 0 to num_of_ports;
|
| 69 |
|
|
--variable read_enable_in_v : STD_LOGIC_VECTOR (num_of_ports -1 downto 0);
|
| 70 |
|
|
begin
|
| 71 |
|
|
-- if(clock'event and clock = '1') then
|
| 72 |
|
|
if(rising_edge(clock)) then
|
| 73 |
|
|
decoded_write_address_s <= decoded_write_address;
|
| 74 |
|
|
end if;
|
| 75 |
|
|
end process;
|
| 76 |
|
|
|
| 77 |
|
|
|
| 78 |
|
|
|
| 79 |
|
|
store_WR_data : process(clock,reset,read_enable,write_enable,acknowledge_in)
|
| 80 |
|
|
variable Data_array_v : data_array;
|
| 81 |
|
|
variable var_a, var_b : integer range 0 to stack_depth -1;
|
| 82 |
|
|
--variable read_ack_v : STD_LOGIC_VECTOR(7 downto 0);
|
| 83 |
|
|
variable count_v : std_logic_vector(2 downto 0);
|
| 84 |
|
|
begin
|
| 85 |
|
|
if clock='1' and clock'event then
|
| 86 |
|
|
-------------------Works------------------------
|
| 87 |
|
|
if reset='1' then
|
| 88 |
|
|
var_a := 0;
|
| 89 |
|
|
var_b := 0;
|
| 90 |
|
|
count_v := "000";
|
| 91 |
|
|
for i in 0 to (stack_depth -1) loop
|
| 92 |
|
|
data_array_v(i) := (others => '0');
|
| 93 |
|
|
end loop;
|
| 94 |
|
|
else
|
| 95 |
|
|
if(read_enable = '1' AND acknowledge_in = '1') then -- AND full_s = '0') then
|
| 96 |
|
|
Data_array_v(var_a) := decoded_read_address & dummy_data & read_cmd;
|
| 97 |
|
|
-- read_ack_v(index_array(var_b)) := '1';
|
| 98 |
|
|
count_v := count_v;
|
| 99 |
|
|
if(var_a = stack_depth -1) then
|
| 100 |
|
|
var_a := 0;
|
| 101 |
|
|
else
|
| 102 |
|
|
var_a := var_a +1;
|
| 103 |
|
|
end if;
|
| 104 |
|
|
if(var_b = stack_depth -1) then
|
| 105 |
|
|
var_b := 0;
|
| 106 |
|
|
else
|
| 107 |
|
|
var_b := var_b +1;
|
| 108 |
|
|
end if;
|
| 109 |
|
|
elsif(read_enable = '1') then -- AND full_s = '0') then
|
| 110 |
|
|
if(full_s = '0') then
|
| 111 |
|
|
Data_array_v(var_a) := decoded_read_address & dummy_data & read_cmd;
|
| 112 |
|
|
count_v := count_v +1;
|
| 113 |
|
|
if(var_a = stack_depth -1) then
|
| 114 |
|
|
var_a := 0;
|
| 115 |
|
|
else
|
| 116 |
|
|
var_a := var_a +1;
|
| 117 |
|
|
end if;
|
| 118 |
|
|
end if;
|
| 119 |
|
|
|
| 120 |
|
|
----------------------------------------------------------------------
|
| 121 |
|
|
elsif(write_enable > "000000000" AND acknowledge_in = '1') then -- AND full_s = '0') then
|
| 122 |
|
|
case(write_enable) is
|
| 123 |
|
|
when "000000001" =>
|
| 124 |
|
|
Data_array_v(var_a) := decoded_write_address_s & dat_i(0) & write_cmd;
|
| 125 |
|
|
when "000000010" =>
|
| 126 |
|
|
Data_array_v(var_a) := decoded_write_address_s & dat_i(1) & write_cmd;
|
| 127 |
|
|
when "000000100" =>
|
| 128 |
|
|
Data_array_v(var_a) := decoded_write_address_s & dat_i(2) & write_cmd;
|
| 129 |
|
|
when "000001000" =>
|
| 130 |
|
|
Data_array_v(var_a) := decoded_write_address_s & dat_i(3) & write_cmd;
|
| 131 |
|
|
when "000010000" =>
|
| 132 |
|
|
Data_array_v(var_a) := decoded_write_address_s & dat_i(4) & write_cmd;
|
| 133 |
|
|
when "000100000" =>
|
| 134 |
|
|
Data_array_v(var_a) := decoded_write_address_s & dat_i(5) & write_cmd;
|
| 135 |
|
|
when "001000000" =>
|
| 136 |
|
|
Data_array_v(var_a) := decoded_write_address_s & dat_i(6) & write_cmd;
|
| 137 |
|
|
when "010000000" =>
|
| 138 |
|
|
Data_array_v(var_a) := decoded_write_address_s & dat_i(7) & write_cmd;
|
| 139 |
|
|
when "100000000" =>
|
| 140 |
|
|
Data_array_v(var_a) := decoded_write_address_s & dat_i(8) & write_cmd;
|
| 141 |
|
|
when others =>
|
| 142 |
|
|
Data_array_v(var_a) := decoded_write_address_s & dummy_data & "00";
|
| 143 |
|
|
end case;
|
| 144 |
|
|
count_v := count_v;
|
| 145 |
|
|
if(var_a = stack_depth -1) then
|
| 146 |
|
|
var_a := 0;
|
| 147 |
|
|
else
|
| 148 |
|
|
var_a := var_a +1;
|
| 149 |
|
|
end if;
|
| 150 |
|
|
if(var_b = stack_depth -1) then
|
| 151 |
|
|
var_b := 0;
|
| 152 |
|
|
else
|
| 153 |
|
|
var_b := var_b +1;
|
| 154 |
|
|
end if;
|
| 155 |
|
|
|
| 156 |
|
|
elsif(write_enable > "000000000") then
|
| 157 |
|
|
if(full_s = '0') then
|
| 158 |
|
|
count_v := count_v +1;
|
| 159 |
|
|
case(write_enable) is
|
| 160 |
|
|
when "000000001" =>
|
| 161 |
|
|
Data_array_v(var_a) := decoded_write_address_s & dat_i(0) & write_cmd;
|
| 162 |
|
|
when "000000010" =>
|
| 163 |
|
|
Data_array_v(var_a) := decoded_write_address_s & dat_i(1) & write_cmd;
|
| 164 |
|
|
when "000000100" =>
|
| 165 |
|
|
Data_array_v(var_a) := decoded_write_address_s & dat_i(2) & write_cmd;
|
| 166 |
|
|
when "000001000" =>
|
| 167 |
|
|
Data_array_v(var_a) := decoded_write_address_s & dat_i(3) & write_cmd;
|
| 168 |
|
|
when "000010000" =>
|
| 169 |
|
|
Data_array_v(var_a) := decoded_write_address_s & dat_i(4) & write_cmd;
|
| 170 |
|
|
when "000100000" =>
|
| 171 |
|
|
Data_array_v(var_a) := decoded_write_address_s & dat_i(5) & write_cmd;
|
| 172 |
|
|
when "001000000" =>
|
| 173 |
|
|
Data_array_v(var_a) := decoded_write_address_s & dat_i(6) & write_cmd;
|
| 174 |
|
|
when "010000000" =>
|
| 175 |
|
|
Data_array_v(var_a) := decoded_write_address_s & dat_i(7) & write_cmd;
|
| 176 |
|
|
when "100000000" =>
|
| 177 |
|
|
Data_array_v(var_a) := decoded_write_address_s & dat_i(8) & write_cmd;
|
| 178 |
|
|
when others =>
|
| 179 |
|
|
Data_array_v(var_a) := decoded_write_address_s & dummy_data & "00";
|
| 180 |
|
|
end case;
|
| 181 |
|
|
if(var_a = stack_depth -1) then
|
| 182 |
|
|
var_a := 0;
|
| 183 |
|
|
else
|
| 184 |
|
|
var_a := var_a +1;
|
| 185 |
|
|
end if;
|
| 186 |
|
|
end if;
|
| 187 |
|
|
elsif(acknowledge_in = '1') then -- AND empty_s = '0') then
|
| 188 |
|
|
if(empty_s = '0') then
|
| 189 |
|
|
count_v := count_v -1;
|
| 190 |
|
|
if(var_b = stack_depth -1) then
|
| 191 |
|
|
var_b := 0;
|
| 192 |
|
|
else
|
| 193 |
|
|
var_b := var_b +1;
|
| 194 |
|
|
end if;
|
| 195 |
|
|
end if;
|
| 196 |
|
|
else
|
| 197 |
|
|
count_v := count_v;
|
| 198 |
|
|
var_a := var_a;
|
| 199 |
|
|
var_b := var_b;
|
| 200 |
|
|
end if;
|
| 201 |
|
|
end if;
|
| 202 |
|
|
end if;
|
| 203 |
|
|
count_v_s <= count_v;
|
| 204 |
|
|
Write_data_out <= Data_array_v(var_b)(data_delimiter downto read_write_delimiter);
|
| 205 |
|
|
address_out <= Data_array_v(var_b)(address_delimiter downto data_delimiter +1);
|
| 206 |
|
|
--Write_data_out <= Data_array_v(var_b)(33 downto 2);
|
| 207 |
|
|
--address_out <= Data_array_v(var_b)(57 downto 34);
|
| 208 |
|
|
write_enable_out <= Data_array_v(var_b)(1);
|
| 209 |
|
|
read_enable_out <= Data_array_v(var_b)(0);
|
| 210 |
|
|
|
| 211 |
|
|
end process store_WR_data;
|
| 212 |
|
|
|
| 213 |
|
|
FULL_s <= '1'when (conv_integer(count_v_s) = stack_depth) else '0';
|
| 214 |
|
|
EMPTY_s <= '1'when (conv_integer(count_v_s) = 0) else '0';
|
| 215 |
|
|
|
| 216 |
|
|
fifo_full <= full_s;
|
| 217 |
|
|
fifo_empty <= empty_s;
|
| 218 |
|
|
|
| 219 |
|
|
end Behavioral;
|
| 220 |
|
|
|
