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mcwaccent |
----------------------------------------------------------------------------------
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--
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-- This file is a part of Technica Corporation Wizardry Project
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--
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-- Copyright (C) 2004-2009, Technica Corporation
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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-- Module Name: XILINX_RDIC_Bridge - Structural
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-- Project Name: Wizardry
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-- Target Devices: Virtex 4 ML401
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-- Description: Translates between Xilinx mem contoller and RDIC.
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-- Revision: 1.0
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity RDIC_Xilinx_bridge is
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Port ( clock : in STD_LOGIC;
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reset : in STD_LOGIC;
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fifo_empty_out : in std_Logic;
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write_enable_out : in std_logic;
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APP_AF_WREN : out std_logic;
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APP_WDF_WREN : out std_logic;
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ack_access_in : out std_logic;
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command : out std_logic_vector(2 downto 0);
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mask : out std_logic_vector(7 downto 0));
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end RDIC_Xilinx_bridge;
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architecture Behavioral of RDIC_Xilinx_bridge is
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type StateType_1 is (wait_arbitration,check_access_type,assert_write_enable,assert_read_enable,
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acknowledge_access,wait_0, wait_1,wait_2,wait_3,wait_9,acknowledge_access_0,
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wait_10,wait_11,wait_12,wait_13,wait_14,wait_15, wait_16,
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check_W_A_fifo,check_A_fifo,assert_write_enable_1,assert_write_enable_2,wait_delay,
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wait_delay_1,wait_delay_2,wait_delay_3,wait_delay_4,assert_read_enable_0);
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signal currentstate_1,nextstate_1 : statetype_1;
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begin
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process(currentstate_1,fifo_empty_out,write_enable_out)
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begin
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case currentstate_1 is
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when wait_arbitration =>
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if(fifo_empty_out = '0') then
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NextState_1 <= check_access_type;
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else
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NextState_1 <= wait_arbitration;
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end if;
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-- tx_pdata <= (others => '0');
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-- load_uart_char <= '0';
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-- read_uart_char <= '0';
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-- next_banner_char <= '0';
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-- load_banner_addres <= '0';
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-- banner_address <= (others => '0');
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-- cyc_o <= '0';
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-- stb_o <= '0';
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-- we_o <= '0';
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-- lock_o <= '0';
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-- leds <= "011111111";
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APP_AF_WREN <= '0';
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APP_WDF_WREN <= '0';
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ack_access_in <= '0';
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command <= "000";
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-- next_mem_location <= '0';
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-- load_new_addr <= '0';
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-- new_addr <= (others => '0');
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mask <= "00000000";
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when check_access_type =>
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if(write_enable_out = '1') then
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NextState_1 <= check_W_A_fifo;
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else
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NextState_1 <= check_A_fifo;
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-- else
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-- NextState <= check_A_fifo;
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end if;
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-- tx_pdata <= (others => '0');
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-- load_uart_char <= '0';
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-- read_uart_char <= '0';
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-- next_banner_char <= '0';
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-- load_banner_addres <= '0';
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-- banner_address <= (others => '0');
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-- cyc_o <= '0';
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-- stb_o <= '0';
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-- we_o <= '0';
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-- lock_o <= '0';
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-- leds <= "000011010";
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APP_AF_WREN <= '0';
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APP_WDF_WREN <= '0';
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ack_access_in <= '0';
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command <= "000";
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-- next_mem_location <= '0';
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-- load_new_addr <= '0';
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-- new_addr <= (others => '0');
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mask <= "00000000";
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when check_W_A_fifo =>
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-- if(WDF_ALMOST_FULL = '1' OR AF_ALMOST_FULL = '1') then -- may not need to check condition
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-- NextState <= check_W_A_fifo;
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-- else
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NextState_1 <= assert_write_enable;
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-- end if;
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-- tx_pdata <= (others => '0');
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-- load_uart_char <= '0';
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-- read_uart_char <= '0';
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-- next_banner_char <= '0';
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-- load_banner_addres <= '0';
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-- banner_address <= (others => '0');
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-- cyc_o <= '0';
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-- stb_o <= '0';
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-- we_o <= '0';
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-- lock_o <= '0';
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-- leds <= "000011010";
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APP_AF_WREN <= '0';
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APP_WDF_WREN <= '0';
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ack_access_in <= '0';
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command <= "100";
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-- next_mem_location <= '0';
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-- load_new_addr <= '0';
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-- new_addr <= (others => '0');
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mask <= "00000000";
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when assert_write_enable =>
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NextState_1 <= assert_write_enable_1;
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-- tx_pdata <= (others => '0');
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-- load_uart_char <= '0';
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-- read_uart_char <= '0';
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-- next_banner_char <= '0';
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-- load_banner_addres <= '0';
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-- banner_address <= (others => '0');
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-- cyc_o <= '0';
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-- stb_o <= '0';
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-- we_o <= '0';
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-- lock_o <= '0';
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-- leds <= "000011010";
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APP_AF_WREN <= '1';
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APP_WDF_WREN <= '1';
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ack_access_in <= '0';
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command <= "100";
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-- next_mem_location <= '0';
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-- load_new_addr <= '0';
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-- new_addr <= (others => '0');
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mask <= "00001111";
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when assert_write_enable_1 =>
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NextState_1 <= assert_write_enable_2;
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-- tx_pdata <= (others => '0');
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-- load_uart_char <= '0';
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-- read_uart_char <= '0';
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-- next_banner_char <= '0';
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-- load_banner_addres <= '0';
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-- banner_address <= (others => '0');
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-- cyc_o <= '0';
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-- stb_o <= '0';
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-- we_o <= '0';
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-- lock_o <= '0';
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-- leds <= "000011010";
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APP_AF_WREN <= '0';
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APP_WDF_WREN <= '1';
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ack_access_in <= '0';
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command <= "100";
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-- next_mem_location <= '0';
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-- load_new_addr <= '0';
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-- new_addr <= (others => '0');
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mask <= "11111111";
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when assert_write_enable_2 =>
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NextState_1 <= acknowledge_access_0;
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-- NextState_1 <= wait_9;
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-- tx_pdata <= (others => '0');
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-- load_uart_char <= '0';
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-- read_uart_char <= '0';
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-- next_banner_char <= '0';
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-- load_banner_addres <= '0';
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-- banner_address <= (others => '0');
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-- cyc_o <= '0';
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-- stb_o <= '0';
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-- we_o <= '0';
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-- lock_o <= '0';
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-- leds <= "000011010";
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APP_AF_WREN <= '0';
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APP_WDF_WREN <= '0';
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ack_access_in <= '0';
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command <= "100";
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-- next_mem_location <= '0';
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-- load_new_addr <= '0';
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-- new_addr <= (others => '0');
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mask <= "00000000";
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when check_A_fifo =>
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-- if(AF_ALMOST_FULL = '1') then -- may not need to check condition
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-- NextState <= check_A_fifo;
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-- else
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NextState_1 <= assert_read_enable;
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-- end if;
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-- tx_pdata <= (others => '0');
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-- load_uart_char <= '0';
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-- read_uart_char <= '0';
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-- next_banner_char <= '0';
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-- load_banner_addres <= '0';
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-- banner_address <= (others => '0');
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-- cyc_o <= '0';
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-- stb_o <= '0';
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-- we_o <= '0';
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-- lock_o <= '0';
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-- leds <= "000011010";
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APP_AF_WREN <= '0';
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APP_WDF_WREN <= '0';
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ack_access_in <= '0';
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command <= "101";
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-- next_mem_location <= '0';
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-- load_new_addr <= '0';
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-- new_addr <= (others => '0');
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mask <= "00000000";
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when assert_read_enable =>
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-- NextState_1 <= assert_read_enable_0;
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-- NextState_1 <= wait_0;
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NextState_1 <= acknowledge_access;
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-- tx_pdata <= (others => '0');
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-- load_uart_char <= '0';
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-- read_uart_char <= '0';
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-- next_banner_char <= '0';
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-- load_banner_addres <= '0';
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-- banner_address <= (others => '0');
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| 269 |
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-- cyc_o <= '0';
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| 270 |
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-- stb_o <= '0';
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| 271 |
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-- we_o <= '0';
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| 272 |
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-- lock_o <= '0';
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-- leds <= "000011010";
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APP_AF_WREN <= '1';
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APP_WDF_WREN <= '0';
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| 276 |
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ack_access_in <= '0';
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| 277 |
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command <= "101";
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| 278 |
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-- next_mem_location <= '0';
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| 279 |
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-- load_new_addr <= '0';
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| 280 |
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-- new_addr <= (others => '0');
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| 281 |
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mask <= "00000000";
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| 282 |
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| 283 |
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-------Added February 6, 2008
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| 284 |
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-- when assert_read_enable_0 =>
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| 285 |
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-- NextState_1 <= wait_0;
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--
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| 287 |
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--
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| 288 |
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---- tx_pdata <= (others => '0');
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| 289 |
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---- load_uart_char <= '0';
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| 290 |
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---- read_uart_char <= '0';
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| 291 |
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---- next_banner_char <= '0';
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| 292 |
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---- load_banner_addres <= '0';
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| 293 |
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---- banner_address <= (others => '0');
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| 294 |
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---- cyc_o <= '0';
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| 295 |
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---- stb_o <= '0';
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| 296 |
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---- we_o <= '0';
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| 297 |
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---- lock_o <= '0';
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| 298 |
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---- leds <= "000011010";
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| 299 |
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-- APP_AF_WREN <= '1';
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| 300 |
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-- APP_WDF_WREN <= '0';
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| 301 |
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-- ack_access_in <= '0';
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| 302 |
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-- command <= "101";
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| 303 |
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---- next_mem_location <= '0';
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| 304 |
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---- load_new_addr <= '0';
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| 305 |
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---- new_addr <= (others => '0');
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| 306 |
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-- mask <= "00000000";
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| 307 |
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--------------------------------------------------
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| 308 |
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| 309 |
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| 310 |
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when wait_0 =>
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NextState_1 <= wait_1;
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| 314 |
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-- tx_pdata <= (others => '0');
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| 315 |
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-- load_uart_char <= '0';
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| 316 |
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-- read_uart_char <= '0';
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| 317 |
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-- next_banner_char <= '0';
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| 318 |
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-- load_banner_addres <= '0';
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| 319 |
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-- banner_address <= (others => '0');
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| 320 |
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-- cyc_o <= '0';
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| 321 |
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-- stb_o <= '0';
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| 322 |
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-- we_o <= '0';
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| 323 |
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-- lock_o <= '0';
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| 324 |
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-- leds <= "000011010";
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| 325 |
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APP_AF_WREN <= '0';
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| 326 |
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APP_WDF_WREN <= '0';
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| 327 |
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ack_access_in <= '0';
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| 328 |
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command <= "000";
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| 329 |
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-- next_mem_location <= '0';
|
| 330 |
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-- load_new_addr <= '0';
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| 331 |
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-- new_addr <= (others => '0');
|
| 332 |
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mask <= "00000000";
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| 333 |
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| 334 |
|
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when wait_1 =>
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| 335 |
|
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NextState_1 <= wait_2;
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| 336 |
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| 337 |
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|
|
| 338 |
|
|
-- tx_pdata <= (others => '0');
|
| 339 |
|
|
-- load_uart_char <= '0';
|
| 340 |
|
|
-- read_uart_char <= '0';
|
| 341 |
|
|
-- next_banner_char <= '0';
|
| 342 |
|
|
-- load_banner_addres <= '0';
|
| 343 |
|
|
-- banner_address <= (others => '0');
|
| 344 |
|
|
-- cyc_o <= '0';
|
| 345 |
|
|
-- stb_o <= '0';
|
| 346 |
|
|
-- we_o <= '0';
|
| 347 |
|
|
-- lock_o <= '0';
|
| 348 |
|
|
-- leds <= "000011010";
|
| 349 |
|
|
APP_AF_WREN <= '0';
|
| 350 |
|
|
APP_WDF_WREN <= '0';
|
| 351 |
|
|
ack_access_in <= '0';
|
| 352 |
|
|
command <= "000";
|
| 353 |
|
|
-- next_mem_location <= '0';
|
| 354 |
|
|
-- load_new_addr <= '0';
|
| 355 |
|
|
-- new_addr <= (others => '0');
|
| 356 |
|
|
mask <= "00000000";
|
| 357 |
|
|
|
| 358 |
|
|
when wait_2 =>
|
| 359 |
|
|
NextState_1 <= wait_3;
|
| 360 |
|
|
|
| 361 |
|
|
|
| 362 |
|
|
-- tx_pdata <= (others => '0');
|
| 363 |
|
|
-- load_uart_char <= '0';
|
| 364 |
|
|
-- read_uart_char <= '0';
|
| 365 |
|
|
-- next_banner_char <= '0';
|
| 366 |
|
|
-- load_banner_addres <= '0';
|
| 367 |
|
|
-- banner_address <= (others => '0');
|
| 368 |
|
|
-- cyc_o <= '0';
|
| 369 |
|
|
-- stb_o <= '0';
|
| 370 |
|
|
-- we_o <= '0';
|
| 371 |
|
|
-- lock_o <= '0';
|
| 372 |
|
|
-- leds <= "000011010";
|
| 373 |
|
|
APP_AF_WREN <= '0';
|
| 374 |
|
|
APP_WDF_WREN <= '0';
|
| 375 |
|
|
ack_access_in <= '0';
|
| 376 |
|
|
command <= "000";
|
| 377 |
|
|
-- next_mem_location <= '0';
|
| 378 |
|
|
-- load_new_addr <= '0';
|
| 379 |
|
|
-- new_addr <= (others => '0');
|
| 380 |
|
|
mask <= "00000000";
|
| 381 |
|
|
|
| 382 |
|
|
when wait_3 =>
|
| 383 |
|
|
NextState_1 <= acknowledge_access;
|
| 384 |
|
|
|
| 385 |
|
|
|
| 386 |
|
|
-- tx_pdata <= (others => '0');
|
| 387 |
|
|
-- load_uart_char <= '0';
|
| 388 |
|
|
-- read_uart_char <= '0';
|
| 389 |
|
|
-- next_banner_char <= '0';
|
| 390 |
|
|
-- load_banner_addres <= '0';
|
| 391 |
|
|
-- banner_address <= (others => '0');
|
| 392 |
|
|
-- cyc_o <= '0';
|
| 393 |
|
|
-- stb_o <= '0';
|
| 394 |
|
|
-- we_o <= '0';
|
| 395 |
|
|
-- lock_o <= '0';
|
| 396 |
|
|
-- leds <= "000011010";
|
| 397 |
|
|
APP_AF_WREN <= '0';
|
| 398 |
|
|
APP_WDF_WREN <= '0';
|
| 399 |
|
|
ack_access_in <= '0';
|
| 400 |
|
|
command <= "000";
|
| 401 |
|
|
-- next_mem_location <= '0';
|
| 402 |
|
|
-- load_new_addr <= '0';
|
| 403 |
|
|
-- new_addr <= (others => '0');
|
| 404 |
|
|
mask <= "00000000";
|
| 405 |
|
|
|
| 406 |
|
|
when acknowledge_access =>
|
| 407 |
|
|
NextState_1 <= wait_delay;
|
| 408 |
|
|
|
| 409 |
|
|
--
|
| 410 |
|
|
-- tx_pdata <= (others => '0');
|
| 411 |
|
|
-- load_uart_char <= '0';
|
| 412 |
|
|
-- read_uart_char <= '0';
|
| 413 |
|
|
-- next_banner_char <= '0';
|
| 414 |
|
|
-- load_banner_addres <= '0';
|
| 415 |
|
|
-- banner_address <= (others => '0');
|
| 416 |
|
|
-- cyc_o <= '0';
|
| 417 |
|
|
-- stb_o <= '0';
|
| 418 |
|
|
-- we_o <= '0';
|
| 419 |
|
|
-- lock_o <= '0';
|
| 420 |
|
|
-- leds <= "000011010";
|
| 421 |
|
|
APP_AF_WREN <= '0';
|
| 422 |
|
|
APP_WDF_WREN <= '0';
|
| 423 |
|
|
ack_access_in <= '1';
|
| 424 |
|
|
command <= "000";
|
| 425 |
|
|
-- next_mem_location <= '0';
|
| 426 |
|
|
-- load_new_addr <= '0';
|
| 427 |
|
|
-- new_addr <= (others => '0');
|
| 428 |
|
|
mask <= "00000000";
|
| 429 |
|
|
|
| 430 |
|
|
|
| 431 |
|
|
when wait_delay =>
|
| 432 |
|
|
Nextstate_1 <= wait_delay_1;
|
| 433 |
|
|
-- tx_pdata <= (others => '0');
|
| 434 |
|
|
-- load_uart_char <= '0';
|
| 435 |
|
|
-- read_uart_char <= '0';
|
| 436 |
|
|
-- next_banner_char <= '0';
|
| 437 |
|
|
-- load_banner_addres <= '0';
|
| 438 |
|
|
-- banner_address <= (others => '0');
|
| 439 |
|
|
-- cyc_o <= '0';
|
| 440 |
|
|
-- stb_o <= '0';
|
| 441 |
|
|
-- we_o <= '0';
|
| 442 |
|
|
-- lock_o <= '0';
|
| 443 |
|
|
-- leds <= "000011010";
|
| 444 |
|
|
APP_AF_WREN <= '0';
|
| 445 |
|
|
APP_WDF_WREN <= '0';
|
| 446 |
|
|
ack_access_in <= '0';
|
| 447 |
|
|
command <= "000";
|
| 448 |
|
|
-- next_mem_location <= '0';
|
| 449 |
|
|
-- load_new_addr <= '0';
|
| 450 |
|
|
-- new_addr <= (others => '0');
|
| 451 |
|
|
mask <= "00000000";
|
| 452 |
|
|
|
| 453 |
|
|
when wait_delay_1 =>
|
| 454 |
|
|
Nextstate_1 <= wait_delay_2;
|
| 455 |
|
|
-- tx_pdata <= (others => '0');
|
| 456 |
|
|
-- load_uart_char <= '0';
|
| 457 |
|
|
-- read_uart_char <= '0';
|
| 458 |
|
|
-- next_banner_char <= '0';
|
| 459 |
|
|
-- load_banner_addres <= '0';
|
| 460 |
|
|
-- banner_address <= (others => '0');
|
| 461 |
|
|
-- cyc_o <= '0';
|
| 462 |
|
|
-- stb_o <= '0';
|
| 463 |
|
|
-- we_o <= '0';
|
| 464 |
|
|
-- lock_o <= '0';
|
| 465 |
|
|
-- leds <= "000011010";
|
| 466 |
|
|
APP_AF_WREN <= '0';
|
| 467 |
|
|
APP_WDF_WREN <= '0';
|
| 468 |
|
|
ack_access_in <= '0';
|
| 469 |
|
|
command <= "000";
|
| 470 |
|
|
-- next_mem_location <= '0';
|
| 471 |
|
|
-- load_new_addr <= '0';
|
| 472 |
|
|
-- new_addr <= (others => '0');
|
| 473 |
|
|
mask <= "00000000";
|
| 474 |
|
|
|
| 475 |
|
|
when wait_delay_2 =>
|
| 476 |
|
|
Nextstate_1 <= wait_delay_3;
|
| 477 |
|
|
-- tx_pdata <= (others => '0');
|
| 478 |
|
|
-- load_uart_char <= '0';
|
| 479 |
|
|
-- read_uart_char <= '0';
|
| 480 |
|
|
-- next_banner_char <= '0';
|
| 481 |
|
|
-- load_banner_addres <= '0';
|
| 482 |
|
|
-- banner_address <= (others => '0');
|
| 483 |
|
|
-- cyc_o <= '0';
|
| 484 |
|
|
-- stb_o <= '0';
|
| 485 |
|
|
-- we_o <= '0';
|
| 486 |
|
|
-- lock_o <= '0';
|
| 487 |
|
|
-- leds <= "000011010";
|
| 488 |
|
|
APP_AF_WREN <= '0';
|
| 489 |
|
|
APP_WDF_WREN <= '0';
|
| 490 |
|
|
ack_access_in <= '0';
|
| 491 |
|
|
command <= "000";
|
| 492 |
|
|
-- next_mem_location <= '0';
|
| 493 |
|
|
-- load_new_addr <= '0';
|
| 494 |
|
|
-- new_addr <= (others => '0');
|
| 495 |
|
|
mask <= "00000000";
|
| 496 |
|
|
|
| 497 |
|
|
when wait_delay_3 =>
|
| 498 |
|
|
Nextstate_1 <= wait_delay_4;
|
| 499 |
|
|
-- tx_pdata <= (others => '0');
|
| 500 |
|
|
-- load_uart_char <= '0';
|
| 501 |
|
|
-- read_uart_char <= '0';
|
| 502 |
|
|
-- next_banner_char <= '0';
|
| 503 |
|
|
-- load_banner_addres <= '0';
|
| 504 |
|
|
-- banner_address <= (others => '0');
|
| 505 |
|
|
-- cyc_o <= '0';
|
| 506 |
|
|
-- stb_o <= '0';
|
| 507 |
|
|
-- we_o <= '0';
|
| 508 |
|
|
-- lock_o <= '0';
|
| 509 |
|
|
-- leds <= "000011010";
|
| 510 |
|
|
APP_AF_WREN <= '0';
|
| 511 |
|
|
APP_WDF_WREN <= '0';
|
| 512 |
|
|
ack_access_in <= '0';
|
| 513 |
|
|
command <= "000";
|
| 514 |
|
|
-- next_mem_location <= '0';
|
| 515 |
|
|
-- load_new_addr <= '0';
|
| 516 |
|
|
-- new_addr <= (others => '0');
|
| 517 |
|
|
mask <= "00000000";
|
| 518 |
|
|
|
| 519 |
|
|
when wait_delay_4 =>
|
| 520 |
|
|
Nextstate_1 <= wait_arbitration;
|
| 521 |
|
|
-- tx_pdata <= (others => '0');
|
| 522 |
|
|
-- load_uart_char <= '0';
|
| 523 |
|
|
-- read_uart_char <= '0';
|
| 524 |
|
|
-- next_banner_char <= '0';
|
| 525 |
|
|
-- load_banner_addres <= '0';
|
| 526 |
|
|
-- banner_address <= (others => '0');
|
| 527 |
|
|
-- cyc_o <= '0';
|
| 528 |
|
|
-- stb_o <= '0';
|
| 529 |
|
|
-- we_o <= '0';
|
| 530 |
|
|
-- lock_o <= '0';
|
| 531 |
|
|
-- leds <= "000011010";
|
| 532 |
|
|
APP_AF_WREN <= '0';
|
| 533 |
|
|
APP_WDF_WREN <= '0';
|
| 534 |
|
|
ack_access_in <= '0';
|
| 535 |
|
|
command <= "000";
|
| 536 |
|
|
-- next_mem_location <= '0';
|
| 537 |
|
|
-- load_new_addr <= '0';
|
| 538 |
|
|
-- new_addr <= (others => '0');
|
| 539 |
|
|
mask <= "00000000";
|
| 540 |
|
|
|
| 541 |
|
|
when wait_9 =>
|
| 542 |
|
|
NextState_1 <= wait_10;
|
| 543 |
|
|
|
| 544 |
|
|
|
| 545 |
|
|
-- tx_pdata <= (others => '0');
|
| 546 |
|
|
-- load_uart_char <= '0';
|
| 547 |
|
|
-- read_uart_char <= '0';
|
| 548 |
|
|
-- next_banner_char <= '0';
|
| 549 |
|
|
-- load_banner_addres <= '0';
|
| 550 |
|
|
-- banner_address <= (others => '0');
|
| 551 |
|
|
-- cyc_o <= '0';
|
| 552 |
|
|
-- stb_o <= '0';
|
| 553 |
|
|
-- we_o <= '0';
|
| 554 |
|
|
-- lock_o <= '0';
|
| 555 |
|
|
-- leds <= "000011010";
|
| 556 |
|
|
APP_AF_WREN <= '0';
|
| 557 |
|
|
APP_WDF_WREN <= '0';
|
| 558 |
|
|
ack_access_in <= '0';
|
| 559 |
|
|
command <= "000";
|
| 560 |
|
|
-- next_mem_location <= '0';
|
| 561 |
|
|
-- load_new_addr <= '0';
|
| 562 |
|
|
-- new_addr <= (others => '0');
|
| 563 |
|
|
mask <= "00000000";
|
| 564 |
|
|
|
| 565 |
|
|
when wait_10 =>
|
| 566 |
|
|
NextState_1 <= wait_11;
|
| 567 |
|
|
|
| 568 |
|
|
|
| 569 |
|
|
-- tx_pdata <= (others => '0');
|
| 570 |
|
|
-- load_uart_char <= '0';
|
| 571 |
|
|
-- read_uart_char <= '0';
|
| 572 |
|
|
-- next_banner_char <= '0';
|
| 573 |
|
|
-- load_banner_addres <= '0';
|
| 574 |
|
|
-- banner_address <= (others => '0');
|
| 575 |
|
|
-- cyc_o <= '0';
|
| 576 |
|
|
-- stb_o <= '0';
|
| 577 |
|
|
-- we_o <= '0';
|
| 578 |
|
|
-- lock_o <= '0';
|
| 579 |
|
|
-- leds <= "000011010";
|
| 580 |
|
|
APP_AF_WREN <= '0';
|
| 581 |
|
|
APP_WDF_WREN <= '0';
|
| 582 |
|
|
ack_access_in <= '0';
|
| 583 |
|
|
command <= "000";
|
| 584 |
|
|
-- next_mem_location <= '0';
|
| 585 |
|
|
-- load_new_addr <= '0';
|
| 586 |
|
|
-- new_addr <= (others => '0');
|
| 587 |
|
|
mask <= "00000000";
|
| 588 |
|
|
|
| 589 |
|
|
when wait_11 =>
|
| 590 |
|
|
NextState_1 <= wait_12;
|
| 591 |
|
|
|
| 592 |
|
|
|
| 593 |
|
|
-- tx_pdata <= (others => '0');
|
| 594 |
|
|
-- load_uart_char <= '0';
|
| 595 |
|
|
-- read_uart_char <= '0';
|
| 596 |
|
|
-- next_banner_char <= '0';
|
| 597 |
|
|
-- load_banner_addres <= '0';
|
| 598 |
|
|
-- banner_address <= (others => '0');
|
| 599 |
|
|
-- cyc_o <= '0';
|
| 600 |
|
|
-- stb_o <= '0';
|
| 601 |
|
|
-- we_o <= '0';
|
| 602 |
|
|
-- lock_o <= '0';
|
| 603 |
|
|
-- leds <= "000011010";
|
| 604 |
|
|
APP_AF_WREN <= '0';
|
| 605 |
|
|
APP_WDF_WREN <= '0';
|
| 606 |
|
|
ack_access_in <= '0';
|
| 607 |
|
|
command <= "000";
|
| 608 |
|
|
-- next_mem_location <= '0';
|
| 609 |
|
|
-- load_new_addr <= '0';
|
| 610 |
|
|
-- new_addr <= (others => '0');
|
| 611 |
|
|
mask <= "00000000";
|
| 612 |
|
|
|
| 613 |
|
|
when wait_12 =>
|
| 614 |
|
|
NextState_1 <= acknowledge_access_0;
|
| 615 |
|
|
|
| 616 |
|
|
|
| 617 |
|
|
-- tx_pdata <= (others => '0');
|
| 618 |
|
|
-- load_uart_char <= '0';
|
| 619 |
|
|
-- read_uart_char <= '0';
|
| 620 |
|
|
-- next_banner_char <= '0';
|
| 621 |
|
|
-- load_banner_addres <= '0';
|
| 622 |
|
|
-- banner_address <= (others => '0');
|
| 623 |
|
|
-- cyc_o <= '0';
|
| 624 |
|
|
-- stb_o <= '0';
|
| 625 |
|
|
-- we_o <= '0';
|
| 626 |
|
|
-- lock_o <= '0';
|
| 627 |
|
|
-- leds <= "000011010";
|
| 628 |
|
|
APP_AF_WREN <= '0';
|
| 629 |
|
|
APP_WDF_WREN <= '0';
|
| 630 |
|
|
ack_access_in <= '0';
|
| 631 |
|
|
command <= "000";
|
| 632 |
|
|
-- next_mem_location <= '0';
|
| 633 |
|
|
-- load_new_addr <= '0';
|
| 634 |
|
|
-- new_addr <= (others => '0');
|
| 635 |
|
|
mask <= "00000000";
|
| 636 |
|
|
|
| 637 |
|
|
when acknowledge_access_0 =>
|
| 638 |
|
|
NextState_1 <= wait_13;
|
| 639 |
|
|
|
| 640 |
|
|
|
| 641 |
|
|
-- tx_pdata <= (others => '0');
|
| 642 |
|
|
-- load_uart_char <= '0';
|
| 643 |
|
|
-- read_uart_char <= '0';
|
| 644 |
|
|
-- next_banner_char <= '0';
|
| 645 |
|
|
-- load_banner_addres <= '0';
|
| 646 |
|
|
-- banner_address <= (others => '0');
|
| 647 |
|
|
-- cyc_o <= '0';
|
| 648 |
|
|
-- stb_o <= '0';
|
| 649 |
|
|
-- we_o <= '0';
|
| 650 |
|
|
-- lock_o <= '0';
|
| 651 |
|
|
-- leds <= "000011010";
|
| 652 |
|
|
APP_AF_WREN <= '0';
|
| 653 |
|
|
APP_WDF_WREN <= '0';
|
| 654 |
|
|
ack_access_in <= '1';
|
| 655 |
|
|
command <= "000";
|
| 656 |
|
|
-- next_mem_location <= '0';
|
| 657 |
|
|
-- load_new_addr <= '0';
|
| 658 |
|
|
-- new_addr <= (others => '0');
|
| 659 |
|
|
mask <= "00000000";
|
| 660 |
|
|
|
| 661 |
|
|
when wait_13 =>
|
| 662 |
|
|
NextState_1 <= wait_14;
|
| 663 |
|
|
|
| 664 |
|
|
|
| 665 |
|
|
-- tx_pdata <= (others => '0');
|
| 666 |
|
|
-- load_uart_char <= '0';
|
| 667 |
|
|
-- read_uart_char <= '0';
|
| 668 |
|
|
-- next_banner_char <= '0';
|
| 669 |
|
|
-- load_banner_addres <= '0';
|
| 670 |
|
|
-- banner_address <= (others => '0');
|
| 671 |
|
|
-- cyc_o <= '0';
|
| 672 |
|
|
-- stb_o <= '0';
|
| 673 |
|
|
-- we_o <= '0';
|
| 674 |
|
|
-- lock_o <= '0';
|
| 675 |
|
|
-- leds <= "000011010";
|
| 676 |
|
|
APP_AF_WREN <= '0';
|
| 677 |
|
|
APP_WDF_WREN <= '0';
|
| 678 |
|
|
ack_access_in <= '0';
|
| 679 |
|
|
command <= "000";
|
| 680 |
|
|
-- next_mem_location <= '0';
|
| 681 |
|
|
-- load_new_addr <= '0';
|
| 682 |
|
|
-- new_addr <= (others => '0');
|
| 683 |
|
|
mask <= "00000000";
|
| 684 |
|
|
|
| 685 |
|
|
when wait_14 =>
|
| 686 |
|
|
NextState_1 <= wait_15;
|
| 687 |
|
|
|
| 688 |
|
|
|
| 689 |
|
|
-- tx_pdata <= (others => '0');
|
| 690 |
|
|
-- load_uart_char <= '0';
|
| 691 |
|
|
-- read_uart_char <= '0';
|
| 692 |
|
|
-- next_banner_char <= '0';
|
| 693 |
|
|
-- load_banner_addres <= '0';
|
| 694 |
|
|
-- banner_address <= (others => '0');
|
| 695 |
|
|
-- cyc_o <= '0';
|
| 696 |
|
|
-- stb_o <= '0';
|
| 697 |
|
|
-- we_o <= '0';
|
| 698 |
|
|
-- lock_o <= '0';
|
| 699 |
|
|
-- leds <= "000011010";
|
| 700 |
|
|
APP_AF_WREN <= '0';
|
| 701 |
|
|
APP_WDF_WREN <= '0';
|
| 702 |
|
|
ack_access_in <= '0';
|
| 703 |
|
|
command <= "000";
|
| 704 |
|
|
-- next_mem_location <= '0';
|
| 705 |
|
|
-- load_new_addr <= '0';
|
| 706 |
|
|
-- new_addr <= (others => '0');
|
| 707 |
|
|
mask <= "00000000";
|
| 708 |
|
|
|
| 709 |
|
|
when wait_15 =>
|
| 710 |
|
|
NextState_1 <= wait_16;
|
| 711 |
|
|
|
| 712 |
|
|
|
| 713 |
|
|
-- tx_pdata <= (others => '0');
|
| 714 |
|
|
-- load_uart_char <= '0';
|
| 715 |
|
|
-- read_uart_char <= '0';
|
| 716 |
|
|
-- next_banner_char <= '0';
|
| 717 |
|
|
-- load_banner_addres <= '0';
|
| 718 |
|
|
-- banner_address <= (others => '0');
|
| 719 |
|
|
-- cyc_o <= '0';
|
| 720 |
|
|
-- stb_o <= '0';
|
| 721 |
|
|
-- we_o <= '0';
|
| 722 |
|
|
-- lock_o <= '0';
|
| 723 |
|
|
-- leds <= "000011010";
|
| 724 |
|
|
APP_AF_WREN <= '0';
|
| 725 |
|
|
APP_WDF_WREN <= '0';
|
| 726 |
|
|
ack_access_in <= '0';
|
| 727 |
|
|
command <= "000";
|
| 728 |
|
|
-- next_mem_location <= '0';
|
| 729 |
|
|
-- load_new_addr <= '0';
|
| 730 |
|
|
-- new_addr <= (others => '0');
|
| 731 |
|
|
mask <= "00000000";
|
| 732 |
|
|
|
| 733 |
|
|
when wait_16 =>
|
| 734 |
|
|
|
| 735 |
|
|
NextState_1 <= wait_arbitration;
|
| 736 |
|
|
|
| 737 |
|
|
|
| 738 |
|
|
-- tx_pdata <= (others => '0');
|
| 739 |
|
|
-- load_uart_char <= '0';
|
| 740 |
|
|
-- read_uart_char <= '0';
|
| 741 |
|
|
-- next_banner_char <= '0';
|
| 742 |
|
|
-- load_banner_addres <= '0';
|
| 743 |
|
|
-- banner_address <= (others => '0');
|
| 744 |
|
|
-- cyc_o <= '0';
|
| 745 |
|
|
-- stb_o <= '0';
|
| 746 |
|
|
-- we_o <= '0';
|
| 747 |
|
|
-- lock_o <= '0';
|
| 748 |
|
|
-- leds <= "000011010";
|
| 749 |
|
|
APP_AF_WREN <= '0';
|
| 750 |
|
|
APP_WDF_WREN <= '0';
|
| 751 |
|
|
ack_access_in <= '0';
|
| 752 |
|
|
command <= "000";
|
| 753 |
|
|
-- next_mem_location <= '0';
|
| 754 |
|
|
-- load_new_addr <= '0';
|
| 755 |
|
|
-- new_addr <= (others => '0');
|
| 756 |
|
|
mask <= "00000000";
|
| 757 |
|
|
|
| 758 |
|
|
when others =>
|
| 759 |
|
|
Nextstate_1 <= wait_arbitration;
|
| 760 |
|
|
-- tx_pdata <= (others => '0');
|
| 761 |
|
|
-- load_uart_char <= '0';
|
| 762 |
|
|
-- read_uart_char <= '0';
|
| 763 |
|
|
-- next_banner_char <= '0';
|
| 764 |
|
|
-- load_banner_addres <= '0';
|
| 765 |
|
|
-- banner_address <= (others => '0');
|
| 766 |
|
|
-- cyc_o <= '0';
|
| 767 |
|
|
-- stb_o <= '0';
|
| 768 |
|
|
-- we_o <= '0';
|
| 769 |
|
|
-- lock_o <= '0';
|
| 770 |
|
|
-- leds <= "000011010";
|
| 771 |
|
|
APP_AF_WREN <= '0';
|
| 772 |
|
|
APP_WDF_WREN <= '0';
|
| 773 |
|
|
ack_access_in <= '0';
|
| 774 |
|
|
command <= "000";
|
| 775 |
|
|
-- next_mem_location <= '0';
|
| 776 |
|
|
-- load_new_addr <= '0';
|
| 777 |
|
|
-- new_addr <= (others => '0');
|
| 778 |
|
|
mask <= "00000000";
|
| 779 |
|
|
|
| 780 |
|
|
end case;
|
| 781 |
|
|
end process;
|
| 782 |
|
|
|
| 783 |
|
|
currentstate_1logic: process
|
| 784 |
|
|
begin
|
| 785 |
|
|
wait until clock'EVENT and clock = '1'; --WAIT FOR RISING EDGE
|
| 786 |
|
|
-- INITIALIZATION
|
| 787 |
|
|
if (Reset = '1') then
|
| 788 |
|
|
CurrentState_1 <= wait_arbitration;
|
| 789 |
|
|
else
|
| 790 |
|
|
CurrentState_1 <= NextState_1;
|
| 791 |
|
|
end if;
|
| 792 |
|
|
end process currentstate_1logic;
|
| 793 |
|
|
|
| 794 |
|
|
|
| 795 |
|
|
end Behavioral;
|
| 796 |
|
|
|
