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[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [Memory Design/] [MIG.vhd] - Blame information for rev 24

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-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor             : Xilinx
-- \   \   \/    Version            : $Name: i+IP+131489 $
--  \   \        Application        : MIG
--  /   /        Filename           : MIG.vhd
-- /___/   /\    Date Last Modified : $Date: 2007/09/21 15:23:24 $
-- \   \  /  \   Date Created       : Mon May 2 2005
--  \___\/\___\
--
-- Device      : Virtex-4
-- Design Name : DDR SDRAM
-- Description: It is the top most module which interfaces with the system and
--              the memory.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use work.MIG_parameters_0.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG is
  port(
    cntrl0_ddr_dq                        : inout  std_logic_vector(31 downto 0);
    cntrl0_ddr_a                         : out  std_logic_vector(12 downto 0);
    cntrl0_ddr_ba                        : out  std_logic_vector(1 downto 0);
    cntrl0_ddr_cke                       : out std_logic;
    cntrl0_ddr_cs_n                      : out std_logic;
    cntrl0_ddr_ras_n                     : out std_logic;
    cntrl0_ddr_cas_n                     : out std_logic;
    cntrl0_ddr_we_n                      : out std_logic;
    cntrl0_ddr_dm                        : out  std_logic_vector(3 downto 0);
    sys_clk_p                            : in std_logic;
    sys_clk_n                            : in std_logic;
    clk200_p                             : in std_logic;
    clk200_n                             : in std_logic;
         clk_100_top                            : in std_logic;
         clk_200_top                            : in std_logic;
    init_done                            : out std_logic;
    sys_reset_in_n                       : in std_logic;
    cntrl0_clk_tb                        : out std_logic;
    cntrl0_reset_tb                      : out std_logic;
    cntrl0_wdf_almost_full               : out std_logic;
    cntrl0_af_almost_full                : out std_logic;
    cntrl0_read_data_valid               : out std_logic;
    cntrl0_app_wdf_wren                  : in std_logic;
    cntrl0_app_af_wren                   : in std_logic;
    cntrl0_burst_length_div2             : out  std_logic_vector(2 downto 0);
    cntrl0_app_af_addr                   : in  std_logic_vector(35 downto 0);
    cntrl0_app_wdf_data                  : in  std_logic_vector(63 downto 0);
    cntrl0_read_data_fifo_out            : out  std_logic_vector(63 downto 0);
    cntrl0_app_mask_data                 : in  std_logic_vector(7 downto 0);
    cntrl0_ddr_dqs                       : inout  std_logic_vector(3 downto 0);
    cntrl0_ddr_ck                        : out  std_logic_vector(1 downto 0);
    cntrl0_ddr_ck_n                      : out  std_logic_vector(1 downto 0)
         );
end MIG;
 
architecture arc_mem_interface_top of MIG is
 
  component MIG_top_0  port (
   ddr_dq                         : inout  std_logic_vector(31 downto 0);
   ddr_a                          : out  std_logic_vector(12 downto 0);
   ddr_ba                         : out  std_logic_vector(1 downto 0);
   ddr_cke                        : out std_logic;
   ddr_cs_n                       : out std_logic;
   ddr_ras_n                      : out std_logic;
   ddr_cas_n                      : out std_logic;
   ddr_we_n                       : out std_logic;
   ddr_dm                         : out  std_logic_vector(3 downto 0);
   init_done                      : out std_logic;
   clk_tb                         : out std_logic;
   reset_tb                       : out std_logic;
   wdf_almost_full                : out std_logic;
   af_almost_full                 : out std_logic;
   read_data_valid                : out std_logic;
   app_wdf_wren                   : in std_logic;
   app_af_wren                    : in std_logic;
   burst_length_div2              : out  std_logic_vector(2 downto 0);
   app_af_addr                    : in  std_logic_vector(35 downto 0);
   app_wdf_data                   : in  std_logic_vector(63 downto 0);
   read_data_fifo_out             : out  std_logic_vector(63 downto 0);
   app_mask_data                  : in  std_logic_vector(7 downto 0);
   ddr_dqs                        : inout  std_logic_vector(3 downto 0);
   ddr_ck                         : out  std_logic_vector(1 downto 0);
   ddr_ck_n                       : out  std_logic_vector(1 downto 0);
 
   clk_0                          : in std_logic;
   clk_90                         : in std_logic;
   sys_rst                        : in std_logic;
   sys_rst90                      : in std_logic;
   idelay_ctrl_rdy                : in std_logic
 
   );
end component;
 
  component MIG_infrastructure
    port(
      idelay_ctrl_rdy                : in std_logic;
      clk                            : out std_logic;
      clk90                          : out std_logic;
      clk200                         : out std_logic;
      sys_rst                        : out std_logic;
      sys_rst90                      : out std_logic;
      sys_rst_r1                     : out std_logic;
      sys_clk_p                      : in std_logic;
      sys_clk_n                      : in std_logic;
      clk200_p                       : in std_logic;
      clk200_n                       : in std_logic;
                clk_100_top                             : in std_logic;
                clk_200_top                             : in std_logic;
      sys_reset_in_n                 : in std_logic
      );
  end component;
 
  component MIG_idelay_ctrl
    port(
      clk200     : in  std_logic;
      reset      : in  std_logic;
      rdy_status : out std_logic
      );
  end component;
 
 
 
  signal clk_0           : std_logic;
  signal clk_90          : std_logic;
  signal clk_200         : std_logic;
  signal sys_rst         : std_logic;
  signal sys_rst90       : std_logic;
  signal idelay_ctrl_rdy : std_logic;
  signal sys_rst_r1      : std_logic;
 
  attribute syn_useioff : boolean ;
  attribute syn_useioff of arc_mem_interface_top : architecture is true;
 
begin
 
  top_00 :    MIG_top_0 port map (
   ddr_dq                         => cntrl0_ddr_dq,
   ddr_a                          => cntrl0_ddr_a,
   ddr_ba                         => cntrl0_ddr_ba,
   ddr_cke                        => cntrl0_ddr_cke,
   ddr_cs_n                       => cntrl0_ddr_cs_n,
   ddr_ras_n                      => cntrl0_ddr_ras_n,
   ddr_cas_n                      => cntrl0_ddr_cas_n,
   ddr_we_n                       => cntrl0_ddr_we_n,
   ddr_dm                         => cntrl0_ddr_dm,
   init_done                      => init_done,
   clk_tb                         => cntrl0_clk_tb,
   reset_tb                       => cntrl0_reset_tb,
   wdf_almost_full                => cntrl0_wdf_almost_full,
   af_almost_full                 => cntrl0_af_almost_full,
   read_data_valid                => cntrl0_read_data_valid,
   app_wdf_wren                   => cntrl0_app_wdf_wren,
   app_af_wren                    => cntrl0_app_af_wren,
   burst_length_div2              => cntrl0_burst_length_div2,
   app_af_addr                    => cntrl0_app_af_addr,
   app_wdf_data                   => cntrl0_app_wdf_data,
   read_data_fifo_out             => cntrl0_read_data_fifo_out,
   app_mask_data                  => cntrl0_app_mask_data,
   ddr_dqs                        => cntrl0_ddr_dqs,
   ddr_ck                         => cntrl0_ddr_ck,
   ddr_ck_n                       => cntrl0_ddr_ck_n,
 
   clk_0                          => clk_0,
   clk_90                         => clk_90,
   idelay_ctrl_rdy                => idelay_ctrl_rdy,
   sys_rst                        => sys_rst,
   sys_rst90                      => sys_rst90
   );
 
 
  infrastructure0 : MIG_infrastructure
    port map (
      clk                            => clk_0,
      clk90                          => clk_90,
      clk200                         => clk_200,
      idelay_ctrl_rdy                => idelay_ctrl_rdy,
      sys_rst                        => sys_rst,
      sys_rst90                      => sys_rst90,
      sys_rst_r1                     => sys_rst_r1,
      sys_clk_p                      => sys_clk_p,
      sys_clk_n                      => sys_clk_n,
      clk200_p                       => clk200_p,
      clk200_n                       => clk200_n,
                clk_100_top                             => clk_100_top,
                clk_200_top                             => clk_200_top,
 
      sys_reset_in_n                 => sys_reset_in_n
      );
 
  idelay_ctrl0 : MIG_idelay_ctrl
    port map (
      clk200     => clk_200,
      reset      => sys_rst_r1,
      rdy_status => idelay_ctrl_rdy
      );
 
end arc_mem_interface_top;

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Subversion Repositories the_wizardry_project

[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [Memory Design/] [MIG.vhd] - Blame information for rev 24

Line No.	Rev	Author	Line
1	24	mcwaccent	`-------------------------------------------------------------------------------`
2			`-- Copyright (c) 2005-2007 Xilinx, Inc.`
3			`-- This design is confidential and proprietary of Xilinx, All Rights Reserved.`
4			`-------------------------------------------------------------------------------`
5			`-- ____ ____`
6			`-- / /\/ /`
7			`-- /___/ \ / Vendor : Xilinx`
8			`-- \ \ \/ Version : $Name: i+IP+131489 $`
9			`-- \ \ Application : MIG`
10			`-- / / Filename : MIG.vhd`
11			`-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:24 $`
12			`-- \ \ / \ Date Created : Mon May 2 2005`
13			`-- \___\/\___\`
14			`--`
15			`-- Device : Virtex-4`
16			`-- Design Name : DDR SDRAM`
17			`-- Description: It is the top most module which interfaces with the system and`
18			`-- the memory.`
19			`-------------------------------------------------------------------------------`
20
21			`library ieee;`
22			`use ieee.std_logic_1164.all;`
23			`use work.MIG_parameters_0.all;`
24			`library UNISIM;`
25			`use UNISIM.vcomponents.all;`
26
27			`entity MIG is`
28			`port(`
29			`cntrl0_ddr_dq : inout std_logic_vector(31 downto 0);`
30			`cntrl0_ddr_a : out std_logic_vector(12 downto 0);`
31			`cntrl0_ddr_ba : out std_logic_vector(1 downto 0);`
32			`cntrl0_ddr_cke : out std_logic;`
33			`cntrl0_ddr_cs_n : out std_logic;`
34			`cntrl0_ddr_ras_n : out std_logic;`
35			`cntrl0_ddr_cas_n : out std_logic;`
36			`cntrl0_ddr_we_n : out std_logic;`
37			`cntrl0_ddr_dm : out std_logic_vector(3 downto 0);`
38			`sys_clk_p : in std_logic;`
39			`sys_clk_n : in std_logic;`
40			`clk200_p : in std_logic;`
41			`clk200_n : in std_logic;`
42			`clk_100_top : in std_logic;`
43			`clk_200_top : in std_logic;`
44			`init_done : out std_logic;`
45			`sys_reset_in_n : in std_logic;`
46			`cntrl0_clk_tb : out std_logic;`
47			`cntrl0_reset_tb : out std_logic;`
48			`cntrl0_wdf_almost_full : out std_logic;`
49			`cntrl0_af_almost_full : out std_logic;`
50			`cntrl0_read_data_valid : out std_logic;`
51			`cntrl0_app_wdf_wren : in std_logic;`
52			`cntrl0_app_af_wren : in std_logic;`
53			`cntrl0_burst_length_div2 : out std_logic_vector(2 downto 0);`
54			`cntrl0_app_af_addr : in std_logic_vector(35 downto 0);`
55			`cntrl0_app_wdf_data : in std_logic_vector(63 downto 0);`
56			`cntrl0_read_data_fifo_out : out std_logic_vector(63 downto 0);`
57			`cntrl0_app_mask_data : in std_logic_vector(7 downto 0);`
58			`cntrl0_ddr_dqs : inout std_logic_vector(3 downto 0);`
59			`cntrl0_ddr_ck : out std_logic_vector(1 downto 0);`
60			`cntrl0_ddr_ck_n : out std_logic_vector(1 downto 0)`
61			`);`
62			`end MIG;`
63
64			`architecture arc_mem_interface_top of MIG is`
65
66			`component MIG_top_0 port (`
67			`ddr_dq : inout std_logic_vector(31 downto 0);`
68			`ddr_a : out std_logic_vector(12 downto 0);`
69			`ddr_ba : out std_logic_vector(1 downto 0);`
70			`ddr_cke : out std_logic;`
71			`ddr_cs_n : out std_logic;`
72			`ddr_ras_n : out std_logic;`
73			`ddr_cas_n : out std_logic;`
74			`ddr_we_n : out std_logic;`
75			`ddr_dm : out std_logic_vector(3 downto 0);`
76			`init_done : out std_logic;`
77			`clk_tb : out std_logic;`
78			`reset_tb : out std_logic;`
79			`wdf_almost_full : out std_logic;`
80			`af_almost_full : out std_logic;`
81			`read_data_valid : out std_logic;`
82			`app_wdf_wren : in std_logic;`
83			`app_af_wren : in std_logic;`
84			`burst_length_div2 : out std_logic_vector(2 downto 0);`
85			`app_af_addr : in std_logic_vector(35 downto 0);`
86			`app_wdf_data : in std_logic_vector(63 downto 0);`
87			`read_data_fifo_out : out std_logic_vector(63 downto 0);`
88			`app_mask_data : in std_logic_vector(7 downto 0);`
89			`ddr_dqs : inout std_logic_vector(3 downto 0);`
90			`ddr_ck : out std_logic_vector(1 downto 0);`
91			`ddr_ck_n : out std_logic_vector(1 downto 0);`
92
93			`clk_0 : in std_logic;`
94			`clk_90 : in std_logic;`
95			`sys_rst : in std_logic;`
96			`sys_rst90 : in std_logic;`
97			`idelay_ctrl_rdy : in std_logic`
98
99			`);`
100			`end component;`
101
102			`component MIG_infrastructure`
103			`port(`
104			`idelay_ctrl_rdy : in std_logic;`
105			`clk : out std_logic;`
106			`clk90 : out std_logic;`
107			`clk200 : out std_logic;`
108			`sys_rst : out std_logic;`
109			`sys_rst90 : out std_logic;`
110			`sys_rst_r1 : out std_logic;`
111			`sys_clk_p : in std_logic;`
112			`sys_clk_n : in std_logic;`
113			`clk200_p : in std_logic;`
114			`clk200_n : in std_logic;`
115			`clk_100_top : in std_logic;`
116			`clk_200_top : in std_logic;`
117			`sys_reset_in_n : in std_logic`
118			`);`
119			`end component;`
120
121			`component MIG_idelay_ctrl`
122			`port(`
123			`clk200 : in std_logic;`
124			`reset : in std_logic;`
125			`rdy_status : out std_logic`
126			`);`
127			`end component;`
128
129
130
131			`signal clk_0 : std_logic;`
132			`signal clk_90 : std_logic;`
133			`signal clk_200 : std_logic;`
134			`signal sys_rst : std_logic;`
135			`signal sys_rst90 : std_logic;`
136			`signal idelay_ctrl_rdy : std_logic;`
137			`signal sys_rst_r1 : std_logic;`
138
139			`attribute syn_useioff : boolean ;`
140			`attribute syn_useioff of arc_mem_interface_top : architecture is true;`
141
142			`begin`
143
144			`top_00 : MIG_top_0 port map (`
145			`ddr_dq => cntrl0_ddr_dq,`
146			`ddr_a => cntrl0_ddr_a,`
147			`ddr_ba => cntrl0_ddr_ba,`
148			`ddr_cke => cntrl0_ddr_cke,`
149			`ddr_cs_n => cntrl0_ddr_cs_n,`
150			`ddr_ras_n => cntrl0_ddr_ras_n,`
151			`ddr_cas_n => cntrl0_ddr_cas_n,`
152			`ddr_we_n => cntrl0_ddr_we_n,`
153			`ddr_dm => cntrl0_ddr_dm,`
154			`init_done => init_done,`
155			`clk_tb => cntrl0_clk_tb,`
156			`reset_tb => cntrl0_reset_tb,`
157			`wdf_almost_full => cntrl0_wdf_almost_full,`
158			`af_almost_full => cntrl0_af_almost_full,`
159			`read_data_valid => cntrl0_read_data_valid,`
160			`app_wdf_wren => cntrl0_app_wdf_wren,`
161			`app_af_wren => cntrl0_app_af_wren,`
162			`burst_length_div2 => cntrl0_burst_length_div2,`
163			`app_af_addr => cntrl0_app_af_addr,`
164			`app_wdf_data => cntrl0_app_wdf_data,`
165			`read_data_fifo_out => cntrl0_read_data_fifo_out,`
166			`app_mask_data => cntrl0_app_mask_data,`
167			`ddr_dqs => cntrl0_ddr_dqs,`
168			`ddr_ck => cntrl0_ddr_ck,`
169			`ddr_ck_n => cntrl0_ddr_ck_n,`
170
171			`clk_0 => clk_0,`
172			`clk_90 => clk_90,`
173			`idelay_ctrl_rdy => idelay_ctrl_rdy,`
174			`sys_rst => sys_rst,`
175			`sys_rst90 => sys_rst90`
176			`);`
177
178
179			`infrastructure0 : MIG_infrastructure`
180			`port map (`
181			`clk => clk_0,`
182			`clk90 => clk_90,`
183			`clk200 => clk_200,`
184			`idelay_ctrl_rdy => idelay_ctrl_rdy,`
185			`sys_rst => sys_rst,`
186			`sys_rst90 => sys_rst90,`
187			`sys_rst_r1 => sys_rst_r1,`
188			`sys_clk_p => sys_clk_p,`
189			`sys_clk_n => sys_clk_n,`
190			`clk200_p => clk200_p,`
191			`clk200_n => clk200_n,`
192			`clk_100_top => clk_100_top,`
193			`clk_200_top => clk_200_top,`
194
195			`sys_reset_in_n => sys_reset_in_n`
196			`);`
197
198			`idelay_ctrl0 : MIG_idelay_ctrl`
199			`port map (`
200			`clk200 => clk_200,`
201			`reset => sys_rst_r1,`
202			`rdy_status => idelay_ctrl_rdy`
203			`);`
204
205			`end arc_mem_interface_top;`