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[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [Memory Design/] [MIG_top_00/] [MIG_data_path_0/] [MIG_tap_logic/] [MIG_data_tap_inc.vhd] - Blame information for rev 24

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1 24 mcwaccent 
-------------------------------------------------------------------------------
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-- Copyright (c) 2005-2007 Xilinx, Inc.
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-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
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-------------------------------------------------------------------------------
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--   ____  ____
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--  /   /\/   /
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-- /___/  \  /   Vendor             : Xilinx
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-- \   \   \/    Version            : $Name: i+IP+131489 $
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--  \   \        Application        : MIG
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--  /   /        Filename           : MIG_data_tap_inc.vhd
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-- /___/   /\    Date Last Modified : $Date: 2007/09/21 15:23:24 $
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-- \   \  /  \   Date Created       : Mon May 2 2005
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--  \___\/\___\
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--
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-- Device      : Virtex-4
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-- Design Name : DDR SDRAM
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-- Description: The tap logic for calibration of the memory data with respect
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--              to FPGA clock is provided here. According to the edge detection
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--              or not the taps in the IDELAY element of the Virtex4 devices
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--              are either increased or decreased.
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library UNISIM;
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use UNISIM.vcomponents.all;
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entity MIG_data_tap_inc is
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  port(
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    clk                  : in  std_logic;
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    reset                : in  std_logic;
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    data_dlyinc          : out std_logic;
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    data_dlyce           : out std_logic;
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    data_dlyrst          : out std_logic;
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    data_tap_sel_done    : out std_logic;
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    dqs_sel_done         : in  std_logic;
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    valid_data_tap_count : in  std_logic;
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    data_tap_count       : in  std_logic_vector(5 downto 0)
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    );
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end MIG_data_tap_inc;
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architecture arch of MIG_data_tap_inc is
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  signal data_dlyinc_clk0       : std_logic;
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  signal data_dlyce_clk0        : std_logic;
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  signal data_dlyrst_clk0       : std_logic;
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  signal data_tap_inc_counter   : std_logic_vector(5 downto 0) := "000000";
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  signal data_tap_sel_clk       : std_logic;
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  signal data_tap_sel_r1        : std_logic;
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  signal dqs_sel_done_r         : std_logic;
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  signal valid_data_tap_count_r : std_logic;
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  signal rst_r                  : std_logic;
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begin
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  data_tap_sel_done <= data_tap_sel_r1;
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  data_dlyinc       <= data_dlyinc_clk0;
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  data_dlyce        <= data_dlyce_clk0;
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  data_dlyrst       <= data_dlyrst_clk0;
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  process(clk)
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  begin
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    if(clk'event and clk = '1') then
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      rst_r <= reset;
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    end if;
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  end process;
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  process(clk)
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  begin
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    if(clk'event and clk = '1') then
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      if(rst_r = '1') then
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        data_tap_sel_clk <= '0';
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      elsif(data_tap_inc_counter = "000001") then
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        data_tap_sel_clk <= '1';
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      end if;
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    end if;
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  end process;
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  process(clk)
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  begin
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    if(clk'event and clk = '1') then
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      if(rst_r = '1') then
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        data_tap_sel_r1 <= '0';
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      else
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        data_tap_sel_r1 <= data_tap_sel_clk;
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      end if;
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    end if;
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  end process;
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  process(clk)
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  begin
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    if(clk'event and clk = '1') then
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      if(rst_r = '1') then
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        dqs_sel_done_r <= '0';
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      elsif(dqs_sel_done = '1') then
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        dqs_sel_done_r <= '1';
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      end if;
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    end if;
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  end process;
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  process(clk)
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  begin
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    if(clk'event and clk = '1') then
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      if(rst_r = '1') then
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        valid_data_tap_count_r <= '0';
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      else
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        valid_data_tap_count_r <= valid_data_tap_count;
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      end if;
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    end if;
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  end process;
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  process(clk)
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  begin
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    if(clk'event and clk = '1') then
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      if(rst_r = '1' or dqs_sel_done_r = '0') then
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        data_dlyinc_clk0     <= '0';
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        data_dlyce_clk0      <= '0';
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        data_dlyrst_clk0     <= '1';
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        data_tap_inc_counter <= "000000";
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      elsif(valid_data_tap_count_r = '1') then
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        data_dlyinc_clk0     <= '0';
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        data_dlyce_clk0      <= '0';
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        data_dlyrst_clk0     <= '0';
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        data_tap_inc_counter <= data_tap_count;
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      elsif(data_tap_inc_counter /= "000000") then  -- Data IDELAY incremented
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        data_dlyinc_clk0     <= '1';
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        data_dlyce_clk0      <= '1';
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        data_dlyrst_clk0     <= '0';
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        data_tap_inc_counter <= data_tap_inc_counter - '1';
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      else                              -- Data IDELAY no change mode
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        data_dlyinc_clk0     <= '0';
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        data_dlyce_clk0      <= '0';
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        data_dlyrst_clk0     <= '0';
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        data_tap_inc_counter <= "000000";
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      end if;
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    end if;
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  end process;
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end arch;

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