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[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [Memory Design/] [MIG_top_00/] [MIG_ddr_controller_0.vhd] - Blame information for rev 24

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1 24 mcwaccent 
-------------------------------------------------------------------------------
2 
-- Copyright (c) 2005-2007 Xilinx, Inc.
3 
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
4 
-------------------------------------------------------------------------------
5 
--   ____  ____
6 
--  /   /\/   /
7 
-- /___/  \  /   Vendor             : Xilinx
8 
-- \   \   \/    Version            : $Name: i+IP+131489 $
9 
--  \   \        Application        : MIG
10 
--  /   /        Filename           : MIG_ddr_controller_0.vhd
11 
-- /___/   /\    Date Last Modified : $Date: 2007/09/21 15:23:24 $
12 
-- \   \  /  \   Date Created       : Mon May 2 2005
13 
--  \___\/\___\
14 
--
15 
-- Device      : Virtex-4
16 
-- Design Name : DDR SDRAM
17 
-- Description: This is the main control logic of the memory interface. All
18 
--              commands are issued from here acoording to the burst, CAS
19 
--              Latency and the user commands.
20 
-------------------------------------------------------------------------------
21 
 
22 
library ieee;
23 
use ieee.std_logic_1164.all;
24 
use ieee.std_logic_unsigned.all;
25 
use work.MIG_parameters_0.all;
26 
library UNISIM;
27 
use UNISIM.vcomponents.all;
28 
 
29 
entity MIG_ddr_controller_0 is
30 
  port(
31 
    clk_0                : in  std_logic;
32 
    rst                  : in  std_logic;
33 
    -- FIFO  signals
34 
    af_addr              : in  std_logic_vector(35 downto 0);
35 
    af_empty             : in  std_logic;
36 
    --  signals for the Dummy Reads
37 
    comp_done            : in  std_logic;
38 
    phy_dly_slct_done    : in  std_logic;
39 
    ctrl_dummyread_start : out std_logic;
40 
    -- FIFO read enable signals
41 
    ctrl_af_rden         : out std_logic;
42 
    ctrl_wdf_rden        : out std_logic;
43 
    -- Rst and Enable signals for DQS logic
44 
    ctrl_dqs_rst         : out std_logic;
45 
    ctrl_dqs_en          : out std_logic;
46 
    -- Read and Write Enable signals to the phy interface
47 
    ctrl_wren            : out std_logic;
48 
    ctrl_rden            : out std_logic;
49 
    --
50 
    ctrl_ddr_address     : out std_logic_vector((ROW_ADDRESS - 1) downto 0);
51 
    ctrl_ddr_ba          : out std_logic_vector((BANK_ADDRESS - 1) downto 0);
52 
    ctrl_ddr_ras_l       : out std_logic;
53 
    ctrl_ddr_cas_l       : out std_logic;
54 
    ctrl_ddr_we_l        : out std_logic;
55 
    ctrl_ddr_cs_l        : out std_logic;
56 
    ctrl_ddr_cke         : out std_logic;
57 
    init_done            : out std_logic;
58 
    dummy_write_pattern  : out std_logic;
59 
    burst_length_div2    : out std_logic_vector(2 downto 0)
60 
    );
61 
end MIG_ddr_controller_0;
62 
 
63 
architecture arch of MIG_ddr_controller_0 is
64 
 
65 
  signal init_count              : std_logic_vector(3 downto 0);
66 
  signal init_count_cp           : std_logic_vector(3 downto 0);
67 
  signal init_memory             : std_logic;
68 
  signal count_200_cycle         : std_logic_vector(7 downto 0);
69 
  signal ref_flag                : std_logic;
70 
  signal ref_flag_0            : std_logic;
71 
  signal ref_flag_0_r          : std_logic;
72 
  signal auto_ref                : std_logic;
73 
  signal next_state              : std_logic_vector(4 downto 0);
74 
  signal state                   : std_logic_vector(4 downto 0);
75 
  signal state_r2                : std_logic_vector(4 downto 0);
76 
  signal row_addr_r              : std_logic_vector((ROW_ADDRESS - 1) downto 0);
77 
  signal ddr_address_init_r      : std_logic_vector((ROW_ADDRESS - 1) downto 0);
78 
  signal ddr_address_r1          : std_logic_vector((ROW_ADDRESS - 1) downto 0);
79 
  signal ddr_address_bl          : std_logic_vector((ROW_ADDRESS - 1) downto 0);
80 
  signal ddr_ba_r1               : std_logic_vector((BANK_ADDRESS - 1) downto 0);
81 
  signal mrd_count               : std_logic;
82 
  signal rp_count                : std_logic_vector(2 downto 0);
83 
  signal rfc_count               : std_logic_vector(5 downto 0);
84 
  signal rcd_count               : std_logic_vector(2 downto 0);
85 
  signal ras_count               : std_logic_vector(3 downto 0);
86 
  signal wr_to_rd_count          : std_logic_vector(3 downto 0);
87 
  signal rd_to_wr_count          : std_logic_vector(3 downto 0);
88 
  signal rtp_count               : std_logic_vector(3 downto 0);
89 
  signal wtp_count               : std_logic_vector(3 downto 0);
90 
  signal refi_count              : std_logic_vector((MAX_REF_WIDTH - 1) downto 0);
91 
  signal cas_count               : std_logic_vector(2 downto 0);
92 
  signal cas_check_count         : std_logic_vector(3 downto 0);
93 
  signal wrburst_cnt             : std_logic_vector(2 downto 0);
94 
  signal read_burst_cnt          : std_logic_vector(2 downto 0);
95 
  signal ctrl_wren_cnt           : std_logic_vector(2 downto 0);
96 
  signal rdburst_cnt             : std_logic_vector(2 downto 0);
97 
  signal af_addr_r               : std_logic_vector(35 downto 0);
98 
  signal wdf_rden_r              : std_logic;
99 
  signal wdf_rden_r2             : std_logic;
100 
  signal wdf_rden_r3             : std_logic;
101 
  signal wdf_rden_r4             : std_logic;
102 
  signal af_rden                 : std_logic;
103 
  signal ddr_ras_r2              : std_logic;
104 
  signal ddr_cas_r2              : std_logic;
105 
  signal ddr_we_r2               : std_logic;
106 
  signal ddr_ras_r               : std_logic;
107 
  signal ddr_cas_r               : std_logic;
108 
  signal ddr_we_r                : std_logic;
109 
  signal ddr_ras_r3              : std_logic;
110 
  signal ddr_cas_r3              : std_logic;
111 
  signal ddr_we_r3               : std_logic;
112 
  signal idle_cnt                : std_logic_vector(3 downto 0);
113 
  signal ctrl_dummyread_start_r1 : std_logic;
114 
  signal ctrl_dummyread_start_r2 : std_logic;
115 
  signal ctrl_dummyread_start_r3 : std_logic;
116 
  signal ctrl_dummyread_start_r4 : std_logic;
117 
  signal conflict_resolved_r     : std_logic;
118 
  signal ddr_cke_r               : std_logic;
119 
  signal chip_cnt                : std_logic_vector(1 downto 0);
120 
  signal dummy_read_en           : std_logic;
121 
  signal ctrl_init_done          : std_logic;
122 
  signal count_200cycle_done_r   : std_logic;
123 
  signal init_done_int           : std_logic;
124 
  signal burst_cnt               : std_logic_vector(3 downto 0);
125 
  signal burst_cnt_by2           : std_logic_vector(2 downto 0);
126 
  signal conflict_detect         : std_logic;
127 
  signal conflict_detect_r       : std_logic;
128 
  signal load_mode_reg           : std_logic_vector((ROW_ADDRESS - 1) downto 0);
129 
  signal ext_mode_reg            : std_logic_vector((ROW_ADDRESS - 1) downto 0);
130 
  signal cas_latency_value       : std_logic_vector(3 downto 0);
131 
  signal burst_length_value      : std_logic_vector(2 downto 0);
132 
  signal registered_dimm        : std_logic;
133 
  signal wr                      : std_logic;
134 
  signal rd                      : std_logic;
135 
  signal lmr                     : std_logic;
136 
  signal pre                     : std_logic;
137 
  signal ref                     : std_logic;
138 
  signal act                     : std_logic;
139 
  signal wr_r                    : std_logic;
140 
  signal rd_r                    : std_logic;
141 
  signal lmr_r                   : std_logic;
142 
  signal pre_r                   : std_logic;
143 
  signal ref_r                   : std_logic;
144 
  signal act_r                   : std_logic;
145 
  signal af_empty_r              : std_logic;
146 
  signal lmr_pre_ref_act_cmd_r   : std_logic;
147 
  signal command_address         : std_logic_vector(2 downto 0);
148 
  signal cke_200us_cnt           : std_logic_vector(4 downto 0);
149 
  signal done_200us              : std_logic;
150 
  signal write_state             : std_logic;
151 
  signal read_state              : std_logic;
152 
  signal read_write_state        : std_logic;
153 
  signal burst_write_state       : std_logic;
154 
  signal first_write_state       : std_logic;
155 
  signal burst_read_state        : std_logic;
156 
  signal first_read_state        : std_logic;
157 
  signal burst_read_state_r2     : std_logic;
158 
  signal burst_read_state_r3     : std_logic;
159 
  signal first_read_state_r2     : std_logic;
160 
  signal read_write_state_r2     : std_logic;
161 
  signal dummy_write_state       : std_logic;
162 
  signal dummy_write_state_r     : std_logic;
163 
  signal pattern_read_state      : std_logic;
164 
  signal pattern_read_state_1    : std_logic;
165 
  signal pattern_read_state_r2   : std_logic;
166 
  signal pattern_read_state_r3   : std_logic;
167 
  signal pattern_read_state_1_r2 : std_logic;
168 
  signal dummy_write_flag        : std_logic;
169 
  signal rst_r                   : std_logic;
170 
  signal ctrl_wdf_rden_r         : std_logic;
171 
  signal ctrl_wdf_rden_r1        : std_logic;
172 
  signal ctrl_dqs_rst_r          : std_logic;
173 
  signal ctrl_dqs_rst_r1         : std_logic;
174 
  signal ctrl_wren_r             : std_logic;
175 
  signal ctrl_wren_r1            : std_logic;
176 
  signal ctrl_rden_r             : std_logic;
177 
  signal ctrl_rden_r1            : std_logic;
178 
  signal ctrl_dqs_en_r           : std_logic;
179 
  signal ctrl_dqs_en_r1          : std_logic;
180 
  signal dummy_write_pattern_1   : std_logic;
181 
  signal dummy_write_pattern_2   : std_logic;
182 
  signal ddr_address_r2          : std_logic_vector((ROW_ADDRESS - 1) downto 0);
183 
  signal ddr_ba_r2               : std_logic_vector((BANK_ADDRESS - 1) downto 0);
184 
  signal init_next_state         : std_logic_vector(4 downto 0);
185 
  signal init_state              : std_logic_vector(4 downto 0);
186 
  signal init_state_r2           : std_logic_vector(4 downto 0);
187 
  signal count5                  : std_logic_vector(4 downto 0);
188 
 
189 
  constant IDLE               : std_logic_vector(4 downto 0) := "00000";  --5'h00
190 
  constant LOAD_MODE_REG_ST   : std_logic_vector(4 downto 0) := "00001";  --5'h01
191 
  constant MODE_REGISTER_WAIT : std_logic_vector(4 downto 0) := "00010";  --5'h02
192 
  constant PRECHARGE          : std_logic_vector(4 downto 0) := "00011";  --5'h03
193 
  constant PRECHARGE_WAIT     : std_logic_vector(4 downto 0) := "00100";  --5'h04
194 
  constant AUTO_REFRESH       : std_logic_vector(4 downto 0) := "00101";  --5'h05
195 
  constant AUTO_REFRESH_WAIT  : std_logic_vector(4 downto 0) := "00110";  --5'h06
196 
  constant ACTIVE             : std_logic_vector(4 downto 0) := "00111";  --5'h07
197 
  constant ACTIVE_WAIT        : std_logic_vector(4 downto 0) := "01000";  --5'h08
198 
  constant FIRST_WRITE        : std_logic_vector(4 downto 0) := "01001";  --5'h09
199 
  constant BURST_WRITE        : std_logic_vector(4 downto 0) := "01010";  --5'h0A
200 
  constant WRITE_WAIT         : std_logic_vector(4 downto 0) := "01011";  --5'h0B
201 
  constant WRITE_READ         : std_logic_vector(4 downto 0) := "01100";  --5'h0C
202 
  constant FIRST_READ         : std_logic_vector(4 downto 0) := "01101";  --5'h0D
203 
  constant BURST_READ         : std_logic_vector(4 downto 0) := "01110";  --5'h0E
204 
  constant READ_WAIT          : std_logic_vector(4 downto 0) := "01111";  --5'h0F
205 
  constant READ_WRITE         : std_logic_vector(4 downto 0) := "10000";  --5'h10
206 
 
207 
  constant INIT_IDLE               : std_logic_vector(4 downto 0) := "00000";
208 
  constant INIT_DEEP_MEMORY_ST     : std_logic_vector(4 downto 0) := "00001";
209 
  constant INIT_INITCOUNT_200      : std_logic_vector(4 downto 0) := "00010";
210 
  constant INIT_INITCOUNT_200_WAIT : std_logic_vector(4 downto 0) := "00011";
211 
  constant INIT_DUMMY_READ_CYCLES  : std_logic_vector(4 downto 0) := "00100";
212 
  constant INIT_DUMMY_ACTIVE       : std_logic_vector(4 downto 0) := "00101";
213 
  constant INIT_DUMMY_ACTIVE_WAIT  : std_logic_vector(4 downto 0) := "00110";
214 
  constant INIT_DUMMY_FIRST_READ   : std_logic_vector(4 downto 0) := "00111";
215 
  constant INIT_DUMMY_READ         : std_logic_vector(4 downto 0) := "01000";
216 
  constant INIT_DUMMY_READ_WAIT    : std_logic_vector(4 downto 0) := "01001";
217 
  constant INIT_DUMMY_WRITE1       : std_logic_vector(4 downto 0) := "01010";
218 
  constant INIT_DUMMY_WRITE2       : std_logic_vector(4 downto 0) := "01011";
219 
  constant INIT_DUMMY_WRITE_READ   : std_logic_vector(4 downto 0) := "01100";
220 
  constant INIT_PATTERN_READ1      : std_logic_vector(4 downto 0) := "01101";
221 
  constant INIT_PATTERN_READ2      : std_logic_vector(4 downto 0) := "01110";
222 
  constant INIT_PATTERN_READ_WAIT  : std_logic_vector(4 downto 0) := "01111";
223 
  constant INIT_PRECHARGE          : std_logic_vector(4 downto 0) := "10000";
224 
  constant INIT_PRECHARGE_WAIT     : std_logic_vector(4 downto 0) := "10001";
225 
  constant INIT_AUTO_REFRESH       : std_logic_vector(4 downto 0) := "10010";
226 
  constant INIT_AUTO_REFRESH_WAIT  : std_logic_vector(4 downto 0) := "10011";
227 
  constant INIT_LOAD_MODE_REG_ST   : std_logic_vector(4 downto 0) := "10100";
228 
  constant INIT_MODE_REGISTER_WAIT : std_logic_vector(4 downto 0) := "10101";
229 
 
230 
  constant cntnext : std_logic_vector(4 downto 0) := "11000";
231 
 
232 
attribute syn_preserve : boolean;
233 
attribute syn_preserve of arch : architecture is true;
234 
 
235 
begin
236 
 
237 
 
238 
 
239 
 registered_dimm <= '0';
240 
 
241 
 
242 
  cas_latency_value <= "0010" when (load_mode_reg(6 downto 4) = "110") else
243 
                       '0' & load_mode_reg(6 downto 4);
244 
  burst_length_value <= load_mode_reg(2 downto 0);
245 
  burst_length_div2  <= burst_cnt(2 downto 0);
246 
  command_address    <= af_addr(34 downto 32);
247 
 
248 
  burst_read_state <= '1' when ((conflict_detect = '0') or (conflict_resolved_r = '1'))
249 
                       and (state = BURST_READ) and (rd = '1') else '0';
250 
  first_read_state <= '1' when ((conflict_detect = '0') or (conflict_resolved_r = '1'))
251 
                       and (state = FIRST_READ) and (rd = '1') else '0';
252 
  read_state        <= burst_read_state or first_read_state;
253 
  read_write_state  <= write_state or read_state;
254 
  burst_write_state <= '1' when ((conflict_detect = '0') or (conflict_resolved_r = '1'))
255 
                       and (state = BURST_WRITE) and (wr = '1') else '0';
256 
  first_write_state <= '1' when ((conflict_detect = '0') or (conflict_resolved_r = '1'))
257 
                       and (state = FIRST_WRITE) and (wr = '1') else '0';
258 
  write_state <= burst_write_state or first_write_state;
259 
 
260 
  dummy_write_state <= '1' when ((init_state = INIT_DUMMY_WRITE1) or
261 
                                     (init_state = INIT_DUMMY_WRITE2))
262 
                           else '0';
263 
  dummy_write_pattern_1 <= '1' when ((init_state = INIT_DUMMY_WRITE1) or
264 
                                     (init_state = INIT_DUMMY_WRITE2) or
265 
                                     (init_state = INIT_DUMMY_WRITE_READ)) else '0';
266 
  pattern_read_state <= '1' when ((init_state = INIT_PATTERN_READ1) or
267 
                                     (init_state = INIT_PATTERN_READ2))
268 
                           else '0';
269 
  pattern_read_state_1 <= '1' when (init_state = INIT_PATTERN_READ1) else '0';
270 
 
271 
  process(clk_0)
272 
  begin
273 
    if(clk_0'event and clk_0 = '1') then
274 
      rst_r <= rst;
275 
    end if;
276 
  end process;
277 
 
278 
  process(clk_0)
279 
  begin
280 
    if(clk_0'event and clk_0 = '1') then
281 
      if(rst_r = '1') then
282 
        dummy_write_pattern_2 <= '0';
283 
      else
284 
        dummy_write_pattern_2 <= dummy_write_pattern_1;
285 
      end if;
286 
    end if;
287 
  end process;
288 
 
289 
  dummy_write_pattern <= dummy_write_pattern_2 when (registered_dimm = '1')
290 
                         else dummy_write_pattern_1;
291 
 
292 
-- fifo control signals
293 
 
294 
  ctrl_af_rden <= af_rden;
295 
 
296 
  conflict_detect <= af_addr(35) and ctrl_init_done and (not af_empty);
297 
 
298 
  process(clk_0)
299 
  begin
300 
    if(clk_0'event and clk_0 = '1') then
301 
      if(rst_r = '1') then
302 
        pattern_read_state_r2 <= '0';
303 
        pattern_read_state_r3 <= '0';
304 
      else
305 
        pattern_read_state_r2 <= pattern_read_state;
306 
        pattern_read_state_r3 <= pattern_read_state_r2;
307 
      end if;
308 
    end if;
309 
  end process;
310 
 
311 
  process(clk_0)
312 
  begin
313 
    if(clk_0'event and clk_0 = '1') then
314 
      if(rst_r = '1') then
315 
        pattern_read_state_1_r2 <= '0';
316 
      else
317 
        pattern_read_state_1_r2 <= pattern_read_state_1;
318 
      end if;
319 
    end if;
320 
  end process;
321 
 
322 
  process(clk_0)
323 
  begin
324 
    if(clk_0'event and clk_0 = '1') then
325 
      if(rst_r = '1') then
326 
        dummy_write_state_r <= '0';
327 
      else
328 
        dummy_write_state_r <= dummy_write_state;
329 
      end if;
330 
    end if;
331 
  end process;
332 
 
333 
--commands
334 
 
335 
  process(command_address, ctrl_init_done, af_empty)
336 
  begin
337 
    wr  <= '0';
338 
    rd  <= '0';
339 
    lmr <= '0';
340 
    pre <= '0';
341 
    ref <= '0';
342 
    act <= '0';
343 
    if((ctrl_init_done = '1') and (af_empty = '0')) then
344 
      case command_address is
345 
        when "000"  => lmr <= '1';
346 
        when "001"  => ref <= '1';
347 
        when "010"  => pre <= '1';
348 
        when "011"  => act <= '1';
349 
        when "100"  => wr  <= '1';
350 
        when "101"  => rd  <= '1';
351 
        when others => null;
352 
      end case;
353 
    end if;
354 
  end process;
355 
 
356 
-- register address outputs
357 
  process (clk_0)
358 
  begin
359 
    if(clk_0'event and clk_0 = '1') then
360 
      if(rst_r = '1') then
361 
        wr_r                  <= '0';
362 
        rd_r                  <= '0';
363 
        lmr_r                 <= '0';
364 
        pre_r                 <= '0';
365 
        ref_r                 <= '0';
366 
        act_r                 <= '0';
367 
        af_empty_r            <= '0';
368 
        lmr_pre_ref_act_cmd_r <= '0';
369 
      else
370 
        wr_r                  <= wr;
371 
        rd_r                  <= rd;
372 
        lmr_r                 <= lmr;
373 
        pre_r                 <= pre;
374 
        ref_r                 <= ref;
375 
        act_r                 <= act;
376 
        lmr_pre_ref_act_cmd_r <= lmr or pre or ref or act;
377 
        af_empty_r            <= af_empty;
378 
      end if;
379 
    end if;
380 
  end process;
381 
 
382 
 
383 
-- register address outputs
384 
  process (clk_0)
385 
  begin
386 
    if(clk_0'event and clk_0 = '1') then
387 
      if(rst_r = '1') then
388 
        af_addr_r           <= (others => '0');
389 
        conflict_detect_r   <= '0';
390 
        read_write_state_r2 <= '0';
391 
        first_read_state_r2 <= '0';
392 
        burst_read_state_r2 <= '0';
393 
        burst_read_state_r3 <= '0';
394 
      else
395 
        af_addr_r           <= af_addr;
396 
        conflict_detect_r   <= conflict_detect;
397 
        read_write_state_r2 <= read_write_state;
398 
        first_read_state_r2 <= first_read_state;
399 
        burst_read_state_r2 <= burst_read_state;
400 
        burst_read_state_r3 <= burst_read_state_r2;
401 
      end if;
402 
    end if;
403 
  end process;
404 
 
405 
 
406 
  process (clk_0)
407 
  begin
408 
    if(clk_0'event and clk_0 = '1') then
409 
      if(rst_r = '1') then
410 
        load_mode_reg <= LOAD_MODE_REGISTER((ROW_ADDRESS - 1) downto 0);
411 
      elsif((state = LOAD_MODE_REG_ST or init_state = INIT_LOAD_MODE_REG_ST) and
412 
            (lmr_r = '1') and (af_addr_r((BANK_ADDRESS+ROW_ADDRESS+COL_AP_WIDTH-1)
413 
                                       downto (COL_AP_WIDTH+ROW_ADDRESS)) = "00")) then
414 
        load_mode_reg <= af_addr ((ROW_ADDRESS - 1) downto 0);
415 
      end if;
416 
    end if;
417 
  end process;
418 
 
419 
  process (clk_0)
420 
  begin
421 
    if(clk_0'event and clk_0 = '1') then
422 
      if(rst_r = '1') then
423 
        ext_mode_reg <= EXT_LOAD_MODE_REGISTER((ROW_ADDRESS - 1) downto 0);
424 
      elsif((state = LOAD_MODE_REG_ST or init_state = INIT_LOAD_MODE_REG_ST) and
425 
            (lmr_r = '1') and (af_addr_r((BANK_ADDRESS+ROW_ADDRESS+COL_AP_WIDTH-1)
426 
                                       downto (COL_AP_WIDTH+ROW_ADDRESS)) = "01")) then
427 
        ext_mode_reg <= af_addr (ROW_ADDRESS - 1 downto 0);
428 
      end if;
429 
    end if;
430 
  end process;
431 
 
432 
--to initialize memory
433 
  process (clk_0)
434 
  begin
435 
    if(clk_0'event and clk_0 = '1') then
436 
      if ((rst_r = '1') or (init_state = INIT_DEEP_MEMORY_ST)) then
437 
        init_memory <= '1';
438 
      elsif (init_count_cp = "1010") then
439 
        init_memory <= '0';
440 
      else
441 
        init_memory <= init_memory;
442 
      end if;
443 
    end if;
444 
  end process;
445 
 
446 
-- mrd count
447 
  process (clk_0)
448 
  begin
449 
    if(clk_0'event and clk_0 = '1') then
450 
      if(rst_r = '1') then
451 
        mrd_count <= '0';
452 
      elsif (state = LOAD_MODE_REG_ST) then
453 
        mrd_count <= MRD_COUNT_VALUE;
454 
      elsif (mrd_count /= '0') then
455 
        mrd_count <= '0';
456 
      else
457 
        mrd_count <= '0';
458 
      end if;
459 
    end if;
460 
  end process;
461 
 
462 
-- rp count
463 
  process (clk_0)
464 
  begin
465 
    if(clk_0'event and clk_0 = '1') then
466 
      if(rst_r = '1') then
467 
        rp_count(2 downto 0) <= "000";
468 
      elsif (state = PRECHARGE) then
469 
        rp_count(2 downto 0) <= RP_COUNT_VALUE;
470 
      elsif (rp_count(2 downto 0) /= "000") then
471 
        rp_count(2 downto 0) <= rp_count(2 downto 0) - 1;
472 
      else
473 
        rp_count(2 downto 0) <= "000";
474 
      end if;
475 
    end if;
476 
  end process;
477 
 
478 
-- rfc count
479 
  process (clk_0)
480 
  begin
481 
    if(clk_0'event and clk_0 = '1') then
482 
      if(rst_r = '1') then
483 
        rfc_count(5 downto 0) <= "000000";
484 
      elsif (state = AUTO_REFRESH) then
485 
        rfc_count(5 downto 0) <= RFC_COUNT_VALUE;
486 
      elsif (rfc_count(5 downto 0) /= "000000") then
487 
        rfc_count(5 downto 0) <= rfc_count(5 downto 0) - 1;
488 
      else
489 
        rfc_count(5 downto 0) <= "000000";
490 
      end if;
491 
    end if;
492 
  end process;
493 
 
494 
-- rcd count
495 
  process (clk_0)
496 
  begin
497 
    if(clk_0'event and clk_0 = '1') then
498 
      if(rst_r = '1') then
499 
        rcd_count(2 downto 0) <= "000";
500 
      elsif (state = ACTIVE) then
501 
        rcd_count(2 downto 0) <= RCD_COUNT_VALUE;
502 
      elsif (rcd_count(2 downto 0) /= "000") then
503 
        rcd_count(2 downto 0) <= rcd_count(2 downto 0) - 1;
504 
      else
505 
        rcd_count(2 downto 0) <= "000";
506 
      end if;
507 
    end if;
508 
  end process;
509 
 
510 
 
511 
-- ras count - active to precharge
512 
  process (clk_0)
513 
  begin
514 
    if(clk_0'event and clk_0 = '1') then
515 
      if(rst_r = '1') then
516 
        ras_count(3 downto 0) <= "0000";
517 
      elsif (state = ACTIVE) then
518 
        ras_count(3 downto 0) <= RAS_COUNT_VALUE;
519 
      elsif (ras_count(3 downto 1) = "000") then
520 
        if (ras_count(0) /= '0') then
521 
          ras_count(0) <= '0';
522 
        end if;
523 
      else
524 
        ras_count(3 downto 0) <= ras_count(3 downto 0) - 1;
525 
      end if;
526 
    end if;
527 
  end process;
528 
 
529 
--AL+BL/2+TRTP-2
530 
-- rtp count - read to precharge
531 
  process (clk_0)
532 
  begin
533 
    if(clk_0'event and clk_0 = '1') then
534 
      if(rst_r = '1') then
535 
        rtp_count(3 downto 0) <= "0000";
536 
      elsif (read_state = '1') then
537 
        rtp_count(2 downto 0) <= TRTP_COUNT_VALUE;
538 
      elsif (rtp_count(3 downto 1) = "000") then
539 
        if (rtp_count(0) /= '0') then
540 
          rtp_count(0) <= '0';
541 
        end if;
542 
      else
543 
        rtp_count(3 downto 0) <= rtp_count(3 downto 0) - 1;
544 
      end if;
545 
    end if;
546 
  end process;
547 
 
548 
-- WL+BL/2+TWR
549 
-- wtp count - write to precharge
550 
  process (clk_0)
551 
  begin
552 
    if(clk_0'event and clk_0 = '1') then
553 
      if(rst_r = '1') then
554 
        wtp_count(3 downto 0) <= "0000";
555 
      elsif (write_state = '1') then
556 
        wtp_count(2 downto 0) <= TWR_COUNT_VALUE;
557 
      elsif (wtp_count(3 downto 1) = "000") then
558 
        if (wtp_count(0) /= '0') then
559 
          wtp_count(0) <= '0';
560 
        end if;
561 
      else
562 
        wtp_count(3 downto 0) <= wtp_count(3 downto 0) - 1;
563 
      end if;
564 
    end if;
565 
  end process;
566 
 
567 
-- write to read counter
568 
 
569 
  process (clk_0)
570 
  begin
571 
    if(clk_0'event and clk_0 = '1') then
572 
      if(rst_r = '1') then
573 
        wr_to_rd_count(3 downto 0) <= "0000";
574 
      elsif (write_state = '1') then
575 
        wr_to_rd_count(2 downto 0) <= TWTR_COUNT_VALUE;
576 
      elsif (wr_to_rd_count(3 downto 0) /= "0000") then
577 
        wr_to_rd_count(3 downto 0) <= wr_to_rd_count(3 downto 0) - 1;
578 
      else
579 
        wr_to_rd_count(3 downto 0) <= "0000";
580 
      end if;
581 
    end if;
582 
  end process;
583 
 
584 
-- read to write counter
585 
  process (clk_0)
586 
  begin
587 
    if(clk_0'event and clk_0 = '1') then
588 
      if(rst_r = '1') then
589 
        rd_to_wr_count(3 downto 0) <= "0000";
590 
      elsif (read_state = '1') then
591 
        rd_to_wr_count(3 downto 0) <= REGISTERED + burst_cnt + load_mode_reg(6)
592 
                                      + load_mode_reg(4);
593 
      elsif (rd_to_wr_count(3 downto 0) /= "0000") then
594 
        rd_to_wr_count(3 downto 0) <= rd_to_wr_count(3 downto 0) - 1;
595 
      else
596 
        rd_to_wr_count(3 downto 0) <= "0000";
597 
      end if;
598 
    end if;
599 
  end process;
600 
 
601 
-- auto refresh interval counter in clk_0 domain
602 
  process (clk_0)
603 
  begin
604 
    if(clk_0'event and clk_0 = '1') then
605 
      if(rst_r = '1') then
606 
        refi_count <= (others => '0');
607 
      elsif (refi_count = MAX_REF_CNT) then
608 
        refi_count <= (others => '0');
609 
      else
610 
        refi_count <= refi_count + 1;
611 
      end if;
612 
    end if;
613 
  end process;
614 
 
615 
  ref_flag <= '1' when ((refi_count = MAX_REF_CNT) and (done_200us = '1')) else
616 
              '0';
617 
 
618 
--200us counter for cke
619 
  process (clk_0)
620 
  begin
621 
    if(clk_0'event and clk_0 = '1') then
622 
      if (rst_r = '1') then
623 
        cke_200us_cnt <= "11011";
624 
      elsif (refi_count(MAX_REF_WIDTH - 1 downto 0) = MAX_REF_CNT) then
625 
        cke_200us_cnt <= cke_200us_cnt - 1;
626 
      else
627 
        cke_200us_cnt <= cke_200us_cnt;
628 
      end if;
629 
    end if;
630 
  end process;
631 
 
632 
-- refresh detect
633 
  process (clk_0)
634 
  begin
635 
    if(clk_0'event and clk_0 = '1') then
636 
      if(rst_r = '1') then
637 
        ref_flag_0   <= '0';
638 
        ref_flag_0_r <= '0';
639 
        done_200us     <= '0';
640 
      else
641 
        ref_flag_0   <= ref_flag;
642 
        ref_flag_0_r <= ref_flag_0;
643 
        if (done_200us = '0' and (cke_200us_cnt = "00000")) then
644 
          done_200us <= '1';
645 
        end if;
646 
      end if;
647 
    end if;
648 
  end process;
649 
 
650 
--refresh flag detect
651 
--auto_ref high indicates auto_refresh requirement
652 
--auto_ref is held high until auto refresh command is issued.
653 
  process(clk_0)
654 
  begin
655 
    if(clk_0'event and clk_0 = '1') then
656 
      if(rst_r = '1') then
657 
        auto_ref <= '0';
658 
      elsif (ref_flag_0 = '1' and ref_flag_0_r = '0') then
659 
        auto_ref <= '1';
660 
      elsif ((state = AUTO_REFRESH) or (init_state = INIT_AUTO_REFRESH)) then
661 
        auto_ref <= '0';
662 
      else
663 
        auto_ref <= auto_ref;
664 
      end if;
665 
    end if;
666 
  end process;
667 
 
668 
-- 200 clocks counter - count value : C8
669 
-- required for initialization
670 
  process (clk_0)
671 
  begin
672 
    if(clk_0'event and clk_0 = '1') then
673 
      if(rst_r = '1') then
674 
        count_200_cycle(7 downto 0) <= "00000000";
675 
      elsif (init_state = INIT_INITCOUNT_200) then
676 
        count_200_cycle(7 downto 0) <= "11001000";
677 
      elsif (count_200_cycle(7 downto 0) /= "00000000") then
678 
        count_200_cycle(7 downto 0) <= count_200_cycle(7 downto 0) - 1;
679 
      else
680 
        count_200_cycle(7 downto 0) <= "00000000";
681 
      end if;
682 
    end if;
683 
  end process;
684 
 
685 
  process (clk_0)
686 
  begin
687 
    if(clk_0'event and clk_0 = '1') then
688 
      if(rst_r = '1') then
689 
        count_200cycle_done_r <= '0';
690 
      elsif ((init_memory = '1') and (count_200_cycle = "00000000")) then
691 
        count_200cycle_done_r <= '1';
692 
      else
693 
        count_200cycle_done_r <= '0';
694 
      end if;
695 
    end if;
696 
  end process;
697 
 
698 
 
699 
  process (clk_0)
700 
  begin
701 
    if(clk_0'event and clk_0 = '1') then
702 
      if(rst_r = '1') then
703 
        init_done_int <= '0';
704 
      elsif ((PHY_MODE = '1') and (comp_done = '1') and (count5 = "10100")) then
705 
        init_done_int <= '1';
706 
        --synthesis translate_off
707 
        report "Calibration completed at time " & time'image(now);
708 
        --synthesis translate_on
709 
      else
710 
        init_done_int <= init_done_int;
711 
      end if;
712 
    end if;
713 
  end process;
714 
 
715 
  ctrl_init_done <= init_done_int;
716 
 
717 
  process (clk_0)
718 
  begin
719 
    if(clk_0'event and clk_0 = '1') then
720 
      init_done <= init_done_int;
721 
    end if;
722 
  end process;
723 
 
724 
  burst_cnt <= "0010" when (burst_length_value = "010") else
725 
               "0100" when (burst_length_value = "011") else
726 
               "0001";
727 
 
728 
  burst_cnt_by2 <= "001" when (burst_length_value = "010") else
729 
                   "010" when (burst_length_value = "011") else
730 
                   "000";
731 
 
732 
  ddr_address_bl <= ADD_CONST7((ROW_ADDRESS - 1) downto 0) when
733 
                    (burst_length_value = "010") else
734 
                    ADD_CONST8((ROW_ADDRESS - 1) downto 0) when
735 
                    (burst_length_value = "011") else
736 
                    ADD_CONST6((ROW_ADDRESS - 1) downto 0);
737 
 
738 
  process (clk_0)
739 
  begin
740 
    if(clk_0'event and clk_0 = '1') then
741 
      if ((rst_r = '1')or (init_state = INIT_DEEP_MEMORY_ST)) then
742 
        init_count(3 downto 0) <= "0000";
743 
      elsif (init_memory = '1') then
744 
        if (init_state=INIT_LOAD_MODE_REG_ST or init_state=INIT_PRECHARGE or
745 
            init_state = INIT_AUTO_REFRESH or init_state=INIT_DUMMY_READ_CYCLES
746 
            or init_state=INIT_INITCOUNT_200 or init_state=INIT_DEEP_MEMORY_ST) then
747 
          init_count(3 downto 0) <= init_count(3 downto 0) + 1;
748 
        elsif(init_count = "1010") then
749 
          init_count(3 downto 0) <= "0000";
750 
        else init_count(3 downto 0) <= init_count(3 downto 0);
751 
        end if;
752 
      end if;
753 
    end if;
754 
  end process;
755 
 
756 
  process (clk_0)
757 
  begin
758 
    if(clk_0'event and clk_0 = '1') then
759 
      if ((rst_r = '1')or (init_state = INIT_DEEP_MEMORY_ST)) then
760 
        init_count_cp(3 downto 0) <= "0000";
761 
      elsif (init_memory = '1') then
762 
        if (init_state = INIT_LOAD_MODE_REG_ST or init_state = INIT_PRECHARGE or
763 
            init_state = INIT_AUTO_REFRESH or
764 
            init_state = INIT_DUMMY_READ_CYCLES or init_state=INIT_INITCOUNT_200
765 
            or init_state = INIT_DEEP_MEMORY_ST) then
766 
          init_count_cp(3 downto 0) <= init_count_cp(3 downto 0) + 1;
767 
        elsif(init_count_cp = "1010") then
768 
          init_count_cp(3 downto 0) <= "0000";
769 
        else init_count_cp(3 downto 0) <= init_count_cp(3 downto 0);
770 
        end if;
771 
      end if;
772 
    end if;
773 
  end process;
774 
 
775 
  process (clk_0)
776 
  begin
777 
    if(clk_0'event and clk_0 = '1') then
778 
      if(rst_r = '1') then
779 
        chip_cnt <= "00";
780 
      elsif (init_state = INIT_DEEP_MEMORY_ST) then
781 
        chip_cnt <= chip_cnt + "01";
782 
      else
783 
        chip_cnt <= chip_cnt;
784 
      end if;
785 
    end if;
786 
  end process;
787 
 
788 
-- write burst count
789 
  process (clk_0)
790 
  begin
791 
    if(clk_0'event and clk_0 = '1') then
792 
      if(rst_r = '1') then
793 
        wrburst_cnt(2 downto 0) <= "000";
794 
      elsif (write_state = '1' or dummy_write_state = '1') then
795 
        wrburst_cnt(2 downto 0) <= burst_cnt(2 downto 0);
796 
      elsif (wrburst_cnt(2 downto 0) /= "000") then
797 
        wrburst_cnt(2 downto 0) <= wrburst_cnt(2 downto 0) - 1;
798 
      else wrburst_cnt(2 downto 0) <= "000";
799 
      end if;
800 
    end if;
801 
  end process;
802 
 
803 
-- read burst count for state machine
804 
  process (clk_0)
805 
  begin
806 
    if(clk_0'event and clk_0 = '1') then
807 
      if(rst_r = '1') then
808 
        read_burst_cnt(2 downto 0) <= "000";
809 
      elsif (read_state = '1') then
810 
        read_burst_cnt(2 downto 0) <= burst_cnt(2 downto 0);
811 
      elsif (read_burst_cnt(2 downto 0) /= "000") then
812 
        read_burst_cnt(2 downto 0) <= read_burst_cnt(2 downto 0) - 1;
813 
      else read_burst_cnt(2 downto 0) <= "000";
814 
      end if;
815 
    end if;
816 
  end process;
817 
 
818 
-- count to generate write enable to the data path
819 
  process (clk_0)
820 
  begin
821 
    if(clk_0'event and clk_0 = '1') then
822 
      if(rst_r = '1') then
823 
        ctrl_wren_cnt(2 downto 0) <= "000";
824 
      elsif ((wdf_rden_r = '1') or (dummy_write_state_r = '1')) then
825 
        ctrl_wren_cnt(2 downto 0) <= burst_cnt(2 downto 0);
826 
      elsif (ctrl_wren_cnt(2 downto 0) /= "000") then
827 
        ctrl_wren_cnt(2 downto 0) <= ctrl_wren_cnt(2 downto 0) -1;
828 
      else
829 
        ctrl_wren_cnt(2 downto 0) <= "000";
830 
      end if;
831 
    end if;
832 
  end process;
833 
 
834 
--write enable to data path
835 
  process (ctrl_wren_cnt)
836 
  begin
837 
    if (ctrl_wren_cnt(2 downto 0) /= "000") then
838 
      ctrl_wren_r <= '1';
839 
    else
840 
      ctrl_wren_r <= '0';
841 
    end if;
842 
  end process;
843 
 
844 
  process(clk_0)
845 
  begin
846 
    if(clk_0'event and clk_0 = '1') then
847 
      if(rst_r = '1') then
848 
        ctrl_wren_r1 <= '0';
849 
      else
850 
        ctrl_wren_r1 <= ctrl_wren_r;
851 
      end if;
852 
    end if;
853 
  end process;
854 
 
855 
  ctrl_wren <= ctrl_wren_r1 when (registered_dimm = '1') else
856 
               ctrl_wren_r;
857 
 
858 
-- DQS reset to data path
859 
  process (clk_0)
860 
  begin
861 
    if(clk_0'event and clk_0 = '1') then
862 
      if(rst_r = '1') then
863 
        ctrl_dqs_rst_r <= '0';
864 
      elsif (first_write_state = '1' or init_state = INIT_DUMMY_WRITE1) then
865 
        ctrl_dqs_rst_r <= '1';
866 
      else
867 
        ctrl_dqs_rst_r <= '0';
868 
      end if;
869 
    end if;
870 
  end process;
871 
 
872 
  process(clk_0)
873 
  begin
874 
    if(clk_0'event and clk_0 = '1') then
875 
      if(rst_r = '1') then
876 
        ctrl_dqs_rst_r1 <= '0';
877 
      else
878 
        ctrl_dqs_rst_r1 <= ctrl_dqs_rst_r;
879 
      end if;
880 
    end if;
881 
  end process;
882 
 
883 
  ctrl_dqs_rst <= ctrl_dqs_rst_r1 when (registered_dimm = '1') else
884 
                  ctrl_dqs_rst_r;
885 
 
886 
-- DQS enable to data path
887 
  process (clk_0)
888 
  begin
889 
    if(clk_0'event and clk_0 = '1') then
890 
      if(rst_r = '1') then
891 
        ctrl_dqs_en_r <= '0';
892 
      elsif ((write_state = '1') or (wrburst_cnt /= "000") or
893 
             (dummy_write_state = '1')) then
894 
        ctrl_dqs_en_r <= '1';
895 
      else
896 
        ctrl_dqs_en_r <= '0';
897 
      end if;
898 
    end if;
899 
  end process;
900 
 
901 
  process(clk_0)
902 
  begin
903 
    if(clk_0'event and clk_0 = '1') then
904 
      if(rst_r = '1') then
905 
        ctrl_dqs_en_r1 <= '0';
906 
      else
907 
        ctrl_dqs_en_r1 <= ctrl_dqs_en_r;
908 
      end if;
909 
    end if;
910 
  end process;
911 
 
912 
  ctrl_dqs_en <= ctrl_dqs_en_r1 when (registered_dimm = '1') else
913 
                 ctrl_dqs_en_r;
914 
 
915 
-- cas count
916 
  process (clk_0)
917 
  begin
918 
    if(clk_0'event and clk_0 = '1') then
919 
      if(rst_r = '1') then
920 
        cas_count(2 downto 0) <= "000";
921 
      elsif ((init_state = INIT_DUMMY_FIRST_READ)) then
922 
        cas_count(2 downto 0) <= cas_latency_value(2 downto 0) + REGISTERED;
923 
      elsif (cas_count(2 downto 0) /= "000") then
924 
        cas_count(2 downto 0) <= cas_count(2 downto 0) - 1;
925 
      else cas_count(2 downto 0) <= "000";
926 
      end if;
927 
    end if;
928 
  end process;
929 
 
930 
--dummy_read enable
931 
  process (clk_0)
932 
  begin
933 
    if(clk_0'event and clk_0 = '1') then
934 
      if(rst_r = '1') then
935 
        dummy_read_en <= '0';
936 
      elsif (init_state = INIT_DUMMY_READ) then
937 
        dummy_read_en <= '1';
938 
      elsif (phy_dly_slct_done = '1') then
939 
        dummy_read_en <= '0';
940 
      else dummy_read_en <= dummy_read_en;
941 
      end if;
942 
    end if;
943 
  end process;
944 
 
945 
-- ctrl_dummyread_start signal generation to the data path module
946 
  process (clk_0)
947 
  begin
948 
    if(clk_0'event and clk_0 = '1') then
949 
      if(rst_r = '1') then
950 
 
951 
        ctrl_dummyread_start_r1 <= '0';
952 
      elsif ((dummy_read_en = '1') and (cas_count = "000")) then
953 
        ctrl_dummyread_start_r1 <= '1';
954 
      elsif (phy_dly_slct_done = '1') then
955 
        ctrl_dummyread_start_r1 <= '0';
956 
      else ctrl_dummyread_start_r1 <= ctrl_dummyread_start_r1;
957 
      end if;
958 
    end if;
959 
  end process;
960 
 
961 
-- register ctrl_dummyread_start signal
962 
  process (clk_0)
963 
  begin
964 
    if(clk_0'event and clk_0 = '1') then
965 
      if(rst_r = '1') then
966 
        ctrl_dummyread_start_r2 <= '0';
967 
        ctrl_dummyread_start_r3 <= '0';
968 
        ctrl_dummyread_start_r4 <= '0';
969 
        ctrl_dummyread_start    <= '0';
970 
      else
971 
        ctrl_dummyread_start_r2 <= ctrl_dummyread_start_r1;
972 
        ctrl_dummyread_start_r3 <= ctrl_dummyread_start_r2;
973 
        ctrl_dummyread_start_r4 <= ctrl_dummyread_start_r3;
974 
        ctrl_dummyread_start    <= ctrl_dummyread_start_r4;
975 
      end if;
976 
    end if;
977 
  end process;
978 
 
979 
-- read_wait/write_wait to idle count
980 
-- the state machine waits for 15 clock cycles in the write wait state for any
981 
-- wr/rd commands to be issued. If no commands are issued in 15 clock cycles,
982 
-- the statemachine issues enters the idle state and stays in the idle state
983 
-- until an auto refresh is required.
984 
 
985 
  process (clk_0)
986 
  begin
987 
    if(clk_0'event and clk_0 = '1') then
988 
      if(rst_r = '1') then
989 
        idle_cnt(3 downto 0) <= "0000";
990 
      elsif (read_write_state = '1') then
991 
        idle_cnt(3 downto 0) <= "1111";
992 
      elsif (idle_cnt(3 downto 0) /= "0000") then
993 
        idle_cnt(3 downto 0) <= idle_cnt(3 downto 0) - 1;
994 
      else idle_cnt(3 downto 0) <= "0000";
995 
      end if;
996 
    end if;
997 
  end process;
998 
 
999 
  process (clk_0)
1000 
  begin
1001 
    if(clk_0'event and clk_0 = '1') then
1002 
      if(rst_r = '1') then
1003 
        cas_check_count(3 downto 0) <= "0000";
1004 
      elsif (first_read_state_r2 = '1' or pattern_read_state_1_r2 = '1') then
1005 
        cas_check_count(3 downto 0) <= (cas_latency_value - 1);
1006 
      elsif (cas_check_count(3 downto 0) /= "0000") then
1007 
        cas_check_count(3 downto 0) <= cas_check_count(3 downto 0) - 1;
1008 
      else
1009 
        cas_check_count(3 downto 0) <= "0000";
1010 
      end if;
1011 
    end if;
1012 
  end process;
1013 
 
1014 
  process (clk_0)
1015 
  begin
1016 
    if(clk_0'event and clk_0 = '1') then
1017 
      if (rst_r = '1') then
1018 
        rdburst_cnt(2 downto 0) <= "000";
1019 
        ctrl_rden_r             <= '0';
1020 
      elsif ((cas_check_count = "0001") and (burst_read_state_r3 = '0')) then
1021 
        rdburst_cnt(2 downto 0) <= burst_cnt(2 downto 0);
1022 
        ctrl_rden_r             <= '1';
1023 
      elsif(burst_read_state_r3 = '1' or pattern_read_state_r3 = '1') then
1024 
        if(burst_cnt = "0100") then
1025 
          rdburst_cnt(2 downto 0) <= cas_latency_value(2 downto 0) +
1026 
                                     burst_cnt_by2;
1027 
        elsif (burst_cnt = "010") then
1028 
          rdburst_cnt(2 downto 0) <= cas_latency_value(2 downto 0);
1029 
        else
1030 
          rdburst_cnt(2 downto 0) <= cas_latency_value(2 downto 0) -
1031 
                                     burst_cnt(2 downto 0);
1032 
        end if;
1033 
        if(burst_read_state_r3 = '1') then
1034 
          ctrl_rden_r <= '1';
1035 
        end if;
1036 
      elsif (rdburst_cnt(2 downto 0) /= "000") then
1037 
        rdburst_cnt(2 downto 0) <= rdburst_cnt(2 downto 0) - '1';
1038 
        if(rdburst_cnt = "001") then
1039 
          ctrl_rden_r <= '0';
1040 
        end if;
1041 
      else
1042 
        rdburst_cnt(2 downto 0) <= "000";
1043 
      end if;
1044 
    end if;
1045 
  end process;
1046 
 
1047 
  process(clk_0)
1048 
  begin
1049 
    if(clk_0'event and clk_0 = '1') then
1050 
      if (rst_r = '1') then
1051 
        ctrl_rden_r1 <= '0';
1052 
      else
1053 
        ctrl_rden_r1 <= ctrl_rden_r;
1054 
      end if;
1055 
    end if;
1056 
  end process;
1057 
 
1058 
  ctrl_rden <= ctrl_rden_r1 when (registered_dimm = '1') else
1059 
               ctrl_rden_r;
1060 
 
1061 
-- write address FIFO read enable signals
1062 
 
1063 
  af_rden <= '1' when ((read_write_state = '1') or
1064 
                       ((state = MODE_REGISTER_WAIT) and lmr_r = '1'
1065 
                        and (mrd_count = '0'))
1066 
                       or ((state = PRECHARGE)and pre_r = '1') or
1067 
                       ((state = AUTO_REFRESH) and ref_r = '1')
1068 
                       or ((state = ACTIVE)and act_r = '1')) else '0';
1069 
 
1070 
-- write data fifo read enable
1071 
  process (clk_0)
1072 
  begin
1073 
    if(clk_0'event and clk_0 = '1') then
1074 
      if (rst_r = '1') then
1075 
        wdf_rden_r <= '0';
1076 
      elsif (write_state = '1') then
1077 
        wdf_rden_r <= '1';
1078 
      else
1079 
        wdf_rden_r <= '0';
1080 
      end if;
1081 
    end if;
1082 
  end process;
1083 
 
1084 
  process (clk_0)
1085 
  begin
1086 
    if(clk_0'event and clk_0 = '1') then
1087 
      if (rst_r = '1') then
1088 
        wdf_rden_r2 <= '0';
1089 
        wdf_rden_r3 <= '0';
1090 
        wdf_rden_r4 <= '0';
1091 
      else
1092 
        wdf_rden_r2 <= wdf_rden_r;
1093 
        wdf_rden_r3 <= wdf_rden_r2;
1094 
        wdf_rden_r4 <= wdf_rden_r3;
1095 
      end if;
1096 
    end if;
1097 
  end process;
1098 
 
1099 
-- Read enable to the data fifo
1100 
 
1101 
  process (burst_cnt, wdf_rden_r, wdf_rden_r2, wdf_rden_r3, wdf_rden_r4)
1102 
  begin
1103 
    if (burst_cnt = "001") then
1104 
      ctrl_wdf_rden_r <= (wdf_rden_r);
1105 
    elsif (burst_cnt = "010") then
1106 
      ctrl_wdf_rden_r <= (wdf_rden_r or wdf_rden_r2);
1107 
    elsif (burst_cnt = "100") then
1108 
      ctrl_wdf_rden_r <= (wdf_rden_r or wdf_rden_r2 or wdf_rden_r3 or
1109 
                          wdf_rden_r4);
1110 
    else
1111 
      ctrl_wdf_rden_r <= '0';
1112 
    end if;
1113 
  end process;
1114 
 
1115 
  process (clk_0)
1116 
  begin
1117 
    if(clk_0'event and clk_0 = '1') then
1118 
      if(rst_r = '1') then
1119 
        ctrl_wdf_rden_r1 <= '0';
1120 
      else
1121 
        ctrl_wdf_rden_r1 <= ctrl_wdf_rden_r;
1122 
      end if;
1123 
    end if;
1124 
  end process;
1125 
 
1126 
  ctrl_wdf_rden <= ctrl_wdf_rden_r1 when (registered_dimm = '1') else
1127 
                   ctrl_wdf_rden_r;
1128 
 
1129 
  process(clk_0)
1130 
  begin
1131 
    if(clk_0'event and clk_0 = '1') then
1132 
      if(rst_r = '1') then
1133 
        dummy_write_flag <= '0';
1134 
      else
1135 
        dummy_write_flag <= phy_dly_slct_done and not(comp_done);
1136 
      end if;
1137 
    end if;
1138 
  end process;
1139 
 
1140 
  process (clk_0)
1141 
  begin
1142 
    if(clk_0'event and clk_0 = '1') then
1143 
      if(rst_r = '1') then
1144 
        state <= IDLE;
1145 
      else
1146 
        state <= next_state;
1147 
      end if;
1148 
    end if;
1149 
  end process;
1150 
 
1151 
  process (clk_0)
1152 
  begin
1153 
    if(clk_0'event and clk_0 = '1') then
1154 
      if(rst_r = '1') then
1155 
        init_state <= INIT_IDLE;
1156 
      else
1157 
        init_state <= init_next_state;
1158 
      end if;
1159 
    end if;
1160 
  end process;
1161 
 
1162 
  process (clk_0)
1163 
  begin
1164 
    if(clk_0'event and clk_0 = '1') then
1165 
      if(rst_r = '1') then
1166 
        count5 <= (others => '0');
1167 
      else
1168 
        case init_state is
1169 
          when INIT_PRECHARGE_WAIT | INIT_MODE_REGISTER_WAIT |
1170 
            INIT_AUTO_REFRESH_WAIT | INIT_DUMMY_WRITE_READ |
1171 
            INIT_PATTERN_READ_WAIT | INIT_DUMMY_READ_WAIT |
1172 
            INIT_DUMMY_ACTIVE_WAIT =>
1173 
            count5 <= count5 + '1';
1174 
 
1175 
          when others =>
1176 
            count5 <= (others => '0');
1177 
        end case;
1178 
      end if;
1179 
    end if;
1180 
  end process;
1181 
 
1182 
-- Initialization state machine
1183 
  process (auto_ref, chip_cnt, count_200cycle_done_r, done_200us,
1184 
           init_count, init_memory, phy_dly_slct_done, init_state,
1185 
           burst_cnt, comp_done, dummy_write_flag, count5)
1186 
  begin
1187 
 
1188 
    init_next_state <= init_state;
1189 
    case init_state is
1190 
      when INIT_IDLE =>
1191 
        if (init_memory = '1' and done_200us = '1') then
1192 
          case init_count is            -- synthesis parallel_case full_case
1193 
            when "0000" => init_next_state <= INIT_INITCOUNT_200;
1194 
            when "0001" => init_next_state <= INIT_PRECHARGE;
1195 
            when "0010" => init_next_state <= INIT_LOAD_MODE_REG_ST;
1196 
            when "0011" => init_next_state <= INIT_LOAD_MODE_REG_ST;
1197 
            when "0100" => init_next_state <= INIT_INITCOUNT_200;
1198 
            when "0101" => init_next_state <= INIT_PRECHARGE;
1199 
            when "0110" => init_next_state <= INIT_AUTO_REFRESH;
1200 
            when "0111" => init_next_state <= INIT_AUTO_REFRESH;
1201 
            when "1000" => init_next_state <= INIT_LOAD_MODE_REG_ST;
1202 
            when "1001" =>
1203 
              if((chip_cnt < NO_OF_CS-1)) then
1204 
                init_next_state <= INIT_DEEP_MEMORY_ST;
1205 
              elsif ((PHY_MODE = '1' and count_200cycle_done_r = '1')) then
1206 
                init_next_state <= INIT_DUMMY_READ_CYCLES;
1207 
              else
1208 
                init_next_state <= INIT_IDLE;
1209 
              end if;
1210 
            when "1010" =>
1211 
              if (phy_dly_slct_done = '1') then
1212 
                init_next_state <= INIT_IDLE;
1213 
              end if;
1214 
            when others => init_next_state <= INIT_IDLE;
1215 
 
1216 
          end case;  -- case(init_count )
1217 
        end if;
1218 
 
1219 
      when INIT_DEEP_MEMORY_ST => init_next_state <= INIT_IDLE;
1220 
 
1221 
      when INIT_INITCOUNT_200 => init_next_state <= INIT_INITCOUNT_200_WAIT;
1222 
 
1223 
      when INIT_INITCOUNT_200_WAIT =>
1224 
        if (count_200cycle_done_r = '1') then
1225 
          init_next_state <= INIT_IDLE;
1226 
        else
1227 
          init_next_state <= INIT_INITCOUNT_200_WAIT;
1228 
        end if;
1229 
 
1230 
      when INIT_DUMMY_READ_CYCLES => init_next_state <= INIT_DUMMY_ACTIVE;
1231 
 
1232 
 
1233 
      when INIT_DUMMY_ACTIVE => init_next_state <= INIT_DUMMY_ACTIVE_WAIT;
1234 
 
1235 
 
1236 
      when INIT_DUMMY_ACTIVE_WAIT =>
1237 
        if (count5 = cntnext) then
1238 
          if(dummy_write_flag = '1') then
1239 
            init_next_state <= INIT_DUMMY_WRITE1;
1240 
          else
1241 
            init_next_state <= INIT_DUMMY_FIRST_READ;
1242 
          end if;
1243 
        else
1244 
          init_next_state <= INIT_DUMMY_ACTIVE_WAIT;
1245 
        end if;
1246 
 
1247 
      when INIT_DUMMY_FIRST_READ =>
1248 
        init_next_state <= INIT_DUMMY_READ_WAIT;
1249 
 
1250 
      when INIT_DUMMY_READ =>
1251 
        if((burst_cnt = "001") and (phy_dly_slct_done = '0')) then
1252 
          init_next_state <= INIT_DUMMY_READ;
1253 
        else
1254 
          init_next_state <= INIT_DUMMY_READ_WAIT;
1255 
        end if;
1256 
 
1257 
      when INIT_DUMMY_READ_WAIT =>
1258 
        if (phy_dly_slct_done = '1') then
1259 
          if(count5 = cntnext) then
1260 
            if(auto_ref = '1') then
1261 
              init_next_state <= INIT_PRECHARGE;
1262 
            else
1263 
              init_next_state <= INIT_DUMMY_WRITE1;
1264 
            end if;
1265 
          else
1266 
            init_next_state <= INIT_DUMMY_READ_WAIT;
1267 
          end if;
1268 
        else
1269 
          init_next_state <= INIT_DUMMY_READ;
1270 
        end if;
1271 
 
1272 
      when INIT_DUMMY_WRITE1 =>
1273 
        if (burst_cnt = "0001") then
1274 
          init_next_state <= INIT_DUMMY_WRITE2;
1275 
        else
1276 
          init_next_state <= INIT_DUMMY_WRITE_READ;
1277 
        end if;
1278 
 
1279 
 
1280 
      when INIT_DUMMY_WRITE2 =>
1281 
        init_next_state <= INIT_DUMMY_WRITE_READ;
1282 
 
1283 
      when INIT_DUMMY_WRITE_READ =>
1284 
        if (count5 = cntnext) then
1285 
          init_next_state <= INIT_PATTERN_READ1;
1286 
        else
1287 
          init_next_state <= INIT_DUMMY_WRITE_READ;
1288 
        end if;
1289 
 
1290 
      when INIT_PATTERN_READ1 =>
1291 
        if (burst_cnt = "0001") then
1292 
          init_next_state <= INIT_PATTERN_READ2;
1293 
        else
1294 
          init_next_state <= INIT_PATTERN_READ_WAIT;
1295 
        end if;
1296 
 
1297 
      when INIT_PATTERN_READ2 =>
1298 
        init_next_state <= INIT_PATTERN_READ_WAIT;
1299 
 
1300 
      when INIT_PATTERN_READ_WAIT =>
1301 
        if(comp_done = '1') then
1302 
          init_next_state <= INIT_PRECHARGE;
1303 
        else
1304 
          init_next_state <= INIT_PATTERN_READ_WAIT;
1305 
        end if;
1306 
 
1307 
 
1308 
      when INIT_PRECHARGE => init_next_state <= INIT_PRECHARGE_WAIT;
1309 
 
1310 
 
1311 
      when INIT_PRECHARGE_WAIT =>
1312 
        if (count5 = cntnext) then
1313 
          if (auto_ref = '1' and dummy_write_flag = '1') then
1314 
            init_next_state <= INIT_AUTO_REFRESH;
1315 
          else
1316 
            init_next_state <= INIT_IDLE;
1317 
          end if;
1318 
        else
1319 
          init_next_state <= INIT_PRECHARGE_WAIT;
1320 
        end if;
1321 
 
1322 
      when INIT_LOAD_MODE_REG_ST => init_next_state <= INIT_MODE_REGISTER_WAIT;
1323 
 
1324 
 
1325 
      when INIT_MODE_REGISTER_WAIT =>
1326 
        if (count5 = cntnext) then
1327 
          init_next_state <= INIT_IDLE;
1328 
        else
1329 
          init_next_state <= INIT_MODE_REGISTER_WAIT;
1330 
        end if;
1331 
 
1332 
      when INIT_AUTO_REFRESH => init_next_state <= INIT_AUTO_REFRESH_WAIT;
1333 
 
1334 
      when INIT_AUTO_REFRESH_WAIT =>
1335 
        if ((count5 = cntnext) and (phy_dly_slct_done = '1')) then
1336 
          init_next_state <= INIT_DUMMY_ACTIVE;
1337 
        elsif (count5 = cntnext) then
1338 
          init_next_state <= INIT_IDLE;
1339 
        else
1340 
          init_next_state <= INIT_AUTO_REFRESH_WAIT;
1341 
        end if;
1342 
 
1343 
      when others => init_next_state <= INIT_IDLE;
1344 
 
1345 
    end case;
1346 
  end process;
1347 
 
1348 
--Main control state machine
1349 
  process (act_r, lmr_pre_ref_act_cmd_r, lmr_r, rd
1350 
           , rd_r, ref_r, wr, wr_r, auto_ref
1351 
           , conflict_detect, conflict_detect_r
1352 
           , conflict_resolved_r, idle_cnt, mrd_count, ras_count, rcd_count
1353 
           , rd_to_wr_count, read_burst_cnt, rfc_count, rp_count
1354 
           , rtp_count, state, wr_to_rd_count, wrburst_cnt
1355 
           , wtp_count, burst_cnt, init_done_int, af_empty_r)
1356 
  begin
1357 
 
1358 
    next_state <= state;
1359 
    case state is
1360 
      when IDLE =>
1361 
        if ((conflict_detect_r='1' or lmr_pre_ref_act_cmd_r='1' or auto_ref='1')
1362 
            and ras_count = "0000" and init_done_int = '1') then
1363 
          next_state <= PRECHARGE;
1364 
        elsif ((wr_r = '1' or rd_r = '1') and (ras_count = "0000")) then
1365 
          next_state <= ACTIVE;
1366 
        end if;
1367 
 
1368 
      when LOAD_MODE_REG_ST => next_state <= MODE_REGISTER_WAIT;
1369 
 
1370 
      when MODE_REGISTER_WAIT =>
1371 
        if (mrd_count = '0') then
1372 
          next_state <= IDLE;
1373 
        else
1374 
          next_state <= MODE_REGISTER_WAIT;
1375 
        end if;
1376 
 
1377 
      when PRECHARGE => next_state <= PRECHARGE_WAIT;
1378 
 
1379 
 
1380 
      when PRECHARGE_WAIT =>
1381 
        if (rp_count = "000") then
1382 
          if ((auto_ref or ref_r) = '1') then
1383 
            next_state <= AUTO_REFRESH;
1384 
          elsif (lmr_r = '1') then
1385 
            next_state <= LOAD_MODE_REG_ST;
1386 
          elsif ((conflict_detect_r or act_r) = '1') then
1387 
            next_state <= ACTIVE;
1388 
          else
1389 
            next_state <= IDLE;
1390 
          end if;
1391 
        else
1392 
          next_state <= PRECHARGE_WAIT;
1393 
        end if;
1394 
 
1395 
      when AUTO_REFRESH => next_state <= AUTO_REFRESH_WAIT;
1396 
 
1397 
      when AUTO_REFRESH_WAIT =>
1398 
        if ((rfc_count = "00001") and (conflict_detect_r = '1')) then
1399 
          next_state <= ACTIVE;
1400 
        elsif (rfc_count = "00001") then
1401 
          next_state <= IDLE;
1402 
        else
1403 
          next_state <= AUTO_REFRESH_WAIT;
1404 
        end if;
1405 
 
1406 
      when ACTIVE => next_state <= ACTIVE_WAIT;
1407 
 
1408 
 
1409 
      when ACTIVE_WAIT =>
1410 
        if (rcd_count = "000") then
1411 
          if(wr = '1') then
1412 
            next_state <= FIRST_WRITE;
1413 
          elsif (rd = '1') then
1414 
            next_state <= FIRST_READ;
1415 
          else
1416 
            next_state <= IDLE;
1417 
          end if;
1418 
        else
1419 
          next_state <= ACTIVE_WAIT;
1420 
        end if;
1421 
 
1422 
      when FIRST_WRITE =>
1423 
        if((((conflict_detect = '1') and (conflict_resolved_r = '0')) or
1424 
            (auto_ref = '1')) or rd = '1') then
1425 
          next_state <= WRITE_WAIT;
1426 
        elsif((burst_cnt = "001") and (wr = '1')) then
1427 
          next_state <= BURST_WRITE;
1428 
        else
1429 
          next_state <= WRITE_WAIT;
1430 
        end if;
1431 
 
1432 
      when BURST_WRITE =>
1433 
        if((((conflict_detect = '1') and (conflict_resolved_r = '0')) or
1434 
            (auto_ref = '1')) or (rd = '1')) then
1435 
          next_state <= WRITE_WAIT;
1436 
        elsif((burst_cnt = "001") and (wr = '1')) then
1437 
          next_state <= BURST_WRITE;
1438 
        else
1439 
          next_state <= WRITE_WAIT;
1440 
        end if;
1441 
 
1442 
      when WRITE_WAIT =>
1443 
        if (((conflict_detect = '1') and (conflict_resolved_r = '0')) or
1444 
            (auto_ref = '1')) then
1445 
          if ((wtp_count = "0000") and (ras_count = "0000")) then
1446 
            next_state <= PRECHARGE;
1447 
          else
1448 
            next_state <= WRITE_WAIT;
1449 
          end if;
1450 
        elsif (rd = '1') then
1451 
          next_state <= WRITE_READ;
1452 
        elsif ((wr = '1') and (wrburst_cnt = "010")) then
1453 
          next_state <= BURST_WRITE;
1454 
        elsif((wr = '1') and (wrburst_cnt = "000")) then
1455 
          next_state <= FIRST_WRITE;
1456 
        elsif (idle_cnt = "0000") then
1457 
          next_state <= PRECHARGE;
1458 
        else
1459 
          next_state <= WRITE_WAIT;
1460 
        end if;
1461 
 
1462 
      when WRITE_READ =>
1463 
        if (wr_to_rd_count = "0000") then
1464 
          next_state <= FIRST_READ;
1465 
        else
1466 
          next_state <= WRITE_READ;
1467 
        end if;
1468 
 
1469 
      when FIRST_READ =>
1470 
        if((((conflict_detect = '1') and (conflict_resolved_r = '0')) or
1471 
            (auto_ref = '1')) or (wr = '1')) then
1472 
          next_state <= READ_WAIT;
1473 
        elsif((burst_cnt = "001") and (rd = '1')) then
1474 
          next_state <= BURST_READ;
1475 
        else
1476 
          next_state <= READ_WAIT;
1477 
        end if;
1478 
 
1479 
      when BURST_READ =>
1480 
        if((((conflict_detect = '1') and (conflict_resolved_r = '0'))or
1481 
            (auto_ref = '1')) or (wr = '1')) then
1482 
          next_state <= READ_WAIT;
1483 
        elsif((burst_cnt = "001") and (rd = '1')) then
1484 
          next_state <= BURST_READ;
1485 
        else
1486 
          next_state <= READ_WAIT;
1487 
        end if;
1488 
 
1489 
      when READ_WAIT =>
1490 
        if (((conflict_detect = '1') and (conflict_resolved_r = '0')) or
1491 
            (auto_ref = '1')) then
1492 
          if(rtp_count = "0000" and ras_count = "0000") then
1493 
            next_state <= PRECHARGE;
1494 
          else
1495 
            next_state <= READ_WAIT;
1496 
          end if;
1497 
        elsif (wr = '1') then
1498 
          next_state <= READ_WRITE;
1499 
        elsif ((rd = '1') and (read_burst_cnt <= "010")) then
1500 
          if(af_empty_r = '1') then
1501 
            next_state <= FIRST_READ;
1502 
          else
1503 
            next_state <= BURST_READ;
1504 
          end if;
1505 
        elsif (idle_cnt = "0000") then
1506 
          next_state <= PRECHARGE;
1507 
        else
1508 
          next_state <= READ_WAIT;
1509 
        end if;
1510 
 
1511 
 
1512 
      when READ_WRITE =>
1513 
        if (rd_to_wr_count = "0000") then
1514 
          next_state <= FIRST_WRITE;
1515 
        else
1516 
          next_state <= READ_WRITE;
1517 
        end if;
1518 
 
1519 
      when others => next_state <= IDLE;
1520 
 
1521 
    end case;
1522 
  end process;
1523 
 
1524 
 
1525 
 
1526 
--register command outputs
1527 
  process (clk_0)
1528 
  begin
1529 
    if(clk_0'event and clk_0 = '1') then
1530 
      if(rst_r = '1') then
1531 
        state_r2 <= "00000";
1532 
      else
1533 
        state_r2 <= state;
1534 
      end if;
1535 
    end if;
1536 
  end process;
1537 
 
1538 
  process (clk_0)
1539 
  begin
1540 
    if(clk_0'event and clk_0 = '1') then
1541 
      if(rst_r = '1') then
1542 
        init_state_r2 <= "00000";
1543 
      else
1544 
        init_state_r2 <= init_state;
1545 
      end if;
1546 
    end if;
1547 
  end process;
1548 
 
1549 
 
1550 
-- commands to the memory
1551 
  process (clk_0)
1552 
  begin
1553 
    if(clk_0'event and clk_0 = '1') then
1554 
      if(rst_r = '1') then
1555 
        ddr_ras_r <= '1';
1556 
      elsif ((state = LOAD_MODE_REG_ST) or (state = PRECHARGE) or (state = ACTIVE)
1557 
             or (state = AUTO_REFRESH) or (init_state = INIT_LOAD_MODE_REG_ST)
1558 
             or (init_state = INIT_PRECHARGE) or (init_state = INIT_AUTO_REFRESH)
1559 
             or (init_state = INIT_DUMMY_ACTIVE)) then
1560 
        ddr_ras_r <= '0';
1561 
      else ddr_ras_r <= '1';
1562 
      end if;
1563 
    end if;
1564 
  end process;
1565 
 
1566 
-- commands to the memory
1567 
  process (clk_0)
1568 
  begin
1569 
    if(clk_0'event and clk_0 = '1') then
1570 
      if(rst_r = '1') then
1571 
        ddr_cas_r <= '1';
1572 
      elsif ((state = LOAD_MODE_REG_ST) or (init_state = INIT_LOAD_MODE_REG_ST)
1573 
             or (read_write_state = '1') or (init_state = INIT_DUMMY_FIRST_READ)
1574 
             or (dummy_write_state = '1') or (state = AUTO_REFRESH)
1575 
             or (init_state = INIT_AUTO_REFRESH) or (init_state = INIT_DUMMY_READ)
1576 
             or (pattern_read_state = '1')) then
1577 
        ddr_cas_r <= '0';
1578 
      elsif ((state = ACTIVE_WAIT) or (init_state = INIT_DUMMY_ACTIVE_WAIT)) then
1579 
        ddr_cas_r <= '1';
1580 
      else
1581 
        ddr_cas_r <= '1';
1582 
      end if;
1583 
    end if;
1584 
  end process;
1585 
 
1586 
-- commands to the memory
1587 
  process (clk_0)
1588 
  begin
1589 
    if(clk_0'event and clk_0 = '1') then
1590 
      if(rst_r = '1') then
1591 
        ddr_we_r <= '1';
1592 
      elsif ((state = LOAD_MODE_REG_ST) or (state = PRECHARGE) or
1593 
             (init_state = INIT_LOAD_MODE_REG_ST) or
1594 
             (init_state = INIT_PRECHARGE) or (write_state = '1')
1595 
             or (dummy_write_state = '1')) then
1596 
        ddr_we_r <= '0';
1597 
      else ddr_we_r <= '1';
1598 
      end if;
1599 
    end if;
1600 
  end process;
1601 
 
1602 
--register commands to the memory
1603 
  process (clk_0)
1604 
  begin
1605 
    if(clk_0'event and clk_0 = '1') then
1606 
      if(rst_r = '1') then
1607 
        ddr_ras_r2 <= '1';
1608 
        ddr_cas_r2 <= '1';
1609 
        ddr_we_r2  <= '1';
1610 
      else
1611 
        ddr_ras_r2 <= ddr_ras_r;
1612 
        ddr_cas_r2 <= ddr_cas_r;
1613 
        ddr_we_r2  <= ddr_we_r;
1614 
      end if;
1615 
    end if;
1616 
  end process;
1617 
 
1618 
--register commands to the memory
1619 
  process (clk_0)
1620 
  begin
1621 
    if(clk_0'event and clk_0 = '1') then
1622 
      if (rst_r = '1') then
1623 
        ddr_ras_r3 <= '1';
1624 
        ddr_cas_r3 <= '1';
1625 
        ddr_we_r3  <= '1';
1626 
      else
1627 
        ddr_ras_r3 <= ddr_ras_r2;
1628 
        ddr_cas_r3 <= ddr_cas_r2;
1629 
        ddr_we_r3  <= ddr_we_r2;
1630 
      end if;
1631 
    end if;
1632 
  end process;
1633 
 
1634 
  process (clk_0)
1635 
  begin
1636 
    if(clk_0'event and clk_0 = '1') then
1637 
      if(rst_r = '1') then
1638 
        row_addr_r(ROW_ADDRESS - 1 downto 0) <= (others => '0');
1639 
      else
1640 
        row_addr_r(ROW_ADDRESS - 1 downto 0) <= af_addr((ROW_ADDRESS + COL_AP_WIDTH)
1641 
                                                      -1 downto COL_AP_WIDTH);
1642 
      end if;
1643 
    end if;
1644 
  end process;
1645 
 
1646 
-- address during init
1647 
  process (clk_0)
1648 
  begin
1649 
    if(clk_0'event and clk_0 = '1') then
1650 
      if(rst_r = '1') then
1651 
        ddr_address_init_r <= (others => '0');
1652 
      elsif (init_memory = '1') then
1653 
        if (init_state_r2 = INIT_PRECHARGE) then
1654 
          ddr_address_init_r <= ADD_CONST1((ROW_ADDRESS - 1) downto 0);
1655 
                                            --A10 = 1 for precharge all
1656 
        elsif ((init_state_r2=INIT_LOAD_MODE_REG_ST) and
1657 
               (init_count_cp="0011")) then
1658 
          ddr_address_init_r <= ext_mode_reg;  -- A0 = 0 for DLL enable
1659 
        elsif ((init_state_r2=INIT_LOAD_MODE_REG_ST) and
1660 
               (init_count_cp = "0100")) then
1661 
          ddr_address_init_r <= ADD_CONST2((ROW_ADDRESS - 1) downto 0) or
1662 
                                load_mode_reg;  -- A8 = 1 for DLL reset
1663 
        elsif ((init_state_r2 = INIT_LOAD_MODE_REG_ST) and
1664 
               (init_count_cp = "1001")) then
1665 
          ddr_address_init_r <= ADD_CONST5((ROW_ADDRESS - 1) downto 0) and
1666 
                                load_mode_reg; -- A8 = 0 to deactivate DLL reset
1667 
        else
1668 
          ddr_address_init_r <= ADD_CONST3((ROW_ADDRESS - 1) downto 0);
1669 
        end if;
1670 
      end if;
1671 
    end if;
1672 
  end process;
1673 
 
1674 
  process (clk_0)
1675 
  begin
1676 
    if(clk_0'event and clk_0 = '1') then
1677 
      if(rst_r = '1') then
1678 
        ddr_address_r1 <= (others => '0');
1679 
      elsif ((init_state_r2=INIT_DUMMY_WRITE1) or
1680 
             (init_state_r2=INIT_PATTERN_READ1)) then
1681 
        ddr_address_r1 <= (others => '0');
1682 
      elsif ((init_state_r2=INIT_DUMMY_WRITE2) or
1683 
             (init_state_r2 = INIT_PATTERN_READ2)) then
1684 
        ddr_address_r1 <= ddr_address_bl;
1685 
      elsif ((state_r2 = ACTIVE)) then
1686 
        ddr_address_r1 <= row_addr_r;
1687 
      elsif (read_write_state_r2 = '1') then
1688 
        ddr_address_r1 <= af_addr_r(ROW_ADDRESS - 1 downto 0) and
1689 
                          ADD_CONST4((ROW_ADDRESS - 1) downto 0);
1690 
      elsif ((state_r2 = PRECHARGE) or (init_state_r2 = INIT_PRECHARGE)) then
1691 
          ddr_address_r1 <= ADD_CONST1((ROW_ADDRESS - 1) downto 0);  --X"0400";
1692 
      elsif ((state_r2=LOAD_MODE_REG_ST) or (init_state_r2=INIT_LOAD_MODE_REG_ST))then
1693 
        ddr_address_r1 <= af_addr_r(ROW_ADDRESS - 1 downto 0);
1694 
      else
1695 
        ddr_address_r1 <= ADD_CONST3((ROW_ADDRESS - 1) downto 0); --X"0000";
1696 
      end if;
1697 
    end if;
1698 
  end process;
1699 
 
1700 
  process(clk_0)
1701 
  begin
1702 
    if(clk_0'event and clk_0 = '1') then
1703 
      if(rst_r = '1') then
1704 
        ddr_address_r2 <= (others => '0');
1705 
      elsif(init_memory = '1') then
1706 
        ddr_address_r2 <= ddr_address_init_r;
1707 
      else
1708 
        ddr_address_r2 <= ddr_address_r1;
1709 
      end if;
1710 
    end if;
1711 
  end process;
1712 
 
1713 
  process (clk_0)
1714 
  begin
1715 
    if(clk_0'event and clk_0 = '1') then
1716 
      if(rst_r = '1') then
1717 
        ddr_ba_r1(BANK_ADDRESS - 1 downto 0) <= (others => '0');
1718 
      elsif (init_memory = '1' and (state_r2 = LOAD_MODE_REG_ST or
1719 
                                    init_state_r2 = INIT_LOAD_MODE_REG_ST)) then
1720 
        if (init_count_cp = "0011") then
1721 
          ddr_ba_r1(BANK_ADDRESS - 1 downto 0) <= "01";  --X"1";
1722 
        else
1723 
          ddr_ba_r1(BANK_ADDRESS - 1 downto 0) <= "00";  --X"0";
1724 
        end if;
1725 
      elsif ((state_r2 = ACTIVE) or (init_state_r2 = INIT_DUMMY_ACTIVE) or
1726 
             (state_r2=LOAD_MODE_REG_ST) or (init_state_r2=INIT_LOAD_MODE_REG_ST)
1727 
             or (((state_r2 = PRECHARGE) or (init_state_r2=INIT_PRECHARGE))
1728 
                 and pre_r = '1')) then
1729 
        ddr_ba_r1(BANK_ADDRESS - 1 downto 0) <= af_addr((BANK_ADDRESS+ROW_ADDRESS+
1730 
                                                       COL_AP_WIDTH)-1 downto
1731 
                                                      (COL_AP_WIDTH+ROW_ADDRESS));
1732 
      else ddr_ba_r1(BANK_ADDRESS - 1 downto 0) <= ddr_ba_r1(BANK_ADDRESS - 1 downto 0);
1733 
      end if;
1734 
    end if;
1735 
  end process;
1736 
 
1737 
  process(clk_0)
1738 
  begin
1739 
    if(clk_0'event and clk_0 = '1') then
1740 
      if(rst_r = '1') then
1741 
        ddr_ba_r2 <= (others => '0');
1742 
      else
1743 
        ddr_ba_r2 <= ddr_ba_r1;
1744 
      end if;
1745 
    end if;
1746 
  end process;
1747 
 
1748 
 
1749 
  process (clk_0)
1750 
  begin
1751 
    if(clk_0'event and clk_0 = '1') then
1752 
      if(rst_r = '1') then
1753 
        conflict_resolved_r <= '0';
1754 
      else
1755 
        if (((state = PRECHARGE_WAIT) or (init_state = INIT_PRECHARGE_WAIT))
1756 
            and (conflict_detect_r = '1')) then
1757 
          conflict_resolved_r <= '1';
1758 
        elsif(af_rden = '1') then
1759 
          conflict_resolved_r <= '0';
1760 
        end if;
1761 
      end if;
1762 
    end if;
1763 
  end process;
1764 
 
1765 
 
1766 
  process (clk_0)
1767 
  begin
1768 
    if(clk_0'event and clk_0 = '1') then
1769 
      if(rst_r = '1') then
1770 
        ddr_cke_r <= '0';
1771 
      else
1772 
        if(done_200us = '1') then
1773 
          ddr_cke_r <= '1';
1774 
        end if;
1775 
      end if;
1776 
    end if;
1777 
  end process;
1778 
 
1779 
 
1780 
  ctrl_ddr_address(ROW_ADDRESS - 1 downto 0) <= ddr_address_r2(ROW_ADDRESS - 1 downto 0);
1781 
  ctrl_ddr_ba (BANK_ADDRESS - 1 downto 0)    <= ddr_ba_r2(BANK_ADDRESS - 1 downto 0);
1782 
  ctrl_ddr_ras_l                           <= ddr_ras_r3;
1783 
  ctrl_ddr_cas_l                           <= ddr_cas_r3;
1784 
  ctrl_ddr_we_l                            <= ddr_we_r3;
1785 
  ctrl_ddr_cs_l                            <= '0';
1786 
 
1787 
  ctrl_ddr_cke <= ddr_cke_r;
1788 
 
1789 
end arch;

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