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[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [Memory Design/] [MIG_top_00/] [MIG_iobs_0/] [MIG_iobs_0.vhd] - Blame information for rev 24

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1 24 mcwaccent 
-------------------------------------------------------------------------------
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-- Copyright (c) 2005-2007 Xilinx, Inc.
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-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
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-------------------------------------------------------------------------------
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--   ____  ____
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--  /   /\/   /
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-- /___/  \  /   Vendor             : Xilinx
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-- \   \   \/    Version            : $Name: i+IP+131489 $
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--  \   \        Application        : MIG
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--  /   /        Filename           : MIG_iobs_0.vhd
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-- /___/   /\    Date Last Modified : $Date: 2007/09/21 15:23:24 $
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-- \   \  /  \   Date Created       : Mon May 2 2005
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--  \___\/\___\
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--
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-- Device      : Virtex-4
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-- Design Name : DDR SDRAM
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-- Description: This module instantiates all the iobs modules. It is the
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--              interface between the main logic and the memory.
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-------------------------------------------------------------------------------
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21 
library ieee;
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use ieee.std_logic_1164.all;
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use work.MIG_parameters_0.all;
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library UNISIM;
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use UNISIM.vcomponents.all;
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entity MIG_iobs_0 is
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  port(
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    ddr_ck           : out   std_logic_vector((CLK_WIDTH - 1) downto 0);
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    ddr_ck_n         : out   std_logic_vector((CLK_WIDTH - 1) downto 0);
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    clk              : in    std_logic;
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    clk90            : in    std_logic;
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    dqs_idelay_inc   : in    std_logic_vector((READENABLE - 1) downto 0);
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    dqs_idelay_ce    : in    std_logic_vector((READENABLE - 1) downto 0);
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    dqs_idelay_rst   : in    std_logic_vector((READENABLE - 1) downto 0);
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    data_idelay_inc  : in    std_logic_vector((READENABLE - 1) downto 0);
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    data_idelay_ce   : in    std_logic_vector((READENABLE - 1) downto 0);
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    data_idelay_rst  : in    std_logic_vector((READENABLE - 1) downto 0);
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    dqs_rst          : in    std_logic;
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    dqs_en           : in    std_logic;
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    wr_en            : in    std_logic;
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    wr_data_rise     : in    std_logic_vector((DATA_WIDTH - 1) downto 0);
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    wr_data_fall     : in    std_logic_vector((DATA_WIDTH - 1) downto 0);
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    mask_data_rise   : in    std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
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    mask_data_fall   : in    std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
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    rd_data_rise     : out   std_logic_vector((DATA_WIDTH - 1) downto 0);
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    rd_data_fall     : out   std_logic_vector((DATA_WIDTH - 1) downto 0);
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    dqs_delayed      : out   std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
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    ddr_dq           : inout std_logic_vector((DATA_WIDTH - 1) downto 0);
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    ddr_dqs          : inout std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
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    ddr_dm           : out   std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
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    ctrl_ddr_address : in    std_logic_vector((ROW_ADDRESS - 1) downto 0);
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    ctrl_ddr_ba      : in    std_logic_vector((BANK_ADDRESS - 1) downto 0);
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    ctrl_ddr_ras_l   : in    std_logic;
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    ctrl_ddr_cas_l   : in    std_logic;
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    ctrl_ddr_we_l    : in    std_logic;
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    ctrl_ddr_cs_l    : in    std_logic;
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    ctrl_ddr_cke     : in    std_logic;
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    ddr_address      : out   std_logic_vector((ROW_ADDRESS - 1) downto 0);
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    ddr_ba           : out   std_logic_vector((BANK_ADDRESS - 1) downto 0);
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    ddr_ras_l        : out   std_logic;
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    ddr_cas_l        : out   std_logic;
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    ddr_we_l         : out   std_logic;
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    ddr_cke          : out   std_logic;
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    ddr_cs_l         : out   std_logic
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    );
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end MIG_iobs_0;
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architecture arch of MIG_iobs_0 is
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  component MIG_infrastructure_iobs_0
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    port(
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      clk       : in std_logic;
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      ddr_ck    : out std_logic_vector((CLK_WIDTH - 1) downto 0);
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      ddr_ck_n  : out std_logic_vector((CLK_WIDTH - 1) downto 0)
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      );
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  end component;
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  component MIG_data_path_iobs_0
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    port (
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      clk             : in std_logic;
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      clk90           : in std_logic;
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      dqs_idelay_inc  : in std_logic_vector((READENABLE - 1) downto 0);
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      dqs_idelay_ce   : in std_logic_vector((READENABLE - 1) downto 0);
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      dqs_idelay_rst  : in std_logic_vector((READENABLE - 1) downto 0);
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      dqs_rst         : in std_logic;
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      dqs_en          : in std_logic;
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      dqs_delayed     : out std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
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      data_idelay_inc : in std_logic_vector((READENABLE - 1) downto 0);
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      data_idelay_ce  : in std_logic_vector((READENABLE - 1) downto 0);
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      data_idelay_rst : in std_logic_vector((READENABLE - 1) downto 0);
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      wr_data_rise    : in std_logic_vector((DATA_WIDTH - 1) downto 0);
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      wr_data_fall    : in std_logic_vector((DATA_WIDTH - 1) downto 0);
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      wr_en           : in std_logic;
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      rd_data_rise    : out std_logic_vector((DATA_WIDTH - 1) downto 0);
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      rd_data_fall    : out std_logic_vector((DATA_WIDTH - 1) downto 0);
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      mask_data_rise  : in std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
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      mask_data_fall  : in std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
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      ddr_dq          : inout std_logic_vector((DATA_WIDTH - 1) downto 0);
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      ddr_dqs         : inout std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
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      ddr_dm          : out std_logic_vector((DATA_MASK_WIDTH - 1) downto 0)
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      );
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  end component;
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  component MIG_controller_iobs_0
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    port (
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      ctrl_ddr_address : in  std_logic_vector((ROW_ADDRESS - 1) downto 0);
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      ctrl_ddr_ba      : in  std_logic_vector((BANK_ADDRESS - 1) downto 0);
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      ctrl_ddr_ras_l   : in  std_logic;
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      ctrl_ddr_cas_l   : in  std_logic;
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      ctrl_ddr_we_l    : in  std_logic;
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      ctrl_ddr_cs_l    : in  std_logic;
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      ctrl_ddr_cke     : in  std_logic;
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      ddr_address      : out std_logic_vector((ROW_ADDRESS - 1) downto 0);
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      ddr_ba           : out std_logic_vector((BANK_ADDRESS - 1) downto 0);
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      ddr_ras_l        : out std_logic;
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      ddr_cas_l        : out std_logic;
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      ddr_we_l         : out std_logic;
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      ddr_cke          : out std_logic;
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      ddr_cs_l         : out std_logic
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      );
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  end component;
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begin
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  infrastructure_iobs_00: MIG_infrastructure_iobs_0
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    port map   (
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      clk       => clk,
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      ddr_ck    => ddr_ck,
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      ddr_ck_n  => ddr_ck_n
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      );
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  data_path_iobs_00: MIG_data_path_iobs_0
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    port map    (
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      clk                       => clk,
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      clk90                     => clk90,
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      dqs_idelay_inc            => dqs_idelay_inc,
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      dqs_idelay_ce             => dqs_idelay_ce,
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      dqs_idelay_rst            => dqs_idelay_rst,
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      dqs_rst                   => dqs_rst,
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      dqs_en                    => dqs_en,
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      dqs_delayed               => dqs_delayed,
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      data_idelay_inc           => data_idelay_inc,
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      data_idelay_ce            => data_idelay_ce,
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      data_idelay_rst           => data_idelay_rst,
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      wr_data_rise              => wr_data_rise,
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      wr_data_fall              => wr_data_fall,
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      wr_en                     => wr_en,
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      rd_data_rise              => rd_data_rise,
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      rd_data_fall              => rd_data_fall,
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      mask_data_rise            => mask_data_rise,
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      mask_data_fall            => mask_data_fall,
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      ddr_dq                    => ddr_dq,
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      ddr_dqs                   => ddr_dqs,
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      ddr_dm                    => ddr_dm
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      );
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  controller_iobs_00: MIG_controller_iobs_0
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    port map     (
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      ctrl_ddr_address => ctrl_ddr_address,
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      ctrl_ddr_ba      => ctrl_ddr_ba,
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      ctrl_ddr_ras_l   => ctrl_ddr_ras_l,
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      ctrl_ddr_cas_l   => ctrl_ddr_cas_l,
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      ctrl_ddr_we_l    => ctrl_ddr_we_l,
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      ctrl_ddr_cs_l    => ctrl_ddr_cs_l,
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      ctrl_ddr_cke     => ctrl_ddr_cke,
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      ddr_address      => ddr_address,
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      ddr_ba           => ddr_ba,
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      ddr_ras_l        => ddr_ras_l,
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      ddr_cas_l        => ddr_cas_l,
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      ddr_we_l         => ddr_we_l,
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      ddr_cke          => ddr_cke,
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      ddr_cs_l         => ddr_cs_l
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      );
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end arch;

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