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[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [Memory Design/] [MIG_top_00/] [MIG_top_0.vhd] - Blame information for rev 24

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-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor             : Xilinx
-- \   \   \/    Version            : $Name: i+IP+131489 $
--  \   \        Application        : MIG
--  /   /        Filename           : MIG_top_0.vhd
-- /___/   /\    Date Last Modified : $Date: 2007/09/21 15:23:24 $
-- \   \  /  \   Date Created       : Mon May 2 2005
--  \___\/\___\
--
-- Device      : Virtex-4
-- Design Name : DDR SDRAM
-- Description: Instantiates the main design logic of memory interface and
--              interfaces with the user.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use work.MIG_parameters_0.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_top_0 is
  port(
    clk_0              : in    std_logic;
    clk_90             : in    std_logic;
    idelay_ctrl_rdy    : in    std_logic;
    sys_rst            : in    std_logic;
    sys_rst90          : in    std_logic;
    ddr_ras_n          : out   std_logic;
    ddr_cas_n          : out   std_logic;
    ddr_we_n           : out   std_logic;
    ddr_cke            : out   std_logic;
    ddr_cs_n           : out   std_logic;
    ddr_dq             : inout std_logic_vector((DATA_WIDTH - 1) downto 0);
    ddr_dqs            : inout std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
ddr_dm                 : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
    app_mask_data          : in std_logic_vector((DATA_MASK_WIDTH*2 -1) downto 0);
 
    ddr_ck             : out   std_logic_vector((CLK_WIDTH - 1) downto 0);
    ddr_ck_n           : out   std_logic_vector((CLK_WIDTH - 1) downto 0);
    ddr_ba             : out   std_logic_vector((BANK_ADDRESS - 1) downto 0);
    ddr_a              : out   std_logic_vector((ROW_ADDRESS - 1) downto 0);
    wdf_almost_full    : out   std_logic;
    af_almost_full     : out   std_logic;
    burst_length_div2  : out   std_logic_vector(2 downto 0);
    read_data_valid    : out   std_logic;
    read_data_fifo_out : out   std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
    app_af_addr        : in    std_logic_vector(35 downto 0);
    app_af_wren        : in    std_logic;
    app_wdf_data       : in    std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
    app_wdf_wren       : in    std_logic;
    init_done          : out   std_logic;
    clk_tb             : out   std_logic;
    reset_tb           : out   std_logic
    );
end MIG_top_0;
 
architecture arch of MIG_top_0 is
 
  component MIG_data_path_0
    port(
      clk                  : in  std_logic;
      clk90                : in  std_logic;
      reset0               : in  std_logic;
      reset90              : in  std_logic;
      idelay_ctrl_rdy      : in  std_logic;
      dummy_write_pattern  : in  std_logic;
      ctrl_dummyread_start : in  std_logic;
      wdf_data             : in  std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
      mask_data            : in  std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);
      ctrl_wren            : in  std_logic;
      ctrl_dqs_rst         : in  std_logic;
      ctrl_dqs_en          : in  std_logic;
      dqs_delayed          : in  std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
      data_idelay_inc      : out std_logic_vector((READENABLE - 1) downto 0);
      data_idelay_ce       : out std_logic_vector((READENABLE - 1) downto 0);
      data_idelay_rst      : out std_logic_vector((READENABLE - 1) downto 0);
      dqs_idelay_inc       : out std_logic_vector((READENABLE - 1) downto 0);
      dqs_idelay_ce        : out std_logic_vector((READENABLE - 1) downto 0);
      dqs_idelay_rst       : out std_logic_vector((READENABLE - 1) downto 0);
      sel_done             : out std_logic;
      dqs_rst              : out std_logic;
      dqs_en               : out std_logic;
      wr_en                : out std_logic;
      wr_data_rise         : out std_logic_vector((DATA_WIDTH - 1) downto 0);
      wr_data_fall         : out std_logic_vector((DATA_WIDTH - 1) downto 0);
      mask_data_rise       : out std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
      mask_data_fall       : out std_logic_vector((DATA_MASK_WIDTH - 1) downto 0)
      );
  end component;
 
  component MIG_iobs_0
    port(
      ddr_ck           : out   std_logic_vector((CLK_WIDTH - 1) downto 0);
      ddr_ck_n         : out   std_logic_vector((CLK_WIDTH - 1) downto 0);
      clk              : in    std_logic;
      clk90            : in    std_logic;
      dqs_idelay_inc   : in    std_logic_vector((READENABLE - 1) downto 0);
      dqs_idelay_ce    : in    std_logic_vector((READENABLE - 1) downto 0);
      dqs_idelay_rst   : in    std_logic_vector((READENABLE - 1) downto 0);
      data_idelay_inc  : in    std_logic_vector((READENABLE - 1) downto 0);
      data_idelay_ce   : in    std_logic_vector((READENABLE - 1) downto 0);
      data_idelay_rst  : in    std_logic_vector((READENABLE - 1) downto 0);
      dqs_rst          : in    std_logic;
      dqs_en           : in    std_logic;
      wr_en            : in    std_logic;
      wr_data_rise     : in    std_logic_vector((DATA_WIDTH - 1) downto 0);
      wr_data_fall     : in    std_logic_vector((DATA_WIDTH - 1) downto 0);
      mask_data_rise   : in    std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
      mask_data_fall   : in    std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
      rd_data_rise     : out   std_logic_vector((DATA_WIDTH - 1) downto 0);
      rd_data_fall     : out   std_logic_vector((DATA_WIDTH - 1) downto 0);
      dqs_delayed      : out   std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
      ddr_dq           : inout std_logic_vector((DATA_WIDTH - 1) downto 0);
      ddr_dqs          : inout std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
      ddr_dm           : out   std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
      ctrl_ddr_address : in    std_logic_vector((ROW_ADDRESS - 1) downto 0);
      ctrl_ddr_ba      : in    std_logic_vector((BANK_ADDRESS - 1) downto 0);
      ctrl_ddr_ras_l   : in    std_logic;
      ctrl_ddr_cas_l   : in    std_logic;
      ctrl_ddr_we_l    : in    std_logic;
      ctrl_ddr_cs_l    : in    std_logic;
      ctrl_ddr_cke     : in    std_logic;
      ddr_address      : out   std_logic_vector((ROW_ADDRESS - 1) downto 0);
      ddr_ba           : out   std_logic_vector((BANK_ADDRESS - 1) downto 0);
      ddr_ras_l        : out   std_logic;
      ddr_cas_l        : out   std_logic;
      ddr_we_l         : out   std_logic;
      ddr_cke          : out   std_logic;
      ddr_cs_l         : out   std_logic
      );
  end component;
 
  component MIG_user_interface_0
    port(
      clk                : in  std_logic;
      clk90              : in  std_logic;
      reset              : in  std_logic;
      ctrl_rden          : in  std_logic;
      read_data_rise     : in  std_logic_vector((DATA_WIDTH - 1) downto 0);
      read_data_fall     : in  std_logic_vector((DATA_WIDTH - 1) downto 0);
      read_data_fifo_out : out std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
      comp_done          : out std_logic;
      read_data_valid    : out std_logic;
      af_empty           : out std_logic;
      af_almost_full     : out std_logic;
      app_af_addr        : in  std_logic_vector(35 downto 0);
      app_af_wren        : in  std_logic;
      ctrl_af_rden       : in  std_logic;
      af_addr            : out std_logic_vector(35 downto 0);
      app_wdf_data       : in  std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
      app_mask_data      : in  std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);
      app_wdf_wren       : in  std_logic;
      ctrl_wdf_rden      : in  std_logic;
      wdf_data           : out std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
      mask_data          : out std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);
      wdf_almost_full    : out std_logic
      );
  end component;
 
  component MIG_ddr_controller_0
    port(
      clk_0                : in  std_logic;
      rst                  : in  std_logic;
      af_addr              : in  std_logic_vector(35 downto 0);
      af_empty             : in  std_logic;
      comp_done            : in  std_logic;
      phy_dly_slct_done    : in  std_logic;
      ctrl_dummyread_start : out std_logic;
      ctrl_af_rden         : out std_logic;
      ctrl_wdf_rden        : out std_logic;
      ctrl_dqs_rst         : out std_logic;
      ctrl_dqs_en          : out std_logic;
      ctrl_wren            : out std_logic;
      ctrl_rden            : out std_logic;
      ctrl_ddr_address     : out std_logic_vector((ROW_ADDRESS - 1) downto 0);
      ctrl_ddr_ba          : out std_logic_vector((BANK_ADDRESS - 1) downto 0);
      ctrl_ddr_ras_l       : out std_logic;
      ctrl_ddr_cas_l       : out std_logic;
      ctrl_ddr_we_l        : out std_logic;
      ctrl_ddr_cs_l        : out std_logic;
      ctrl_ddr_cke         : out std_logic;
      init_done            : out std_logic;
      dummy_write_pattern  : out std_logic;
      burst_length_div2    : out std_logic_vector(2 downto 0)
      );
  end component;
 
 
 
  signal wr_df_data          : std_logic_vector((DATA_WIDTH*2 - 1) downto 0);
  signal mask_df_data        : std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);
  signal rd_data_rise        : std_logic_vector((DATA_WIDTH - 1) downto 0);
  signal rd_data_fall        : std_logic_vector((DATA_WIDTH - 1) downto 0);
  signal af_empty_w          : std_logic;
  signal dq_tap_sel_done     : std_logic;
  signal af_addr             : std_logic_vector(35 downto 0);
  signal ctrl_af_rden        : std_logic;
  signal ctrl_wr_df_rden     : std_logic;
  signal ctrl_dummy_rden     : std_logic;
  signal ctrl_dqs_enable     : std_logic;
  signal ctrl_dqs_reset      : std_logic;
  signal ctrl_wr_en          : std_logic;
  signal ctrl_rden           : std_logic;
  signal dqs_idelay_inc      : std_logic_vector((READENABLE - 1) downto 0);
  signal dqs_idelay_ce       : std_logic_vector((READENABLE - 1) downto 0);
  signal dqs_idelay_rst      : std_logic_vector((READENABLE - 1) downto 0);
  signal data_idelay_inc     : std_logic_vector((READENABLE - 1) downto 0);
  signal data_idelay_ce      : std_logic_vector((READENABLE - 1) downto 0);
  signal data_idelay_rst     : std_logic_vector((READENABLE - 1) downto 0);
  signal wr_en               : std_logic;
  signal dqs_rst             : std_logic;
  signal dqs_en              : std_logic;
  signal wr_data_rise        : std_logic_vector((DATA_WIDTH - 1) downto 0);
  signal wr_data_fall        : std_logic_vector((DATA_WIDTH - 1) downto 0);
  signal dqs_delayed         : std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);
  signal mask_data_fall      : std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
  signal mask_data_rise      : std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);
  signal ctrl_ddr_address    : std_logic_vector((ROW_ADDRESS - 1) downto 0);
  signal ctrl_ddr_ba         : std_logic_vector((BANK_ADDRESS - 1) downto 0);
  signal ctrl_ddr_ras_l      : std_logic;
  signal ctrl_ddr_cas_l      : std_logic;
  signal ctrl_ddr_we_l       : std_logic;
  signal ctrl_ddr_cs_l       : std_logic;
  signal ctrl_ddr_cke        : std_logic;
  signal duMmy_write_pattern : std_logic;
  signal comp_done       : std_logic;
 
 
 
begin
 
  clk_tb    <= clk_0;
  reset_tb  <= sys_rst;
 
 
 
  data_path_00 : MIG_data_path_0
    port map (
      clk                  => clk_0,
      clk90                => clk_90,
      reset0               => sys_rst,
      reset90              => sys_rst90,
      idelay_ctrl_rdy      => idelay_ctrl_rdy,
      dummy_write_pattern  => dummy_write_pattern,
      ctrl_dummyread_start => ctrl_dummy_rden,
      wdf_data             => wr_df_data,
      mask_data            => mask_df_data,
      ctrl_wren            => ctrl_wr_en,
      ctrl_dqs_rst         => ctrl_dqs_reset,
      ctrl_dqs_en          => ctrl_dqs_enable,
      dqs_delayed          => dqs_delayed,
      data_idelay_inc      => data_idelay_inc,
      data_idelay_ce       => data_idelay_ce,
      data_idelay_rst      => data_idelay_rst,
      dqs_idelay_inc       => dqs_idelay_inc,
      dqs_idelay_ce        => dqs_idelay_ce,
      dqs_idelay_rst       => dqs_idelay_rst,
      sel_done             => dq_tap_sel_done,
      dqs_rst              => dqs_rst,
      dqs_en               => dqs_en,
      wr_en                => wr_en,
      wr_data_rise         => wr_data_rise,
      wr_data_fall         => wr_data_fall,
      mask_data_rise       => mask_data_rise,
      mask_data_fall       => mask_data_fall
      );
 
  iobs_00 : MIG_iobs_0
    port map (
      ddr_ck           => ddr_ck,
      ddr_ck_n         => ddr_ck_n,
      clk              => clk_0,
      clk90            => clk_90,
      dqs_idelay_inc   => dqs_idelay_inc,
      dqs_idelay_ce    => dqs_idelay_ce,
      dqs_idelay_rst   => dqs_idelay_rst,
      data_idelay_inc  => data_idelay_inc,
      data_idelay_ce   => data_idelay_ce,
      data_idelay_rst  => data_idelay_rst,
      dqs_rst          => dqs_rst,
      dqs_en           => dqs_en,
      wr_en            => wr_en,
      wr_data_rise     => wr_data_rise,
      wr_data_fall     => wr_data_fall,
      mask_data_rise   => mask_data_rise,
      mask_data_fall   => mask_data_fall,
      rd_data_rise     => rd_data_rise,
      rd_data_fall     => rd_data_fall,
      dqs_delayed      => dqs_delayed,
      ddr_dq           => ddr_dq,
      ddr_dqs          => ddr_dqs,
      ddr_dm           => ddr_dm,
      ctrl_ddr_address => ctrl_ddr_address,
      ctrl_ddr_ba      => ctrl_ddr_ba,
      ctrl_ddr_ras_l   => ctrl_ddr_ras_l,
      ctrl_ddr_cas_l   => ctrl_ddr_cas_l,
      ctrl_ddr_we_l    => ctrl_ddr_we_l,
      ctrl_ddr_cs_l    => ctrl_ddr_cs_l,
      ctrl_ddr_cke     => ctrl_ddr_cke,
      ddr_address      => ddr_a,
      ddr_ba           => ddr_ba,
      ddr_ras_l        => ddr_ras_n,
      ddr_cas_l        => ddr_cas_n,
      ddr_we_l         => ddr_we_n,
      ddr_cke          => ddr_cke,
      ddr_cs_l         => ddr_cs_n
      );
 
  user_interface_00 : MIG_user_interface_0
    port map (
      clk                => clk_0,
      clk90              => clk_90,
      reset              => sys_rst,
      ctrl_rden          => ctrl_rden,
      read_data_rise     => rd_data_rise,
      read_data_fall     => rd_data_fall,
      read_data_fifo_out => read_data_fifo_out,
      comp_done          => comp_done,
      read_data_valid    => read_data_valid,
      af_empty           => af_empty_w,
      af_almost_full     => af_almost_full,
      app_af_addr        => app_af_addr,
      app_af_wren        => app_af_wren,
      ctrl_af_rden       => ctrl_af_rden,
      af_addr            => af_addr,
      app_wdf_data       => app_wdf_data,
      app_mask_data      => app_mask_data,
      app_wdf_wren       => app_wdf_wren,
      ctrl_wdf_rden      => ctrl_wr_df_rden,
      wdf_data           => wr_df_data,
      mask_data          => mask_df_data,
      wdf_almost_full    => wdf_almost_full
      );
 
  ddr_controller_00 : MIG_ddr_controller_0
    port map (
      clk_0                => clk_0,
      rst                  => sys_rst,
      af_addr              => af_addr,
      af_empty             => af_empty_w,
      phy_dly_slct_done    => dq_tap_sel_done,
      comp_done            => comp_done,
      ctrl_dummyread_start => ctrl_dummy_rden,
      ctrl_af_rden         => ctrl_af_rden,
      ctrl_wdf_rden        => ctrl_wr_df_rden,
      ctrl_dqs_rst         => ctrl_dqs_reset,
      ctrl_dqs_en          => ctrl_dqs_enable,
      ctrl_wren            => ctrl_wr_en,
      ctrl_rden            => ctrl_rden,
      ctrl_ddr_address     => ctrl_ddr_address,
      ctrl_ddr_ba          => ctrl_ddr_ba,
      ctrl_ddr_ras_l       => ctrl_ddr_ras_l,
      ctrl_ddr_cas_l       => ctrl_ddr_cas_l,
      ctrl_ddr_we_l        => ctrl_ddr_we_l,
      ctrl_ddr_cs_l        => ctrl_ddr_cs_l,
      ctrl_ddr_cke         => ctrl_ddr_cke,
      init_done            => init_done,
      dummy_write_pattern  => dummy_write_pattern,
      burst_length_div2    => burst_length_div2
      );
 
 
end arch;

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Subversion Repositories the_wizardry_project

[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [Memory Design/] [MIG_top_00/] [MIG_top_0.vhd] - Blame information for rev 24

Line No.	Rev	Author	Line
1	24	mcwaccent	`-------------------------------------------------------------------------------`
2			`-- Copyright (c) 2005-2007 Xilinx, Inc.`
3			`-- This design is confidential and proprietary of Xilinx, All Rights Reserved.`
4			`-------------------------------------------------------------------------------`
5			`-- ____ ____`
6			`-- / /\/ /`
7			`-- /___/ \ / Vendor : Xilinx`
8			`-- \ \ \/ Version : $Name: i+IP+131489 $`
9			`-- \ \ Application : MIG`
10			`-- / / Filename : MIG_top_0.vhd`
11			`-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:24 $`
12			`-- \ \ / \ Date Created : Mon May 2 2005`
13			`-- \___\/\___\`
14			`--`
15			`-- Device : Virtex-4`
16			`-- Design Name : DDR SDRAM`
17			`-- Description: Instantiates the main design logic of memory interface and`
18			`-- interfaces with the user.`
19			`-------------------------------------------------------------------------------`
20
21			`library ieee;`
22			`use ieee.std_logic_1164.all;`
23			`use work.MIG_parameters_0.all;`
24			`library UNISIM;`
25			`use UNISIM.vcomponents.all;`
26
27			`entity MIG_top_0 is`
28			`port(`
29			`clk_0 : in std_logic;`
30			`clk_90 : in std_logic;`
31			`idelay_ctrl_rdy : in std_logic;`
32			`sys_rst : in std_logic;`
33			`sys_rst90 : in std_logic;`
34			`ddr_ras_n : out std_logic;`
35			`ddr_cas_n : out std_logic;`
36			`ddr_we_n : out std_logic;`
37			`ddr_cke : out std_logic;`
38			`ddr_cs_n : out std_logic;`
39			`ddr_dq : inout std_logic_vector((DATA_WIDTH - 1) downto 0);`
40			`ddr_dqs : inout std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);`
41			`ddr_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);`
42			`app_mask_data : in std_logic_vector((DATA_MASK_WIDTH*2 -1) downto 0);`
43
44			`ddr_ck : out std_logic_vector((CLK_WIDTH - 1) downto 0);`
45			`ddr_ck_n : out std_logic_vector((CLK_WIDTH - 1) downto 0);`
46			`ddr_ba : out std_logic_vector((BANK_ADDRESS - 1) downto 0);`
47			`ddr_a : out std_logic_vector((ROW_ADDRESS - 1) downto 0);`
48			`wdf_almost_full : out std_logic;`
49			`af_almost_full : out std_logic;`
50			`burst_length_div2 : out std_logic_vector(2 downto 0);`
51			`read_data_valid : out std_logic;`
52			`read_data_fifo_out : out std_logic_vector((DATA_WIDTH*2 - 1) downto 0);`
53			`app_af_addr : in std_logic_vector(35 downto 0);`
54			`app_af_wren : in std_logic;`
55			`app_wdf_data : in std_logic_vector((DATA_WIDTH*2 - 1) downto 0);`
56			`app_wdf_wren : in std_logic;`
57			`init_done : out std_logic;`
58			`clk_tb : out std_logic;`
59			`reset_tb : out std_logic`
60			`);`
61			`end MIG_top_0;`
62
63			`architecture arch of MIG_top_0 is`
64
65			`component MIG_data_path_0`
66			`port(`
67			`clk : in std_logic;`
68			`clk90 : in std_logic;`
69			`reset0 : in std_logic;`
70			`reset90 : in std_logic;`
71			`idelay_ctrl_rdy : in std_logic;`
72			`dummy_write_pattern : in std_logic;`
73			`ctrl_dummyread_start : in std_logic;`
74			`wdf_data : in std_logic_vector((DATA_WIDTH*2 - 1) downto 0);`
75			`mask_data : in std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);`
76			`ctrl_wren : in std_logic;`
77			`ctrl_dqs_rst : in std_logic;`
78			`ctrl_dqs_en : in std_logic;`
79			`dqs_delayed : in std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);`
80			`data_idelay_inc : out std_logic_vector((READENABLE - 1) downto 0);`
81			`data_idelay_ce : out std_logic_vector((READENABLE - 1) downto 0);`
82			`data_idelay_rst : out std_logic_vector((READENABLE - 1) downto 0);`
83			`dqs_idelay_inc : out std_logic_vector((READENABLE - 1) downto 0);`
84			`dqs_idelay_ce : out std_logic_vector((READENABLE - 1) downto 0);`
85			`dqs_idelay_rst : out std_logic_vector((READENABLE - 1) downto 0);`
86			`sel_done : out std_logic;`
87			`dqs_rst : out std_logic;`
88			`dqs_en : out std_logic;`
89			`wr_en : out std_logic;`
90			`wr_data_rise : out std_logic_vector((DATA_WIDTH - 1) downto 0);`
91			`wr_data_fall : out std_logic_vector((DATA_WIDTH - 1) downto 0);`
92			`mask_data_rise : out std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);`
93			`mask_data_fall : out std_logic_vector((DATA_MASK_WIDTH - 1) downto 0)`
94			`);`
95			`end component;`
96
97			`component MIG_iobs_0`
98			`port(`
99			`ddr_ck : out std_logic_vector((CLK_WIDTH - 1) downto 0);`
100			`ddr_ck_n : out std_logic_vector((CLK_WIDTH - 1) downto 0);`
101			`clk : in std_logic;`
102			`clk90 : in std_logic;`
103			`dqs_idelay_inc : in std_logic_vector((READENABLE - 1) downto 0);`
104			`dqs_idelay_ce : in std_logic_vector((READENABLE - 1) downto 0);`
105			`dqs_idelay_rst : in std_logic_vector((READENABLE - 1) downto 0);`
106			`data_idelay_inc : in std_logic_vector((READENABLE - 1) downto 0);`
107			`data_idelay_ce : in std_logic_vector((READENABLE - 1) downto 0);`
108			`data_idelay_rst : in std_logic_vector((READENABLE - 1) downto 0);`
109			`dqs_rst : in std_logic;`
110			`dqs_en : in std_logic;`
111			`wr_en : in std_logic;`
112			`wr_data_rise : in std_logic_vector((DATA_WIDTH - 1) downto 0);`
113			`wr_data_fall : in std_logic_vector((DATA_WIDTH - 1) downto 0);`
114			`mask_data_rise : in std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);`
115			`mask_data_fall : in std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);`
116			`rd_data_rise : out std_logic_vector((DATA_WIDTH - 1) downto 0);`
117			`rd_data_fall : out std_logic_vector((DATA_WIDTH - 1) downto 0);`
118			`dqs_delayed : out std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);`
119			`ddr_dq : inout std_logic_vector((DATA_WIDTH - 1) downto 0);`
120			`ddr_dqs : inout std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);`
121			`ddr_dm : out std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);`
122			`ctrl_ddr_address : in std_logic_vector((ROW_ADDRESS - 1) downto 0);`
123			`ctrl_ddr_ba : in std_logic_vector((BANK_ADDRESS - 1) downto 0);`
124			`ctrl_ddr_ras_l : in std_logic;`
125			`ctrl_ddr_cas_l : in std_logic;`
126			`ctrl_ddr_we_l : in std_logic;`
127			`ctrl_ddr_cs_l : in std_logic;`
128			`ctrl_ddr_cke : in std_logic;`
129			`ddr_address : out std_logic_vector((ROW_ADDRESS - 1) downto 0);`
130			`ddr_ba : out std_logic_vector((BANK_ADDRESS - 1) downto 0);`
131			`ddr_ras_l : out std_logic;`
132			`ddr_cas_l : out std_logic;`
133			`ddr_we_l : out std_logic;`
134			`ddr_cke : out std_logic;`
135			`ddr_cs_l : out std_logic`
136			`);`
137			`end component;`
138
139			`component MIG_user_interface_0`
140			`port(`
141			`clk : in std_logic;`
142			`clk90 : in std_logic;`
143			`reset : in std_logic;`
144			`ctrl_rden : in std_logic;`
145			`read_data_rise : in std_logic_vector((DATA_WIDTH - 1) downto 0);`
146			`read_data_fall : in std_logic_vector((DATA_WIDTH - 1) downto 0);`
147			`read_data_fifo_out : out std_logic_vector((DATA_WIDTH*2 - 1) downto 0);`
148			`comp_done : out std_logic;`
149			`read_data_valid : out std_logic;`
150			`af_empty : out std_logic;`
151			`af_almost_full : out std_logic;`
152			`app_af_addr : in std_logic_vector(35 downto 0);`
153			`app_af_wren : in std_logic;`
154			`ctrl_af_rden : in std_logic;`
155			`af_addr : out std_logic_vector(35 downto 0);`
156			`app_wdf_data : in std_logic_vector((DATA_WIDTH*2 - 1) downto 0);`
157			`app_mask_data : in std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);`
158			`app_wdf_wren : in std_logic;`
159			`ctrl_wdf_rden : in std_logic;`
160			`wdf_data : out std_logic_vector((DATA_WIDTH*2 - 1) downto 0);`
161			`mask_data : out std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);`
162			`wdf_almost_full : out std_logic`
163			`);`
164			`end component;`
165
166			`component MIG_ddr_controller_0`
167			`port(`
168			`clk_0 : in std_logic;`
169			`rst : in std_logic;`
170			`af_addr : in std_logic_vector(35 downto 0);`
171			`af_empty : in std_logic;`
172			`comp_done : in std_logic;`
173			`phy_dly_slct_done : in std_logic;`
174			`ctrl_dummyread_start : out std_logic;`
175			`ctrl_af_rden : out std_logic;`
176			`ctrl_wdf_rden : out std_logic;`
177			`ctrl_dqs_rst : out std_logic;`
178			`ctrl_dqs_en : out std_logic;`
179			`ctrl_wren : out std_logic;`
180			`ctrl_rden : out std_logic;`
181			`ctrl_ddr_address : out std_logic_vector((ROW_ADDRESS - 1) downto 0);`
182			`ctrl_ddr_ba : out std_logic_vector((BANK_ADDRESS - 1) downto 0);`
183			`ctrl_ddr_ras_l : out std_logic;`
184			`ctrl_ddr_cas_l : out std_logic;`
185			`ctrl_ddr_we_l : out std_logic;`
186			`ctrl_ddr_cs_l : out std_logic;`
187			`ctrl_ddr_cke : out std_logic;`
188			`init_done : out std_logic;`
189			`dummy_write_pattern : out std_logic;`
190			`burst_length_div2 : out std_logic_vector(2 downto 0)`
191			`);`
192			`end component;`
193
194
195
196			`signal wr_df_data : std_logic_vector((DATA_WIDTH*2 - 1) downto 0);`
197			`signal mask_df_data : std_logic_vector((DATA_MASK_WIDTH*2 - 1) downto 0);`
198			`signal rd_data_rise : std_logic_vector((DATA_WIDTH - 1) downto 0);`
199			`signal rd_data_fall : std_logic_vector((DATA_WIDTH - 1) downto 0);`
200			`signal af_empty_w : std_logic;`
201			`signal dq_tap_sel_done : std_logic;`
202			`signal af_addr : std_logic_vector(35 downto 0);`
203			`signal ctrl_af_rden : std_logic;`
204			`signal ctrl_wr_df_rden : std_logic;`
205			`signal ctrl_dummy_rden : std_logic;`
206			`signal ctrl_dqs_enable : std_logic;`
207			`signal ctrl_dqs_reset : std_logic;`
208			`signal ctrl_wr_en : std_logic;`
209			`signal ctrl_rden : std_logic;`
210			`signal dqs_idelay_inc : std_logic_vector((READENABLE - 1) downto 0);`
211			`signal dqs_idelay_ce : std_logic_vector((READENABLE - 1) downto 0);`
212			`signal dqs_idelay_rst : std_logic_vector((READENABLE - 1) downto 0);`
213			`signal data_idelay_inc : std_logic_vector((READENABLE - 1) downto 0);`
214			`signal data_idelay_ce : std_logic_vector((READENABLE - 1) downto 0);`
215			`signal data_idelay_rst : std_logic_vector((READENABLE - 1) downto 0);`
216			`signal wr_en : std_logic;`
217			`signal dqs_rst : std_logic;`
218			`signal dqs_en : std_logic;`
219			`signal wr_data_rise : std_logic_vector((DATA_WIDTH - 1) downto 0);`
220			`signal wr_data_fall : std_logic_vector((DATA_WIDTH - 1) downto 0);`
221			`signal dqs_delayed : std_logic_vector((DATA_STROBE_WIDTH - 1) downto 0);`
222			`signal mask_data_fall : std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);`
223			`signal mask_data_rise : std_logic_vector((DATA_MASK_WIDTH - 1) downto 0);`
224			`signal ctrl_ddr_address : std_logic_vector((ROW_ADDRESS - 1) downto 0);`
225			`signal ctrl_ddr_ba : std_logic_vector((BANK_ADDRESS - 1) downto 0);`
226			`signal ctrl_ddr_ras_l : std_logic;`
227			`signal ctrl_ddr_cas_l : std_logic;`
228			`signal ctrl_ddr_we_l : std_logic;`
229			`signal ctrl_ddr_cs_l : std_logic;`
230			`signal ctrl_ddr_cke : std_logic;`
231			`signal duMmy_write_pattern : std_logic;`
232			`signal comp_done : std_logic;`
233
234
235
236			`begin`
237
238			`clk_tb <= clk_0;`
239			`reset_tb <= sys_rst;`
240
241
242
243			`data_path_00 : MIG_data_path_0`
244			`port map (`
245			`clk => clk_0,`
246			`clk90 => clk_90,`
247			`reset0 => sys_rst,`
248			`reset90 => sys_rst90,`
249			`idelay_ctrl_rdy => idelay_ctrl_rdy,`
250			`dummy_write_pattern => dummy_write_pattern,`
251			`ctrl_dummyread_start => ctrl_dummy_rden,`
252			`wdf_data => wr_df_data,`
253			`mask_data => mask_df_data,`
254			`ctrl_wren => ctrl_wr_en,`
255			`ctrl_dqs_rst => ctrl_dqs_reset,`
256			`ctrl_dqs_en => ctrl_dqs_enable,`
257			`dqs_delayed => dqs_delayed,`
258			`data_idelay_inc => data_idelay_inc,`
259			`data_idelay_ce => data_idelay_ce,`
260			`data_idelay_rst => data_idelay_rst,`
261			`dqs_idelay_inc => dqs_idelay_inc,`
262			`dqs_idelay_ce => dqs_idelay_ce,`
263			`dqs_idelay_rst => dqs_idelay_rst,`
264			`sel_done => dq_tap_sel_done,`
265			`dqs_rst => dqs_rst,`
266			`dqs_en => dqs_en,`
267			`wr_en => wr_en,`
268			`wr_data_rise => wr_data_rise,`
269			`wr_data_fall => wr_data_fall,`
270			`mask_data_rise => mask_data_rise,`
271			`mask_data_fall => mask_data_fall`
272			`);`
273
274			`iobs_00 : MIG_iobs_0`
275			`port map (`
276			`ddr_ck => ddr_ck,`
277			`ddr_ck_n => ddr_ck_n,`
278			`clk => clk_0,`
279			`clk90 => clk_90,`
280			`dqs_idelay_inc => dqs_idelay_inc,`
281			`dqs_idelay_ce => dqs_idelay_ce,`
282			`dqs_idelay_rst => dqs_idelay_rst,`
283			`data_idelay_inc => data_idelay_inc,`
284			`data_idelay_ce => data_idelay_ce,`
285			`data_idelay_rst => data_idelay_rst,`
286			`dqs_rst => dqs_rst,`
287			`dqs_en => dqs_en,`
288			`wr_en => wr_en,`
289			`wr_data_rise => wr_data_rise,`
290			`wr_data_fall => wr_data_fall,`
291			`mask_data_rise => mask_data_rise,`
292			`mask_data_fall => mask_data_fall,`
293			`rd_data_rise => rd_data_rise,`
294			`rd_data_fall => rd_data_fall,`
295			`dqs_delayed => dqs_delayed,`
296			`ddr_dq => ddr_dq,`
297			`ddr_dqs => ddr_dqs,`
298			`ddr_dm => ddr_dm,`
299			`ctrl_ddr_address => ctrl_ddr_address,`
300			`ctrl_ddr_ba => ctrl_ddr_ba,`
301			`ctrl_ddr_ras_l => ctrl_ddr_ras_l,`
302			`ctrl_ddr_cas_l => ctrl_ddr_cas_l,`
303			`ctrl_ddr_we_l => ctrl_ddr_we_l,`
304			`ctrl_ddr_cs_l => ctrl_ddr_cs_l,`
305			`ctrl_ddr_cke => ctrl_ddr_cke,`
306			`ddr_address => ddr_a,`
307			`ddr_ba => ddr_ba,`
308			`ddr_ras_l => ddr_ras_n,`
309			`ddr_cas_l => ddr_cas_n,`
310			`ddr_we_l => ddr_we_n,`
311			`ddr_cke => ddr_cke,`
312			`ddr_cs_l => ddr_cs_n`
313			`);`
314
315			`user_interface_00 : MIG_user_interface_0`
316			`port map (`
317			`clk => clk_0,`
318			`clk90 => clk_90,`
319			`reset => sys_rst,`
320			`ctrl_rden => ctrl_rden,`
321			`read_data_rise => rd_data_rise,`
322			`read_data_fall => rd_data_fall,`
323			`read_data_fifo_out => read_data_fifo_out,`
324			`comp_done => comp_done,`
325			`read_data_valid => read_data_valid,`
326			`af_empty => af_empty_w,`
327			`af_almost_full => af_almost_full,`
328			`app_af_addr => app_af_addr,`
329			`app_af_wren => app_af_wren,`
330			`ctrl_af_rden => ctrl_af_rden,`
331			`af_addr => af_addr,`
332			`app_wdf_data => app_wdf_data,`
333			`app_mask_data => app_mask_data,`
334			`app_wdf_wren => app_wdf_wren,`
335			`ctrl_wdf_rden => ctrl_wr_df_rden,`
336			`wdf_data => wr_df_data,`
337			`mask_data => mask_df_data,`
338			`wdf_almost_full => wdf_almost_full`
339			`);`
340
341			`ddr_controller_00 : MIG_ddr_controller_0`
342			`port map (`
343			`clk_0 => clk_0,`
344			`rst => sys_rst,`
345			`af_addr => af_addr,`
346			`af_empty => af_empty_w,`
347			`phy_dly_slct_done => dq_tap_sel_done,`
348			`comp_done => comp_done,`
349			`ctrl_dummyread_start => ctrl_dummy_rden,`
350			`ctrl_af_rden => ctrl_af_rden,`
351			`ctrl_wdf_rden => ctrl_wr_df_rden,`
352			`ctrl_dqs_rst => ctrl_dqs_reset,`
353			`ctrl_dqs_en => ctrl_dqs_enable,`
354			`ctrl_wren => ctrl_wr_en,`
355			`ctrl_rden => ctrl_rden,`
356			`ctrl_ddr_address => ctrl_ddr_address,`
357			`ctrl_ddr_ba => ctrl_ddr_ba,`
358			`ctrl_ddr_ras_l => ctrl_ddr_ras_l,`
359			`ctrl_ddr_cas_l => ctrl_ddr_cas_l,`
360			`ctrl_ddr_we_l => ctrl_ddr_we_l,`
361			`ctrl_ddr_cs_l => ctrl_ddr_cs_l,`
362			`ctrl_ddr_cke => ctrl_ddr_cke,`
363			`init_done => init_done,`
364			`dummy_write_pattern => dummy_write_pattern,`
365			`burst_length_div2 => burst_length_div2`
366			`);`
367
368
369			`end arch;`