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[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [Memory Design/] [MIG_top_00/] [MIG_user_interface_0/] [MIG_rd_data_0/] [MIG_pattern_compare8.vhd] - Blame information for rev 24

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1 24 mcwaccent 
-------------------------------------------------------------------------------
2 
-- Copyright (c) 2005-2007 Xilinx, Inc.
3 
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
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-------------------------------------------------------------------------------
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--   ____  ____
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--  /   /\/   /
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-- /___/  \  /   Vendor             : Xilinx
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-- \   \   \/    Version            : $Name: i+IP+131489 $
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--  \   \        Application        : MIG
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--  /   /        Filename           : MIG_pattern_compare8.vhd
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-- /___/   /\    Date Last Modified : $Date: 2007/09/21 15:23:24 $
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-- \   \  /  \   Date Created       : Mon May 2 2005
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--  \___\/\___\
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--
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-- Device      : Virtex-4
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-- Design Name : DDR SDRAM
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-- Description: Compares the IOB output 8 bit data of one bank that is read
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--              data during the intilaization to get the delay for the data
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--              with respect to the command issued.
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-------------------------------------------------------------------------------
21 
 
22 
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library UNISIM;
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use UNISIM.vcomponents.all;
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28 
entity MIG_pattern_compare8 is
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  port(
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    clk            : in  std_logic;
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    rst            : in  std_logic;
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    ctrl_rden      : in  std_logic;
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    rd_data_rise   : in  std_logic_vector(7 downto 0);
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    rd_data_fall   : in  std_logic_vector(7 downto 0);
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    comp_done      : out std_logic;
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    first_rising   : out std_logic;
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    rise_clk_count : out std_logic_vector(2 downto 0);
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    fall_clk_count : out std_logic_vector(2 downto 0)
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    );
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end MIG_pattern_compare8;
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42 
architecture arch of MIG_pattern_compare8 is
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  constant IDLE        : std_logic_vector(1 downto 0) := "00";
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  constant FIRST_DATA  : std_logic_vector(1 downto 0) := "01";
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  constant SECOND_DATA : std_logic_vector(1 downto 0) := "10";
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  constant COMP_OVER   : std_logic_vector(1 downto 0) := "11";
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49 
  signal state_rise      : std_logic_vector(1 downto 0);
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  signal state_fall      : std_logic_vector(1 downto 0);
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  signal next_state_rise : std_logic_vector(1 downto 0);
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  signal next_state_fall : std_logic_vector(1 downto 0);
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  signal rise_clk_cnt    : std_logic_vector(2 downto 0);
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  signal fall_clk_cnt    : std_logic_vector(2 downto 0);
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  signal ctrl_rden_r     : std_logic;
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  signal pattern_rise1   : std_logic_vector(7 downto 0);
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  signal pattern_fall1   : std_logic_vector(7 downto 0);
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  signal pattern_rise2   : std_logic_vector(7 downto 0);
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  signal pattern_fall2   : std_logic_vector(7 downto 0);
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  signal rd_data_rise_r2 : std_logic_vector(7 downto 0);
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  signal rd_data_fall_r2 : std_logic_vector(7 downto 0);
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  signal rst_r           : std_logic;
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begin
64 
 
65 
  pattern_rise1 <= X"AA";
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  pattern_fall1 <= X"55";
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  pattern_rise2 <= X"99";
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  pattern_fall2 <= X"66";
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70 
  process(clk)
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  begin
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    if(clk'event and clk = '1') then
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      rst_r <= rst;
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    end if;
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  end process;
76 
 
77 
  process(clk)
78 
  begin
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    if(clk'event and clk = '1') then
80 
      if(rst_r = '1') then
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        state_rise <= IDLE;
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      else
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        state_rise <= next_state_rise;
84 
      end if;
85 
    end if;
86 
  end process;
87 
 
88 
  process(clk)
89 
  begin
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    if(clk'event and clk = '1') then
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      if(rst_r = '1') then
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        state_fall <= IDLE;
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      else
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        state_fall <= next_state_fall;
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      end if;
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    end if;
97 
  end process;
98 
 
99 
  process(clk)
100 
  begin
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    if(clk'event and clk = '1') then
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      if(rst_r = '1') then
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        ctrl_rden_r <= '0';
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      else
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        ctrl_rden_r <= ctrl_rden;
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      end if;
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    end if;
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  end process;
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110 
  process(clk)
111 
  begin
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    if(clk'event and clk = '1') then
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      if(rst_r = '1') then
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        rise_clk_cnt <= "000";
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      elsif((state_rise = FIRST_DATA) or (state_rise = SECOND_DATA)) then
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        rise_clk_cnt <= rise_clk_cnt + '1';
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      end if;
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    end if;
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  end process;
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  rise_clk_count <= rise_clk_cnt when (state_rise = COMP_OVER) else "000";
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123 
  comp_done <= '1' when ((state_rise = COMP_OVER) and (state_fall = COMP_OVER))
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               else '0';
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126 
  process(clk)
127 
  begin
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    if(clk'event and clk = '1') then
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      if(rst_r = '1') then
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        fall_clk_cnt <= "000";
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      elsif((state_fall = FIRST_DATA) or (state_fall = SECOND_DATA)) then
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        fall_clk_cnt <= fall_clk_cnt + '1';
133 
      end if;
134 
    end if;
135 
  end process;
136 
 
137 
  fall_clk_count <= fall_clk_cnt when (state_fall = COMP_OVER) else "000";
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139 
  process(clk)
140 
  begin
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    if (clk = '1' and clk'event) then
142 
      if (rst_r = '1') then
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        first_rising <= '0';
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      elsif(state_rise = SECOND_DATA and rd_data_rise = pattern_fall2
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           and rd_data_rise_r2 = pattern_fall1) then
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        first_rising <= '1';
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      end if;
148 
    end if;
149 
  end process;
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  process(clk)
152 
  begin
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    if (clk = '1' and clk'event) then
154 
      if (rst_r = '1') then
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        rd_data_rise_r2 <= (others => '0');
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        rd_data_fall_r2 <= (others => '0');
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      else
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        rd_data_rise_r2 <= rd_data_rise;
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        rd_data_fall_r2 <= rd_data_fall;
160 
      end if;
161 
    end if;
162 
  end process;
163 
 
164 
  process(ctrl_rden_r, state_rise, rd_data_rise, rd_data_rise_r2, pattern_rise1,
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          pattern_fall1, pattern_rise2, pattern_fall2, rst_r)
166 
  begin
167 
    if(rst_r = '1') then
168 
      next_state_rise <= IDLE;
169 
    else
170 
      case state_rise is
171 
        when IDLE =>
172 
          if(ctrl_rden_r = '1') then
173 
            next_state_rise <= FIRST_DATA;
174 
          else
175 
            next_state_rise <= IDLE;
176 
          end if;
177 
 
178 
        when FIRST_DATA =>
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          if((rd_data_rise = pattern_rise1) or (rd_data_rise = pattern_fall1)) then
180 
            next_state_rise <= SECOND_DATA;
181 
          else
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            next_state_rise <= FIRST_DATA;
183 
          end if;
184 
 
185 
        when SECOND_DATA =>
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          if(((rd_data_rise=pattern_rise2) and (rd_data_rise_r2=pattern_rise1)) or
187 
             ((rd_data_rise=pattern_fall2) and (rd_data_rise_r2=pattern_fall1))) then
188 
            next_state_rise <= COMP_OVER;
189 
          else
190 
            next_state_rise <= SECOND_DATA;
191 
          end if;
192 
 
193 
        when COMP_OVER =>
194 
          next_state_rise <= COMP_OVER;
195 
 
196 
        when others =>
197 
          next_state_rise <= IDLE;
198 
      end case;
199 
    end if;
200 
  end process;
201 
 
202 
  process(ctrl_rden_r, state_fall, rd_data_fall, rd_data_fall_r2, pattern_rise1,
203 
          pattern_fall1, pattern_rise2, pattern_fall2, rst_r)
204 
  begin
205 
    if(rst_r = '1') then
206 
      next_state_fall <= IDLE;
207 
    else
208 
      case state_fall is
209 
        when IDLE =>
210 
          if(ctrl_rden_r = '1') then
211 
            next_state_fall <= FIRST_DATA;
212 
          else
213 
            next_state_fall <= IDLE;
214 
          end if;
215 
 
216 
        when FIRST_DATA =>
217 
          if((rd_data_fall = pattern_rise1) or (rd_data_fall = pattern_fall1)) then
218 
            next_state_fall <= SECOND_DATA;
219 
          else
220 
            next_state_fall <= FIRST_DATA;
221 
          end if;
222 
 
223 
        when SECOND_DATA =>
224 
          if(((rd_data_fall=pattern_rise2) and (rd_data_fall_r2=pattern_rise1)) or
225 
             ((rd_data_fall=pattern_fall2) and (rd_data_fall_r2=pattern_fall1))) then
226 
            next_state_fall <= COMP_OVER;
227 
          else
228 
            next_state_fall <= SECOND_DATA;
229 
          end if;
230 
 
231 
        when COMP_OVER =>
232 
          next_state_fall <= COMP_OVER;
233 
 
234 
        when others =>
235 
          next_state_fall <= IDLE;
236 
      end case;
237 
    end if;
238 
  end process;
239 
 
240 
 
241 
end arch;

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