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[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [Memory Design/] [MIG_top_00/] [MIG_user_interface_0/] [MIG_rd_data_0/] [MIG_rd_data_0.vhd] - Blame information for rev 24

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-------------------------------------------------------------------------------
-- Copyright (c) 2005-2007 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor             : Xilinx
-- \   \   \/    Version            : $Name: i+IP+131489 $
--  \   \        Application        : MIG
--  /   /        Filename           : MIG_rd_data_0.vhd
-- /___/   /\    Date Last Modified : $Date: 2007/09/21 15:23:24 $
-- \   \  /  \   Date Created       : Mon May 2 2005
--  \___\/\___\
--
-- Device      : Virtex-4
-- Design Name : DDR SDRAM
-- Description: The delay between the read data with respect to the command
--              issued is calculted in terms of no. of clocks. This data is
--              then stored into the FIFOs and then read back and given as
--              the ouput for comparison.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use work.MIG_parameters_0.all;
library UNISIM;
use UNISIM.vcomponents.all;
 
entity MIG_rd_data_0 is
  port(
    clk                 : in  std_logic;
    reset               : in  std_logic;
    ctrl_rden           : in  std_logic;
    read_data_rise      : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
    read_data_fall      : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
    read_data_fifo_rise : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    read_data_fifo_fall : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    comp_done           : out std_logic;
    read_data_valid     : out std_logic
    );
end MIG_rd_data_0;
 
architecture arch of MIG_rd_data_0 is
 
  component MIG_rd_data_fifo_0
    port(
      clk                  : in  std_logic;
      reset                : in  std_logic;
      read_en_delayed_rise : in  std_logic;
      read_en_delayed_fall : in  std_logic;
      first_rising         : in  std_logic;
      read_data_rise       : in  std_logic_vector(MEMORY_WIDTH - 1 downto 0);
      read_data_fall       : in  std_logic_vector(MEMORY_WIDTH - 1 downto 0);
      fifo_rd_enable       : in  std_logic;
      read_data_fifo_rise  : out std_logic_vector(MEMORY_WIDTH - 1 downto 0);
      read_data_fifo_fall  : out std_logic_vector(MEMORY_WIDTH - 1 downto 0);
      read_data_valid      : out std_logic
      );
  end component;
 
  component MIG_pattern_compare8
    port(
      clk            : in  std_logic;
      rst            : in  std_logic;
      ctrl_rden      : in  std_logic;
      rd_data_rise   : in  std_logic_vector(7 downto 0);
      rd_data_fall   : in  std_logic_vector(7 downto 0);
      comp_done      : out std_logic;
      first_rising   : out std_logic;
      rise_clk_count : out std_logic_vector(2 downto 0);
      fall_clk_count : out std_logic_vector(2 downto 0)
      );
  end component;
 
  component MIG_pattern_compare4
    port(
      clk            : in  std_logic;
      rst            : in  std_logic;
      ctrl_rden      : in  std_logic;
      rd_data_rise   : in  std_logic_vector(3 downto 0);
      rd_data_fall   : in  std_logic_vector(3 downto 0);
      comp_done      : out std_logic;
      first_rising   : out std_logic;
      rise_clk_count : out std_logic_vector(2 downto 0);
      fall_clk_count : out std_logic_vector(2 downto 0)
      );
  end component;
 
  signal rd_en_r1          : std_logic_vector(READENABLE - 1 downto 0);
  signal rd_en_r2          : std_logic_vector(READENABLE - 1 downto 0);
  signal rd_en_r3          : std_logic_vector(READENABLE - 1 downto 0);
  signal rd_en_r4          : std_logic_vector(READENABLE - 1 downto 0);
  signal rd_en_r5          : std_logic_vector(READENABLE - 1 downto 0);
  signal rd_en_r6          : std_logic_vector(READENABLE - 1 downto 0);
  signal comp_done_r       : std_logic;
  signal comp_done_r1      : std_logic;
  signal comp_done_r2      : std_logic;
  signal rd_en_rise        : std_logic_vector(DATA_STROBE_WIDTH - 1 downto 0);
  signal rd_en_fall        : std_logic_vector(DATA_STROBE_WIDTH - 1 downto 0);
  signal ctrl_rden1        : std_logic_vector(READENABLE - 1 downto 0);
  signal first_rising_rden : std_logic_vector(READENABLE - 1 downto 0);
  signal fifo_rd_enable1   : std_logic;
  signal fifo_rd_enable    : std_logic;
  signal rst_r             : std_logic;
 
signal read_data_valid0        : std_logic;
 
 
signal read_data_valid1        : std_logic;
 
 
signal read_data_valid2        : std_logic;
 
 
signal read_data_valid3        : std_logic;
 
  signal comp_done_0 : std_logic;
  signal rise_clk_count0 : std_logic_vector(2 downto 0);
signal fall_clk_count0 : std_logic_vector(2 downto 0);
 
 
begin
 
   ctrl_rden1(0) <= ctrl_rden;
 
  read_data_valid <= read_data_valid0;
 
  pattern_0 : MIG_pattern_compare8
 port map (
            clk             =>   clk,
            rst             =>   reset,
            ctrl_rden       =>   ctrl_rden1(0),
            rd_data_rise    =>   read_data_rise(31  downto  24),
            rd_data_fall    =>   read_data_fall(31  downto  24),
            comp_done       =>   comp_done_0,
            first_rising    =>   first_rising_rden(0),
            rise_clk_count  =>   rise_clk_count0,
            fall_clk_count  =>   fall_clk_count0
        );
 
 
  process(clk)
  begin
    if(clk'event and clk = '1') then
      rst_r <= reset;
    end if;
  end process;
 
  process(clk)
  begin
    if(clk'event and clk = '1') then
      if(rst_r = '1') then
        rd_en_r1 <= (others => '0');
        rd_en_r2 <= (others => '0');
        rd_en_r3 <= (others => '0');
        rd_en_r4 <= (others => '0');
        rd_en_r5 <= (others => '0');
        rd_en_r6 <= (others => '0');
      else
        rd_en_r1 <= ctrl_rden1;
        rd_en_r2 <= rd_en_r1;
        rd_en_r3 <= rd_en_r2;
        rd_en_r4 <= rd_en_r3;
        rd_en_r5 <= rd_en_r4;
        rd_en_r6 <= rd_en_r5;
      end if;
    end if;
  end process;
 
  process(clk)
  begin
    if(clk'event and clk = '1') then
      if(rst_r = '1') then
        comp_done_r  <= '0';
        comp_done_r1 <= '0';
        comp_done_r2 <= '0';
      else
        comp_done_r  <=  comp_done_0 ;
        comp_done_r1 <= comp_done_r;
        comp_done_r2 <= comp_done_r1;
      end if;
    end if;
  end process;
 
  comp_done <= '0' when rst_r = '1' else
                comp_done_0 ;
 
 
process(CLK)
begin
if(CLK'event and CLK = '1') then
 if(rst_r = '1') then
    rd_en_rise(0) <= '0';
 elsif(comp_done_r2 = '1') then
  case rise_clk_count0 is
    when "011" =>
        rd_en_rise(0) <= rd_en_r2(0);
 
    when "100" =>
        rd_en_rise(0) <= rd_en_r3(0);
 
    when "101" =>
        rd_en_rise(0) <= rd_en_r4(0);
 
    when "110" =>
        rd_en_rise(0) <= rd_en_r5(0);
 
    when "111" =>
        rd_en_rise(0) <= rd_en_r6(0);
 
    when others =>
        rd_en_rise(0) <= '0';
  end case;
 end if;
end if;
end process;
 
process(CLK)
begin
if(CLK'event and CLK = '1') then
 if(rst_r = '1') then
    rd_en_fall(0) <= '0';
 elsif(comp_done_r2 = '1') then
  case fall_clk_count0 is
    when "011" =>
        rd_en_fall(0) <= rd_en_r2(0);
 
    when "100" =>
        rd_en_fall(0) <= rd_en_r3(0);
 
    when "101" =>
        rd_en_fall(0) <= rd_en_r4(0);
 
    when "110" =>
        rd_en_fall(0) <= rd_en_r5(0);
 
    when "111" =>
        rd_en_fall(0) <= rd_en_r6(0);
 
    when others =>
        rd_en_fall(0) <= '0';
  end case;
 end if;
end if;
end process;
 
 
process(CLK)
begin
if(CLK'event and CLK = '1') then
 if(rst_r = '1') then
    rd_en_rise(1) <= '0';
 elsif(comp_done_r2 = '1') then
  case rise_clk_count0 is
    when "011" =>
        rd_en_rise(1) <= rd_en_r2(0);
 
    when "100" =>
        rd_en_rise(1) <= rd_en_r3(0);
 
    when "101" =>
        rd_en_rise(1) <= rd_en_r4(0);
 
    when "110" =>
        rd_en_rise(1) <= rd_en_r5(0);
 
    when "111" =>
        rd_en_rise(1) <= rd_en_r6(0);
 
    when others =>
        rd_en_rise(1) <= '0';
  end case;
 end if;
end if;
end process;
 
process(CLK)
begin
if(CLK'event and CLK = '1') then
 if(rst_r = '1') then
    rd_en_fall(1) <= '0';
 elsif(comp_done_r2 = '1') then
  case fall_clk_count0 is
    when "011" =>
        rd_en_fall(1) <= rd_en_r2(0);
 
    when "100" =>
        rd_en_fall(1) <= rd_en_r3(0);
 
    when "101" =>
        rd_en_fall(1) <= rd_en_r4(0);
 
    when "110" =>
        rd_en_fall(1) <= rd_en_r5(0);
 
    when "111" =>
        rd_en_fall(1) <= rd_en_r6(0);
 
    when others =>
        rd_en_fall(1) <= '0';
  end case;
 end if;
end if;
end process;
 
 
process(CLK)
begin
if(CLK'event and CLK = '1') then
 if(rst_r = '1') then
    rd_en_rise(2) <= '0';
 elsif(comp_done_r2 = '1') then
  case rise_clk_count0 is
    when "011" =>
        rd_en_rise(2) <= rd_en_r2(0);
 
    when "100" =>
        rd_en_rise(2) <= rd_en_r3(0);
 
    when "101" =>
        rd_en_rise(2) <= rd_en_r4(0);
 
    when "110" =>
        rd_en_rise(2) <= rd_en_r5(0);
 
    when "111" =>
        rd_en_rise(2) <= rd_en_r6(0);
 
    when others =>
        rd_en_rise(2) <= '0';
  end case;
 end if;
end if;
end process;
 
process(CLK)
begin
if(CLK'event and CLK = '1') then
 if(rst_r = '1') then
    rd_en_fall(2) <= '0';
 elsif(comp_done_r2 = '1') then
  case fall_clk_count0 is
    when "011" =>
        rd_en_fall(2) <= rd_en_r2(0);
 
    when "100" =>
        rd_en_fall(2) <= rd_en_r3(0);
 
    when "101" =>
        rd_en_fall(2) <= rd_en_r4(0);
 
    when "110" =>
        rd_en_fall(2) <= rd_en_r5(0);
 
    when "111" =>
        rd_en_fall(2) <= rd_en_r6(0);
 
    when others =>
        rd_en_fall(2) <= '0';
  end case;
 end if;
end if;
end process;
 
 
process(CLK)
begin
if(CLK'event and CLK = '1') then
 if(rst_r = '1') then
    rd_en_rise(3) <= '0';
 elsif(comp_done_r2 = '1') then
  case rise_clk_count0 is
    when "011" =>
        rd_en_rise(3) <= rd_en_r2(0);
 
    when "100" =>
        rd_en_rise(3) <= rd_en_r3(0);
 
    when "101" =>
        rd_en_rise(3) <= rd_en_r4(0);
 
    when "110" =>
        rd_en_rise(3) <= rd_en_r5(0);
 
    when "111" =>
        rd_en_rise(3) <= rd_en_r6(0);
 
    when others =>
        rd_en_rise(3) <= '0';
  end case;
 end if;
end if;
end process;
 
process(CLK)
begin
if(CLK'event and CLK = '1') then
 if(rst_r = '1') then
    rd_en_fall(3) <= '0';
 elsif(comp_done_r2 = '1') then
  case fall_clk_count0 is
    when "011" =>
        rd_en_fall(3) <= rd_en_r2(0);
 
    when "100" =>
        rd_en_fall(3) <= rd_en_r3(0);
 
    when "101" =>
        rd_en_fall(3) <= rd_en_r4(0);
 
    when "110" =>
        rd_en_fall(3) <= rd_en_r5(0);
 
    when "111" =>
        rd_en_fall(3) <= rd_en_r6(0);
 
    when others =>
        rd_en_fall(3) <= '0';
  end case;
 end if;
end if;
end process;
 
 
  process(clk)
  begin
    if(clk'event and clk = '1') then
      if(rst_r = '1') then
        fifo_rd_enable1 <= '0';
        fifo_rd_enable  <= '0';
      else
        fifo_rd_enable1 <= rd_en_rise(0);
        fifo_rd_enable  <= fifo_rd_enable1;
      end if;
    end if;
  end process;
 
 
  rd_data_fifo0: MIG_rd_data_fifo_0
    port map (
          clk                   => clk,
          reset                 => reset,
          read_en_delayed_rise  => rd_en_rise(0),
          read_en_delayed_fall  => rd_en_fall(0),
          first_rising          => first_rising_rden(0),
          read_data_rise        => read_data_rise(7 downto 0),
          read_data_fall        => read_data_fall(7 downto 0),
          fifo_rd_enable        => fifo_rd_enable,
          read_data_fifo_rise   => read_data_fifo_rise(7 downto 0),
          read_data_fifo_fall   => read_data_fifo_fall(7 downto 0),
          read_data_valid       => read_data_valid0
        );
 
 
  rd_data_fifo1: MIG_rd_data_fifo_0
    port map (
          clk                   => clk,
          reset                 => reset,
          read_en_delayed_rise  => rd_en_rise(1),
          read_en_delayed_fall  => rd_en_fall(1),
          first_rising          => first_rising_rden(0),
          read_data_rise        => read_data_rise(15 downto 8),
          read_data_fall        => read_data_fall(15 downto 8),
          fifo_rd_enable        => fifo_rd_enable,
          read_data_fifo_rise   => read_data_fifo_rise(15 downto 8),
          read_data_fifo_fall   => read_data_fifo_fall(15 downto 8),
          read_data_valid       => read_data_valid1
        );
 
 
  rd_data_fifo2: MIG_rd_data_fifo_0
    port map (
          clk                   => clk,
          reset                 => reset,
          read_en_delayed_rise  => rd_en_rise(2),
          read_en_delayed_fall  => rd_en_fall(2),
          first_rising          => first_rising_rden(0),
          read_data_rise        => read_data_rise(23 downto 16),
          read_data_fall        => read_data_fall(23 downto 16),
          fifo_rd_enable        => fifo_rd_enable,
          read_data_fifo_rise   => read_data_fifo_rise(23 downto 16),
          read_data_fifo_fall   => read_data_fifo_fall(23 downto 16),
          read_data_valid       => read_data_valid2
        );
 
 
  rd_data_fifo3: MIG_rd_data_fifo_0
    port map (
          clk                   => clk,
          reset                 => reset,
          read_en_delayed_rise  => rd_en_rise(3),
          read_en_delayed_fall  => rd_en_fall(3),
          first_rising          => first_rising_rden(0),
          read_data_rise        => read_data_rise(31 downto 24),
          read_data_fall        => read_data_fall(31 downto 24),
          fifo_rd_enable        => fifo_rd_enable,
          read_data_fifo_rise   => read_data_fifo_rise(31 downto 24),
          read_data_fifo_fall   => read_data_fifo_fall(31 downto 24),
          read_data_valid       => read_data_valid3
        );
 
 
end arch;

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Subversion Repositories the_wizardry_project

[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [Memory Design/] [MIG_top_00/] [MIG_user_interface_0/] [MIG_rd_data_0/] [MIG_rd_data_0.vhd] - Blame information for rev 24

Line No.	Rev	Author	Line
1	24	mcwaccent	`-------------------------------------------------------------------------------`
2			`-- Copyright (c) 2005-2007 Xilinx, Inc.`
3			`-- This design is confidential and proprietary of Xilinx, All Rights Reserved.`
4			`-------------------------------------------------------------------------------`
5			`-- ____ ____`
6			`-- / /\/ /`
7			`-- /___/ \ / Vendor : Xilinx`
8			`-- \ \ \/ Version : $Name: i+IP+131489 $`
9			`-- \ \ Application : MIG`
10			`-- / / Filename : MIG_rd_data_0.vhd`
11			`-- /___/ /\ Date Last Modified : $Date: 2007/09/21 15:23:24 $`
12			`-- \ \ / \ Date Created : Mon May 2 2005`
13			`-- \___\/\___\`
14			`--`
15			`-- Device : Virtex-4`
16			`-- Design Name : DDR SDRAM`
17			`-- Description: The delay between the read data with respect to the command`
18			`-- issued is calculted in terms of no. of clocks. This data is`
19			`-- then stored into the FIFOs and then read back and given as`
20			`-- the ouput for comparison.`
21			`-------------------------------------------------------------------------------`
22
23			`library ieee;`
24			`use ieee.std_logic_1164.all;`
25			`use work.MIG_parameters_0.all;`
26			`library UNISIM;`
27			`use UNISIM.vcomponents.all;`
28
29			`entity MIG_rd_data_0 is`
30			`port(`
31			`clk : in std_logic;`
32			`reset : in std_logic;`
33			`ctrl_rden : in std_logic;`
34			`read_data_rise : in std_logic_vector(DATA_WIDTH - 1 downto 0);`
35			`read_data_fall : in std_logic_vector(DATA_WIDTH - 1 downto 0);`
36			`read_data_fifo_rise : out std_logic_vector(DATA_WIDTH - 1 downto 0);`
37			`read_data_fifo_fall : out std_logic_vector(DATA_WIDTH - 1 downto 0);`
38			`comp_done : out std_logic;`
39			`read_data_valid : out std_logic`
40			`);`
41			`end MIG_rd_data_0;`
42
43			`architecture arch of MIG_rd_data_0 is`
44
45			`component MIG_rd_data_fifo_0`
46			`port(`
47			`clk : in std_logic;`
48			`reset : in std_logic;`
49			`read_en_delayed_rise : in std_logic;`
50			`read_en_delayed_fall : in std_logic;`
51			`first_rising : in std_logic;`
52			`read_data_rise : in std_logic_vector(MEMORY_WIDTH - 1 downto 0);`
53			`read_data_fall : in std_logic_vector(MEMORY_WIDTH - 1 downto 0);`
54			`fifo_rd_enable : in std_logic;`
55			`read_data_fifo_rise : out std_logic_vector(MEMORY_WIDTH - 1 downto 0);`
56			`read_data_fifo_fall : out std_logic_vector(MEMORY_WIDTH - 1 downto 0);`
57			`read_data_valid : out std_logic`
58			`);`
59			`end component;`
60
61			`component MIG_pattern_compare8`
62			`port(`
63			`clk : in std_logic;`
64			`rst : in std_logic;`
65			`ctrl_rden : in std_logic;`
66			`rd_data_rise : in std_logic_vector(7 downto 0);`
67			`rd_data_fall : in std_logic_vector(7 downto 0);`
68			`comp_done : out std_logic;`
69			`first_rising : out std_logic;`
70			`rise_clk_count : out std_logic_vector(2 downto 0);`
71			`fall_clk_count : out std_logic_vector(2 downto 0)`
72			`);`
73			`end component;`
74
75			`component MIG_pattern_compare4`
76			`port(`
77			`clk : in std_logic;`
78			`rst : in std_logic;`
79			`ctrl_rden : in std_logic;`
80			`rd_data_rise : in std_logic_vector(3 downto 0);`
81			`rd_data_fall : in std_logic_vector(3 downto 0);`
82			`comp_done : out std_logic;`
83			`first_rising : out std_logic;`
84			`rise_clk_count : out std_logic_vector(2 downto 0);`
85			`fall_clk_count : out std_logic_vector(2 downto 0)`
86			`);`
87			`end component;`
88
89			`signal rd_en_r1 : std_logic_vector(READENABLE - 1 downto 0);`
90			`signal rd_en_r2 : std_logic_vector(READENABLE - 1 downto 0);`
91			`signal rd_en_r3 : std_logic_vector(READENABLE - 1 downto 0);`
92			`signal rd_en_r4 : std_logic_vector(READENABLE - 1 downto 0);`
93			`signal rd_en_r5 : std_logic_vector(READENABLE - 1 downto 0);`
94			`signal rd_en_r6 : std_logic_vector(READENABLE - 1 downto 0);`
95			`signal comp_done_r : std_logic;`
96			`signal comp_done_r1 : std_logic;`
97			`signal comp_done_r2 : std_logic;`
98			`signal rd_en_rise : std_logic_vector(DATA_STROBE_WIDTH - 1 downto 0);`
99			`signal rd_en_fall : std_logic_vector(DATA_STROBE_WIDTH - 1 downto 0);`
100			`signal ctrl_rden1 : std_logic_vector(READENABLE - 1 downto 0);`
101			`signal first_rising_rden : std_logic_vector(READENABLE - 1 downto 0);`
102			`signal fifo_rd_enable1 : std_logic;`
103			`signal fifo_rd_enable : std_logic;`
104			`signal rst_r : std_logic;`
105
106			`signal read_data_valid0 : std_logic;`
107
108
109			`signal read_data_valid1 : std_logic;`
110
111
112			`signal read_data_valid2 : std_logic;`
113
114
115			`signal read_data_valid3 : std_logic;`
116
117			`signal comp_done_0 : std_logic;`
118			`signal rise_clk_count0 : std_logic_vector(2 downto 0);`
119			`signal fall_clk_count0 : std_logic_vector(2 downto 0);`
120
121
122			`begin`
123
124			`ctrl_rden1(0) <= ctrl_rden;`
125
126			`read_data_valid <= read_data_valid0;`
127
128			`pattern_0 : MIG_pattern_compare8`
129			`port map (`
130			`clk => clk,`
131			`rst => reset,`
132			`ctrl_rden => ctrl_rden1(0),`
133			`rd_data_rise => read_data_rise(31 downto 24),`
134			`rd_data_fall => read_data_fall(31 downto 24),`
135			`comp_done => comp_done_0,`
136			`first_rising => first_rising_rden(0),`
137			`rise_clk_count => rise_clk_count0,`
138			`fall_clk_count => fall_clk_count0`
139			`);`
140
141
142			`process(clk)`
143			`begin`
144			`if(clk'event and clk = '1') then`
145			`rst_r <= reset;`
146			`end if;`
147			`end process;`
148
149			`process(clk)`
150			`begin`
151			`if(clk'event and clk = '1') then`
152			`if(rst_r = '1') then`
153			`rd_en_r1 <= (others => '0');`
154			`rd_en_r2 <= (others => '0');`
155			`rd_en_r3 <= (others => '0');`
156			`rd_en_r4 <= (others => '0');`
157			`rd_en_r5 <= (others => '0');`
158			`rd_en_r6 <= (others => '0');`
159			`else`
160			`rd_en_r1 <= ctrl_rden1;`
161			`rd_en_r2 <= rd_en_r1;`
162			`rd_en_r3 <= rd_en_r2;`
163			`rd_en_r4 <= rd_en_r3;`
164			`rd_en_r5 <= rd_en_r4;`
165			`rd_en_r6 <= rd_en_r5;`
166			`end if;`
167			`end if;`
168			`end process;`
169
170			`process(clk)`
171			`begin`
172			`if(clk'event and clk = '1') then`
173			`if(rst_r = '1') then`
174			`comp_done_r <= '0';`
175			`comp_done_r1 <= '0';`
176			`comp_done_r2 <= '0';`
177			`else`
178			`comp_done_r <= comp_done_0 ;`
179			`comp_done_r1 <= comp_done_r;`
180			`comp_done_r2 <= comp_done_r1;`
181			`end if;`
182			`end if;`
183			`end process;`
184
185			`comp_done <= '0' when rst_r = '1' else`
186			`comp_done_0 ;`
187
188
189			`process(CLK)`
190			`begin`
191			`if(CLK'event and CLK = '1') then`
192			`if(rst_r = '1') then`
193			`rd_en_rise(0) <= '0';`
194			`elsif(comp_done_r2 = '1') then`
195			`case rise_clk_count0 is`
196			`when "011" =>`
197			`rd_en_rise(0) <= rd_en_r2(0);`
198
199			`when "100" =>`
200			`rd_en_rise(0) <= rd_en_r3(0);`
201
202			`when "101" =>`
203			`rd_en_rise(0) <= rd_en_r4(0);`
204
205			`when "110" =>`
206			`rd_en_rise(0) <= rd_en_r5(0);`
207
208			`when "111" =>`
209			`rd_en_rise(0) <= rd_en_r6(0);`
210
211			`when others =>`
212			`rd_en_rise(0) <= '0';`
213			`end case;`
214			`end if;`
215			`end if;`
216			`end process;`
217
218			`process(CLK)`
219			`begin`
220			`if(CLK'event and CLK = '1') then`
221			`if(rst_r = '1') then`
222			`rd_en_fall(0) <= '0';`
223			`elsif(comp_done_r2 = '1') then`
224			`case fall_clk_count0 is`
225			`when "011" =>`
226			`rd_en_fall(0) <= rd_en_r2(0);`
227
228			`when "100" =>`
229			`rd_en_fall(0) <= rd_en_r3(0);`
230
231			`when "101" =>`
232			`rd_en_fall(0) <= rd_en_r4(0);`
233
234			`when "110" =>`
235			`rd_en_fall(0) <= rd_en_r5(0);`
236
237			`when "111" =>`
238			`rd_en_fall(0) <= rd_en_r6(0);`
239
240			`when others =>`
241			`rd_en_fall(0) <= '0';`
242			`end case;`
243			`end if;`
244			`end if;`
245			`end process;`
246
247
248			`process(CLK)`
249			`begin`
250			`if(CLK'event and CLK = '1') then`
251			`if(rst_r = '1') then`
252			`rd_en_rise(1) <= '0';`
253			`elsif(comp_done_r2 = '1') then`
254			`case rise_clk_count0 is`
255			`when "011" =>`
256			`rd_en_rise(1) <= rd_en_r2(0);`
257
258			`when "100" =>`
259			`rd_en_rise(1) <= rd_en_r3(0);`
260
261			`when "101" =>`
262			`rd_en_rise(1) <= rd_en_r4(0);`
263
264			`when "110" =>`
265			`rd_en_rise(1) <= rd_en_r5(0);`
266
267			`when "111" =>`
268			`rd_en_rise(1) <= rd_en_r6(0);`
269
270			`when others =>`
271			`rd_en_rise(1) <= '0';`
272			`end case;`
273			`end if;`
274			`end if;`
275			`end process;`
276
277			`process(CLK)`
278			`begin`
279			`if(CLK'event and CLK = '1') then`
280			`if(rst_r = '1') then`
281			`rd_en_fall(1) <= '0';`
282			`elsif(comp_done_r2 = '1') then`
283			`case fall_clk_count0 is`
284			`when "011" =>`
285			`rd_en_fall(1) <= rd_en_r2(0);`
286
287			`when "100" =>`
288			`rd_en_fall(1) <= rd_en_r3(0);`
289
290			`when "101" =>`
291			`rd_en_fall(1) <= rd_en_r4(0);`
292
293			`when "110" =>`
294			`rd_en_fall(1) <= rd_en_r5(0);`
295
296			`when "111" =>`
297			`rd_en_fall(1) <= rd_en_r6(0);`
298
299			`when others =>`
300			`rd_en_fall(1) <= '0';`
301			`end case;`
302			`end if;`
303			`end if;`
304			`end process;`
305
306
307			`process(CLK)`
308			`begin`
309			`if(CLK'event and CLK = '1') then`
310			`if(rst_r = '1') then`
311			`rd_en_rise(2) <= '0';`
312			`elsif(comp_done_r2 = '1') then`
313			`case rise_clk_count0 is`
314			`when "011" =>`
315			`rd_en_rise(2) <= rd_en_r2(0);`
316
317			`when "100" =>`
318			`rd_en_rise(2) <= rd_en_r3(0);`
319
320			`when "101" =>`
321			`rd_en_rise(2) <= rd_en_r4(0);`
322
323			`when "110" =>`
324			`rd_en_rise(2) <= rd_en_r5(0);`
325
326			`when "111" =>`
327			`rd_en_rise(2) <= rd_en_r6(0);`
328
329			`when others =>`
330			`rd_en_rise(2) <= '0';`
331			`end case;`
332			`end if;`
333			`end if;`
334			`end process;`
335
336			`process(CLK)`
337			`begin`
338			`if(CLK'event and CLK = '1') then`
339			`if(rst_r = '1') then`
340			`rd_en_fall(2) <= '0';`
341			`elsif(comp_done_r2 = '1') then`
342			`case fall_clk_count0 is`
343			`when "011" =>`
344			`rd_en_fall(2) <= rd_en_r2(0);`
345
346			`when "100" =>`
347			`rd_en_fall(2) <= rd_en_r3(0);`
348
349			`when "101" =>`
350			`rd_en_fall(2) <= rd_en_r4(0);`
351
352			`when "110" =>`
353			`rd_en_fall(2) <= rd_en_r5(0);`
354
355			`when "111" =>`
356			`rd_en_fall(2) <= rd_en_r6(0);`
357
358			`when others =>`
359			`rd_en_fall(2) <= '0';`
360			`end case;`
361			`end if;`
362			`end if;`
363			`end process;`
364
365
366			`process(CLK)`
367			`begin`
368			`if(CLK'event and CLK = '1') then`
369			`if(rst_r = '1') then`
370			`rd_en_rise(3) <= '0';`
371			`elsif(comp_done_r2 = '1') then`
372			`case rise_clk_count0 is`
373			`when "011" =>`
374			`rd_en_rise(3) <= rd_en_r2(0);`
375
376			`when "100" =>`
377			`rd_en_rise(3) <= rd_en_r3(0);`
378
379			`when "101" =>`
380			`rd_en_rise(3) <= rd_en_r4(0);`
381
382			`when "110" =>`
383			`rd_en_rise(3) <= rd_en_r5(0);`
384
385			`when "111" =>`
386			`rd_en_rise(3) <= rd_en_r6(0);`
387
388			`when others =>`
389			`rd_en_rise(3) <= '0';`
390			`end case;`
391			`end if;`
392			`end if;`
393			`end process;`
394
395			`process(CLK)`
396			`begin`
397			`if(CLK'event and CLK = '1') then`
398			`if(rst_r = '1') then`
399			`rd_en_fall(3) <= '0';`
400			`elsif(comp_done_r2 = '1') then`
401			`case fall_clk_count0 is`
402			`when "011" =>`
403			`rd_en_fall(3) <= rd_en_r2(0);`
404
405			`when "100" =>`
406			`rd_en_fall(3) <= rd_en_r3(0);`
407
408			`when "101" =>`
409			`rd_en_fall(3) <= rd_en_r4(0);`
410
411			`when "110" =>`
412			`rd_en_fall(3) <= rd_en_r5(0);`
413
414			`when "111" =>`
415			`rd_en_fall(3) <= rd_en_r6(0);`
416
417			`when others =>`
418			`rd_en_fall(3) <= '0';`
419			`end case;`
420			`end if;`
421			`end if;`
422			`end process;`
423
424
425			`process(clk)`
426			`begin`
427			`if(clk'event and clk = '1') then`
428			`if(rst_r = '1') then`
429			`fifo_rd_enable1 <= '0';`
430			`fifo_rd_enable <= '0';`
431			`else`
432			`fifo_rd_enable1 <= rd_en_rise(0);`
433			`fifo_rd_enable <= fifo_rd_enable1;`
434			`end if;`
435			`end if;`
436			`end process;`
437
438
439			`rd_data_fifo0: MIG_rd_data_fifo_0`
440			`port map (`
441			`clk => clk,`
442			`reset => reset,`
443			`read_en_delayed_rise => rd_en_rise(0),`
444			`read_en_delayed_fall => rd_en_fall(0),`
445			`first_rising => first_rising_rden(0),`
446			`read_data_rise => read_data_rise(7 downto 0),`
447			`read_data_fall => read_data_fall(7 downto 0),`
448			`fifo_rd_enable => fifo_rd_enable,`
449			`read_data_fifo_rise => read_data_fifo_rise(7 downto 0),`
450			`read_data_fifo_fall => read_data_fifo_fall(7 downto 0),`
451			`read_data_valid => read_data_valid0`
452			`);`
453
454
455			`rd_data_fifo1: MIG_rd_data_fifo_0`
456			`port map (`
457			`clk => clk,`
458			`reset => reset,`
459			`read_en_delayed_rise => rd_en_rise(1),`
460			`read_en_delayed_fall => rd_en_fall(1),`
461			`first_rising => first_rising_rden(0),`
462			`read_data_rise => read_data_rise(15 downto 8),`
463			`read_data_fall => read_data_fall(15 downto 8),`
464			`fifo_rd_enable => fifo_rd_enable,`
465			`read_data_fifo_rise => read_data_fifo_rise(15 downto 8),`
466			`read_data_fifo_fall => read_data_fifo_fall(15 downto 8),`
467			`read_data_valid => read_data_valid1`
468			`);`
469
470
471			`rd_data_fifo2: MIG_rd_data_fifo_0`
472			`port map (`
473			`clk => clk,`
474			`reset => reset,`
475			`read_en_delayed_rise => rd_en_rise(2),`
476			`read_en_delayed_fall => rd_en_fall(2),`
477			`first_rising => first_rising_rden(0),`
478			`read_data_rise => read_data_rise(23 downto 16),`
479			`read_data_fall => read_data_fall(23 downto 16),`
480			`fifo_rd_enable => fifo_rd_enable,`
481			`read_data_fifo_rise => read_data_fifo_rise(23 downto 16),`
482			`read_data_fifo_fall => read_data_fifo_fall(23 downto 16),`
483			`read_data_valid => read_data_valid2`
484			`);`
485
486
487			`rd_data_fifo3: MIG_rd_data_fifo_0`
488			`port map (`
489			`clk => clk,`
490			`reset => reset,`
491			`read_en_delayed_rise => rd_en_rise(3),`
492			`read_en_delayed_fall => rd_en_fall(3),`
493			`first_rising => first_rising_rden(0),`
494			`read_data_rise => read_data_rise(31 downto 24),`
495			`read_data_fall => read_data_fall(31 downto 24),`
496			`fifo_rd_enable => fifo_rd_enable,`
497			`read_data_fifo_rise => read_data_fifo_rise(31 downto 24),`
498			`read_data_fifo_fall => read_data_fifo_fall(31 downto 24),`
499			`read_data_valid => read_data_valid3`
500			`);`
501
502
503			`end arch;`