URL https://opencores.org/ocsvn/the_wizardry_project/the_wizardry_project/trunk

Subversion Repositories the_wizardry_project

[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [TOP_LEVEL_TESTBENCH.vhd] - Blame information for rev 23

Details | Compare with Previous | View Log


----------------------------------------------------------------------------------
--
--  This file is a part of Technica Corporation Wizardry Project
--
--  Copyright (C) 2004-2009, Technica Corporation  
--
--  This program is free software: you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation, either version 3 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Module Name: Top_Level_TESTBENCH - Structural 
-- Project Name: Wizardry
-- Target Devices: Virtex 4 ML401
-- Description: Top-level structural description for Wizardry.
-- Revision: 1.0
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
entity TOP_LEVEL_TESTBENCH is
port(
                FPGA_reset                                                                       : in std_logic;
                FPGA_clk_100_top                                                                 : in std_logic;
                rx                                : in  std_logic;
                tx                                : out  std_logic;
--              leds : out std_logic_vector(8 downto 0);
--              FIFO_empty                                                                              : out std_logic;
--         read_enable                                                                  : out std_logic;
--         write_enable                                                                 : out std_logic;
                cntrl0_ddr_dq                        : inout  std_logic_vector(31 downto 0);
                cntrl0_ddr_dqs                       : inout  std_logic_vector(3 downto 0);
                cntrl0_ddr_a                         : out  std_logic_vector(12 downto 0);
                cntrl0_ddr_ba                        : out  std_logic_vector(1 downto 0);
                cntrl0_ddr_cke                       : out std_logic;
                cntrl0_ddr_cs_n                      : out std_logic;
                cntrl0_ddr_ras_n                     : out std_logic;
                cntrl0_ddr_cas_n                     : out std_logic;
                cntrl0_ddr_we_n                      : out std_logic;
                cntrl0_ddr_dm                        : out  std_logic_vector(3 downto 0);
                cntrl0_ddr_ck                        : out  std_logic_vector(1 downto 0);
                cntrl0_ddr_ck_n                      : out  std_logic_vector(1 downto 0);
 
                         -- eRCP and EmPAC Signals to/from top level
         phy_clock : in std_logic;
         phy_reset : out std_logic;
         phy_data_in : in  STD_LOGIC_VECTOR (3 downto 0);
                phy_data_valid_in : in  STD_LOGIC;
--              WIZ_rx_sdata : in  STD_LOGIC;
--              WIZ_tx_sdata : out  STD_LOGIC;
 
        --  Debug Signals to top level
--      rdcount : out std_logic_vector(11 downto 0);
--                         wrcount0 : out std_logic_vector(6 downto 0);
--                              empac_empty_debug: out std_logic;
--                              empac_full_debug : out std_logic;
 
        ---==========================================================--
----===========Virtex-4 SRAM Port============================--
        wd : out std_logic;
        sram_clk : out std_logic;
        sram_feedback_clk : out std_logic;
 
        sram_addr : out std_logic_vector(22 downto 0);
 
        sram_we_n : out std_logic;
        sram_oe_n : out std_logic;
 
        sram_data : inout std_logic_vector(31 downto 0);
 
        sram_bw0: out std_logic;
        sram_bw1 : out std_logic;
 
        sram_bw2 : out std_Logic;
        sram_bw3 : out std_logic;
 
        sram_adv_ld_n : out std_logic;
        sram_mode : out std_logic;
        sram_cen : out std_logic;
        sram_cen_test : out std_logic;
        sram_zz : out std_logic
 
---=========================================================---
---=========================================================---
 
                );
end TOP_LEVEL_TESTBENCH;
 
architecture Behavioral of TOP_LEVEL_TESTBENCH is
 
signal rdcount : std_logic_Vector(11 downto 0);
signal WIZ_rx_sdata : sTD_LOGIC;
signal WIZ_tx_sdata : STD_LOGIC;
--signal leds : std_logic_vector(8 downto 0);
signal FIFO_empty       : std_logic;
signal read_enable      : std_logic;
signal write_enable     : std_logic;
 
Component MIG is
  port(
    cntrl0_ddr_dq                        : inout  std_logic_vector(31 downto 0);
    cntrl0_ddr_a                         : out  std_logic_vector(12 downto 0);
    cntrl0_ddr_ba                        : out  std_logic_vector(1 downto 0);
    cntrl0_ddr_cke                       : out std_logic;
    cntrl0_ddr_cs_n                      : out std_logic;
    cntrl0_ddr_ras_n                     : out std_logic;
    cntrl0_ddr_cas_n                     : out std_logic;
    cntrl0_ddr_we_n                      : out std_logic;
    cntrl0_ddr_dm                        : out  std_logic_vector(3 downto 0);
    sys_clk_p                            : in std_logic;
    sys_clk_n                            : in std_logic;
    clk200_p                             : in std_logic;
    clk200_n                             : in std_logic;
         clk_100_top                            : in std_logic;
         clk_200_top                            : in std_logic;
    init_done                            : out std_logic;
    sys_reset_in_n                       : in std_logic;
    cntrl0_clk_tb                        : out std_logic;
    cntrl0_reset_tb                      : out std_logic;
    cntrl0_wdf_almost_full               : out std_logic;
    cntrl0_af_almost_full                : out std_logic;
    cntrl0_read_data_valid               : out std_logic;
    cntrl0_app_wdf_wren                  : in std_logic;
    cntrl0_app_af_wren                   : in std_logic;
    cntrl0_burst_length_div2             : out  std_logic_vector(2 downto 0);
    cntrl0_app_af_addr                   : in  std_logic_vector(35 downto 0);
    cntrl0_app_wdf_data                  : in  std_logic_vector(63 downto 0);
    cntrl0_read_data_fifo_out            : out  std_logic_vector(63 downto 0);
    cntrl0_app_mask_data                 : in  std_logic_vector(7 downto 0);
    cntrl0_ddr_dqs                       : inout  std_logic_vector(3 downto 0);
    cntrl0_ddr_ck                        : out  std_logic_vector(1 downto 0);
    cntrl0_ddr_ck_n                      : out  std_logic_vector(1 downto 0)
         );
end Component;
 
--signal    cntrl0_ddr_dq                        :   std_logic_vector(31 downto 0);
--signal    cntrl0_ddr_a                         :   std_logic_vector(12 downto 0);
--signal    cntrl0_ddr_ba                        :   std_logic_vector(1 downto 0);
--signal    cntrl0_ddr_cke                       :  std_logic;
--signal    cntrl0_ddr_cs_n                      :  std_logic;
--signal    cntrl0_ddr_ras_n                     :  std_logic;
--signal    cntrl0_ddr_cas_n                     :  std_logic;
--signal    cntrl0_ddr_we_n                      :  std_logic;
--signal    cntrl0_ddr_dm                        :   std_logic_vector(3 downto 0);
signal    sys_clk_p                            : std_logic;
signal    sys_clk_n                            :  std_logic;
signal    clk200_p                             :  std_logic;
signal    clk200_n                             :  std_logic;
signal    init_done                            :  std_logic := '0';
signal    sys_reset_in_n                       :  std_logic;
signal    cntrl0_clk_tb                        :  std_logic;
signal    cntrl0_reset_tb                      :  std_logic;
signal    cntrl0_wdf_almost_full               :  std_logic;
signal    cntrl0_af_almost_full                :  std_logic;
signal    cntrl0_read_data_valid               :  std_logic;
signal    cntrl0_app_wdf_wren                  : std_logic;
signal    cntrl0_app_af_wren                   :  std_logic;
signal    cntrl0_burst_length_div2             :   std_logic_vector(2 downto 0);
signal    cntrl0_app_af_addr                   :   std_logic_vector(35 downto 0);
signal    cntrl0_app_wdf_data                  :   std_logic_vector(63 downto 0);
signal    cntrl0_read_data_fifo_out            :   std_logic_vector(63 downto 0);
signal    cntrl0_app_mask_data                 :   std_logic_vector(7 downto 0);
--signal    cntrl0_ddr_dqs                       :   std_logic_vector(3 downto 0);
--signal    cntrl0_ddr_ck                        :   std_logic_vector(1 downto 0);
--signal    cntrl0_ddr_ck_n                      :   std_logic_vector(1 downto 0);
signal   bkend_wraddr_en_s                                                : std_logic;
signal clk_100_top : std_logic;
signal clk_200_top : std_logic;
signal system_clock_100, system_clock_200 : std_logic;
signal clk_100_top_fb : std_logic;
signal dcm_lock : std_logic;
 
signal          DCM_reset : std_logic;
signal          DCM_reset_0 : std_logic;
signal          DCM_reset_1 : std_logic;
signal          DCM_reset_2 : std_logic;
signal          DCM_reset_3 : std_logic;
 
signal          system_reset : std_logic;
signal          system_reset_0 : std_logic;
signal          system_reset_1 : std_logic;
signal          system_reset_2 : std_logic;
signal          system_reset_3 : std_logic;
signal          phy_reset_dummy : std_logic;
signal wrcount : std_logic_vector(11 downto 0);
 
component MIG_addr_gen is
  port (
    clk0            : in  std_logic;
    rst             : in  std_logic;
    bkend_wraddr_en : in  std_logic;
         rx                               : in  std_logic;
         tx                               : out  std_logic;
--       leds : out std_logic_vector(8 downto 0);
    cntrl0_app_af_addr     : out std_logic_vector(35 downto 0);
    cntrl0_app_af_wren     : out std_logic;
         cntrl0_app_mask_data                 : out  std_logic_vector(7 downto 0);
         cntrl0_app_wdf_wren                  : out std_logic;
         cntrl0_app_wdf_data                  : out  std_logic_vector(63 downto 0);
         cntrl0_read_data_valid               : in std_logic;
         cntrl0_read_data_fifo_out            : in  std_logic_vector(63 downto 0);
         init_done                                                                        : in std_logic;
         FIFO_empty                                                                             : out std_logic;
         read_enable                                                                    : out std_logic;
         write_enable                                                                   : out std_logic;
 
         -- eRCP and EmPAC Signals to/from top level
         phy_clock : in std_logic;
         phy_reset : out std_logic;
         phy_data_in : in  STD_LOGIC_VECTOR (3 downto 0);
                phy_data_valid_in : in  STD_LOGIC;
                WIZ_rx_sdata : in  STD_LOGIC;
                WIZ_tx_sdata : out  STD_LOGIC;
 
        --  Debug Signals to top level
--      rdcount : out std_logic_vector(11 downto 0);
--                         wrcount : out std_logic_vector(11 downto 0);
--                              empac_empty_debug: out std_logic;
--                              empac_full_debug : out std_logic;
 
        ---==========================================================--
----===========Virtex-4 SRAM Port============================--
        wd : out std_logic;
        sram_clk : out std_logic;
        sram_feedback_clk : out std_logic;
 
        sram_addr : out std_logic_vector(22 downto 0);
 
        sram_we_n : out std_logic;
        sram_oe_n : out std_logic;
 
        sram_data : inout std_logic_vector(31 downto 0);
 
        sram_bw0: out std_logic;
        sram_bw1 : out std_logic;
 
        sram_bw2 : out std_Logic;
        sram_bw3 : out std_logic;
 
        sram_adv_ld_n : out std_logic;
        sram_mode : out std_logic;
        sram_cen : out std_logic;
        sram_cen_test : out std_logic;
        sram_zz : out std_logic
 
 
    );
end component;
 
Component MT46V16M16 IS
    GENERIC (                                   -- Timing for -75Z CL2
        tCK       : TIME    :=  7.500 ns;
        tCH       : TIME    :=  3.375 ns;       -- 0.45*tCK
        tCL       : TIME    :=  3.375 ns;       -- 0.45*tCK
        tDH       : TIME    :=  0.500 ns;
        tDS       : TIME    :=  0.500 ns;
        tIH       : TIME    :=  0.900 ns;
        tIS       : TIME    :=  0.900 ns;
        tMRD      : TIME    := 15.000 ns;
        tRAS      : TIME    := 40.000 ns;
        tRAP      : TIME    := 20.000 ns;
        tRC       : TIME    := 65.000 ns;
        tRFC      : TIME    := 75.000 ns;
        tRCD      : TIME    := 20.000 ns;
        tRP       : TIME    := 20.000 ns;
        tRRD      : TIME    := 15.000 ns;
        tWR       : TIME    := 15.000 ns;
        addr_bits : INTEGER := 13;
        data_bits : INTEGER := 16;
        cols_bits : INTEGER :=  9
    );
    PORT (
        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
        Dqs   : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
        Ba    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0);
        Clk   : IN    STD_LOGIC;
        Clk_n : IN    STD_LOGIC;
        Cke   : IN    STD_LOGIC;
        Cs_n  : IN    STD_LOGIC;
        Ras_n : IN    STD_LOGIC;
        Cas_n : IN    STD_LOGIC;
        We_n  : IN    STD_LOGIC;
        Dm    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0)
    );
END component;
 
 
begin
phy_reset <= fpga_reset;
MEMORY_DESIGN : MIG
  port map(
    cntrl0_ddr_dq                        => cntrl0_ddr_dq,
    cntrl0_ddr_a                         => cntrl0_ddr_a,
    cntrl0_ddr_ba                        => cntrl0_ddr_ba,
    cntrl0_ddr_cke                       => cntrl0_ddr_cke,
    cntrl0_ddr_cs_n                      => cntrl0_ddr_cs_n,
    cntrl0_ddr_ras_n                     => cntrl0_ddr_ras_n,
    cntrl0_ddr_cas_n                     => cntrl0_ddr_cas_n,
    cntrl0_ddr_we_n                      => cntrl0_ddr_we_n,
    cntrl0_ddr_dm                        => cntrl0_ddr_dm,
    sys_clk_p                            => sys_clk_p,
    sys_clk_n                            => sys_clk_n,
    clk200_p                             => clk200_p,
    clk200_n                             => clk200_n,
         clk_100_top                            => clk_100_top,
         clk_200_top                            => clk_200_top,
    init_done                            => init_done,
    sys_reset_in_n                       => system_reset,
    cntrl0_clk_tb                        => cntrl0_clk_tb,
    cntrl0_reset_tb                      => cntrl0_reset_tb,
    cntrl0_wdf_almost_full               => cntrl0_wdf_almost_full,
    cntrl0_af_almost_full                => cntrl0_af_almost_full,
    cntrl0_read_data_valid               => cntrl0_read_data_valid,
    cntrl0_app_wdf_wren                  => cntrl0_app_wdf_wren,
    cntrl0_app_af_wren                   => cntrl0_app_af_wren,
    cntrl0_burst_length_div2             => cntrl0_burst_length_div2,
    cntrl0_app_af_addr                   => cntrl0_app_af_addr,
    cntrl0_app_wdf_data                  => cntrl0_app_wdf_data,
    cntrl0_read_data_fifo_out            => cntrl0_read_data_fifo_out,
    cntrl0_app_mask_data                 => cntrl0_app_mask_data,
    cntrl0_ddr_dqs                       => cntrl0_ddr_dqs,
    cntrl0_ddr_ck                        => cntrl0_ddr_ck,
    cntrl0_ddr_ck_n                      => cntrl0_ddr_ck_n
         );
 
Address_Generation : MIG_addr_gen
  port map(
    clk0            => cntrl0_clk_tb,
    rst             => cntrl0_reset_tb,
    bkend_wraddr_en => bkend_wraddr_en_s,
         rx                               => rx,
         tx                               => tx,
--       leds                     => leds,
         cntrl0_app_af_addr     => cntrl0_app_af_addr,
    cntrl0_app_af_wren     => cntrl0_app_af_wren,
         cntrl0_app_mask_data                 => cntrl0_app_mask_data,
         cntrl0_app_wdf_wren                  => cntrl0_app_wdf_wren,
         cntrl0_app_wdf_data                  => cntrl0_app_wdf_data,
         cntrl0_read_data_valid               => cntrl0_read_data_valid,
         cntrl0_read_data_fifo_out            => cntrl0_read_data_fifo_out,
         init_done                                                                        => init_done,
         FIFO_empty                                                                     => FIFO_empty,
         read_enable                                                            => read_enable,
         write_enable                                                           => write_enable,
 
         -- eRCP and EmPAC Signals to/from top level
         phy_clock => phy_clock,
         phy_reset => phy_reset_dummy, --open,--phy_reset,
         phy_data_in => phy_data_in,
         phy_data_valid_in => phy_data_valid_in,
                                WIZ_rx_sdata => WIZ_rx_sdata,
                                WIZ_tx_sdata => WIZ_tx_sdata,
--                              ,
 
        --  Debug Signals to top level
--      rdcount => rdcount,
--                         wrcount => wrcount,
--                              empac_empty_debug => empac_empty_debug,
--                              empac_full_debug => empac_full_debug,
 
        ---==========================================================--
----===========Virtex-4 SRAM Port============================--
        wd => wd,
        sram_clk => sram_clk,
        sram_feedback_clk => sram_feedback_clk,
 
        sram_addr => sram_addr,
 
        sram_we_n => sram_we_n,
        sram_oe_n => sram_oe_n,
 
        sram_data => sram_data,
 
        sram_bw0 => sram_bw0,
        sram_bw1 => sram_bw1,
 
        sram_bw2 => sram_bw2,
        sram_bw3 => sram_bw3,
 
        sram_adv_ld_n => sram_adv_ld_n,
        sram_mode => sram_mode,
        sram_cen => sram_cen,
        sram_cen_test => sram_cen_test,
        sram_zz =>sram_zz
 
---=========================================================---
---=========================================================---
 
    );
--wrcount0 <= wrcount(6 downto 0);
--SIM_RAM_0 : MT46V16M16
-- --   GENERIC MAP(                                   -- Timing for -75Z CL2
----        tCK       : TIME    :=  7.500 ns;
----        tCH       : TIME    :=  3.375 ns;       -- 0.45*tCK
----        tCL       : TIME    :=  3.375 ns;       -- 0.45*tCK
----        tDH       : TIME    :=  0.500 ns;
----        tDS       : TIME    :=  0.500 ns;
----        tIH       : TIME    :=  0.900 ns;
----        tIS       : TIME    :=  0.900 ns;
----        tMRD      : TIME    := 15.000 ns;
----        tRAS      : TIME    := 40.000 ns;
----        tRAP      : TIME    := 20.000 ns;
----        tRC       : TIME    := 65.000 ns;
----        tRFC      : TIME    := 75.000 ns;
----        tRCD      : TIME    := 20.000 ns;
----        tRP       : TIME    := 20.000 ns;
----        tRRD      : TIME    := 15.000 ns;
----        tWR       : TIME    := 15.000 ns;
----        addr_bits : INTEGER := 13;
-- --       data_bits : INTEGER := 32;
----        cols_bits : INTEGER :=  9
----    );
--    PORT MAP(
--        Dq    => cntrl0_ddr_dq(15 downto 0),
--        Dqs   => cntrl0_ddr_dqs(1 downto 0),
--        Addr  => cntrl0_ddr_a,
--        Ba    => cntrl0_ddr_ba,
--        Clk   => cntrl0_ddr_ck(0),
--        Clk_n => cntrl0_ddr_ck_n(0),
--        Cke   => cntrl0_ddr_cke,
--        Cs_n  => cntrl0_ddr_cs_n,
--        Ras_n => cntrl0_ddr_ras_n,
--        Cas_n => cntrl0_ddr_cas_n,
--        We_n  => cntrl0_ddr_we_n,
--        Dm    => cntrl0_ddr_dm(1 downto 0)
--    );
--
--
--SIM_RAM_1 : MT46V16M16
-- --   GENERIC MAP(                                   -- Timing for -75Z CL2
----        tCK       : TIME    :=  7.500 ns;
----        tCH       : TIME    :=  3.375 ns;       -- 0.45*tCK
----        tCL       : TIME    :=  3.375 ns;       -- 0.45*tCK
----        tDH       : TIME    :=  0.500 ns;
----        tDS       : TIME    :=  0.500 ns;
----        tIH       : TIME    :=  0.900 ns;
----        tIS       : TIME    :=  0.900 ns;
----        tMRD      : TIME    := 15.000 ns;
----        tRAS      : TIME    := 40.000 ns;
----        tRAP      : TIME    := 20.000 ns;
----        tRC       : TIME    := 65.000 ns;
----        tRFC      : TIME    := 75.000 ns;
----        tRCD      : TIME    := 20.000 ns;
----        tRP       : TIME    := 20.000 ns;
----        tRRD      : TIME    := 15.000 ns;
----        tWR       : TIME    := 15.000 ns;
----        addr_bits : INTEGER := 13;
-- --       data_bits : INTEGER := 32;
----        cols_bits : INTEGER :=  9
----    );
--    PORT MAP(
--        Dq    => cntrl0_ddr_dq(31 downto 16),
--        Dqs   => cntrl0_ddr_dqs(3 downto 2),
--        Addr  => cntrl0_ddr_a,
--        Ba    => cntrl0_ddr_ba,
--        Clk   => cntrl0_ddr_ck(0),
--        Clk_n => cntrl0_ddr_ck_n(0),
--        Cke   => cntrl0_ddr_cke,
--        Cs_n  => cntrl0_ddr_cs_n,
--        Ras_n => cntrl0_ddr_ras_n,
--        Cas_n => cntrl0_ddr_cas_n,
--        We_n  => cntrl0_ddr_we_n,
--        Dm    => cntrl0_ddr_dm(3 downto 2)
--    );
--       
         DCM_BASE0: DCM_BASE
    generic map(
             CLKDV_DIVIDE      => 16.0,
             CLKFX_DIVIDE      => 8,
             CLKFX_MULTIPLY    => 2,
             DCM_PERFORMANCE_MODE  => "MAX_SPEED",
             DFS_FREQUENCY_MODE    => "LOW",
             DLL_FREQUENCY_MODE    => "LOW",
             DUTY_CYCLE_CORRECTION => TRUE,
             FACTORY_JF            => X"F0F0"
           )
    port map(
          CLK0      => clk_100_top,
          CLK180    => open,
          CLK270    => open,
          CLK2X     => clk_200_top,
          CLK2X180  => open,
          CLK90     => open,
          CLKDV     => open,
          CLKFX     => open,
          CLKFX180  => open,
          LOCKED    => dcm_lock,
          CLKFB     => clk_100_top_fb,
          CLKIN     => FPGA_clk_100_top,
          RST       => DCM_reset
        );
 
        system_clock_100_bufg: BUFG
    port map (
      O => clk_100_top_fb,
      I => clk_100_top
    );
 
reset_DCM : process(FPGA_clk_100_top,FPGA_reset)
begin
        if(FPGA_reset = '0') then
                DCM_reset <= '1';
                DCM_reset_0 <= '1';
                DCM_reset_1 <= '1';
                DCM_reset_2 <= '1';
                DCM_reset_3 <= '1';
        elsif (FPGA_clk_100_top'event and FPGA_clk_100_top = '1') then
                DCM_reset <= DCM_reset_0;
                DCM_reset_0 <= DCM_reset_1;
                DCM_reset_1 <= DCM_reset_2;
                DCM_reset_2 <= DCM_reset_3;
                DCM_reset_3 <= '0';
        end if;
end process reset_DCM;
 
-- Backup Version
--reset_DCM : process(FPGA_clk_100_top,FPGA_reset)
--begin
--      if(FPGA_reset = '0') then
--              DCM_reset <= '1';
--              DCM_reset_0 <= '1';
--              DCM_reset_1 <= '1';
--              DCM_reset_2 <= '1';
--              DCM_reset_3 <= '1';
--      else
--              DCM_reset <= DCM_reset_0;
--              DCM_reset_0 <= DCM_reset_1;
--              DCM_reset_1 <= DCM_reset_2;
--              DCM_reset_2 <= DCM_reset_3;
--              DCM_reset_3 <= '0';
--      end if;
--end process reset_DCM;
 
  process(clk_100_top, dcm_lock)
  begin
    if (dcm_lock = '0') then
      system_reset <= '0';
                system_reset_0 <= '0';
                system_reset_1 <= '0';
                system_reset_2 <= '0';
                system_reset_3 <= '0';
    elsif (clk_100_top'event and clk_100_top = '1') then
      system_reset <= system_reset_0;
                system_reset_0 <= system_reset_1;
                system_reset_1 <= system_reset_2;
                system_reset_2 <= system_reset_3;
                system_reset_3 <= '1';
    end if;
  end process;
 
 
end Behavioral;
 

Browse

Tools

Subversion Repositories the_wizardry_project

[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [TOP_LEVEL_TESTBENCH.vhd] - Blame information for rev 23

Line No.	Rev	Author	Line
1	23	mcwaccent	`----------------------------------------------------------------------------------`
2			`--`
3			`-- This file is a part of Technica Corporation Wizardry Project`
4			`--`
5			`-- Copyright (C) 2004-2009, Technica Corporation`
6			`--`
7			`-- This program is free software: you can redistribute it and/or modify`
8			`-- it under the terms of the GNU General Public License as published by`
9			`-- the Free Software Foundation, either version 3 of the License, or`
10			`-- (at your option) any later version.`
11			`--`
12			`-- This program is distributed in the hope that it will be useful,`
13			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
15			`-- GNU General Public License for more details.`
16			`--`
17			`-- You should have received a copy of the GNU General Public License`
18			`-- along with this program. If not, see <http://www.gnu.org/licenses/>.`
19			`--`
20			`----------------------------------------------------------------------------------`
21			`----------------------------------------------------------------------------------`
22			`-- Module Name: Top_Level_TESTBENCH - Structural`
23			`-- Project Name: Wizardry`
24			`-- Target Devices: Virtex 4 ML401`
25			`-- Description: Top-level structural description for Wizardry.`
26			`-- Revision: 1.0`
27			`-- Additional Comments:`
28			`--`
29			`----------------------------------------------------------------------------------`
30			`library IEEE;`
31			`use IEEE.STD_LOGIC_1164.ALL;`
32			`use IEEE.STD_LOGIC_ARITH.ALL;`
33			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
34
35			`---- Uncomment the following library declaration if instantiating`
36			`---- any Xilinx primitives in this code.`
37			`library UNISIM;`
38			`use UNISIM.VComponents.all;`
39
40			`entity TOP_LEVEL_TESTBENCH is`
41			`port(`
42			`FPGA_reset : in std_logic;`
43			`FPGA_clk_100_top : in std_logic;`
44			`rx : in std_logic;`
45			`tx : out std_logic;`
46			`-- leds : out std_logic_vector(8 downto 0);`
47			`-- FIFO_empty : out std_logic;`
48			`-- read_enable : out std_logic;`
49			`-- write_enable : out std_logic;`
50			`cntrl0_ddr_dq : inout std_logic_vector(31 downto 0);`
51			`cntrl0_ddr_dqs : inout std_logic_vector(3 downto 0);`
52			`cntrl0_ddr_a : out std_logic_vector(12 downto 0);`
53			`cntrl0_ddr_ba : out std_logic_vector(1 downto 0);`
54			`cntrl0_ddr_cke : out std_logic;`
55			`cntrl0_ddr_cs_n : out std_logic;`
56			`cntrl0_ddr_ras_n : out std_logic;`
57			`cntrl0_ddr_cas_n : out std_logic;`
58			`cntrl0_ddr_we_n : out std_logic;`
59			`cntrl0_ddr_dm : out std_logic_vector(3 downto 0);`
60			`cntrl0_ddr_ck : out std_logic_vector(1 downto 0);`
61			`cntrl0_ddr_ck_n : out std_logic_vector(1 downto 0);`
62
63			`-- eRCP and EmPAC Signals to/from top level`
64			`phy_clock : in std_logic;`
65			`phy_reset : out std_logic;`
66			`phy_data_in : in STD_LOGIC_VECTOR (3 downto 0);`
67			`phy_data_valid_in : in STD_LOGIC;`
68			`-- WIZ_rx_sdata : in STD_LOGIC;`
69			`-- WIZ_tx_sdata : out STD_LOGIC;`
70
71			`-- Debug Signals to top level`
72			`-- rdcount : out std_logic_vector(11 downto 0);`
73			`-- wrcount0 : out std_logic_vector(6 downto 0);`
74			`-- empac_empty_debug: out std_logic;`
75			`-- empac_full_debug : out std_logic;`
76
77			`---==========================================================--`
78			`----===========Virtex-4 SRAM Port============================--`
79			`wd : out std_logic;`
80			`sram_clk : out std_logic;`
81			`sram_feedback_clk : out std_logic;`
82
83			`sram_addr : out std_logic_vector(22 downto 0);`
84
85			`sram_we_n : out std_logic;`
86			`sram_oe_n : out std_logic;`
87
88			`sram_data : inout std_logic_vector(31 downto 0);`
89
90			`sram_bw0: out std_logic;`
91			`sram_bw1 : out std_logic;`
92
93			`sram_bw2 : out std_Logic;`
94			`sram_bw3 : out std_logic;`
95
96			`sram_adv_ld_n : out std_logic;`
97			`sram_mode : out std_logic;`
98			`sram_cen : out std_logic;`
99			`sram_cen_test : out std_logic;`
100			`sram_zz : out std_logic`
101
102			`---=========================================================---`
103			`---=========================================================---`
104
105			`);`
106			`end TOP_LEVEL_TESTBENCH;`
107
108			`architecture Behavioral of TOP_LEVEL_TESTBENCH is`
109
110			`signal rdcount : std_logic_Vector(11 downto 0);`
111			`signal WIZ_rx_sdata : sTD_LOGIC;`
112			`signal WIZ_tx_sdata : STD_LOGIC;`
113			`--signal leds : std_logic_vector(8 downto 0);`
114			`signal FIFO_empty : std_logic;`
115			`signal read_enable : std_logic;`
116			`signal write_enable : std_logic;`
117
118			`Component MIG is`
119			`port(`
120			`cntrl0_ddr_dq : inout std_logic_vector(31 downto 0);`
121			`cntrl0_ddr_a : out std_logic_vector(12 downto 0);`
122			`cntrl0_ddr_ba : out std_logic_vector(1 downto 0);`
123			`cntrl0_ddr_cke : out std_logic;`
124			`cntrl0_ddr_cs_n : out std_logic;`
125			`cntrl0_ddr_ras_n : out std_logic;`
126			`cntrl0_ddr_cas_n : out std_logic;`
127			`cntrl0_ddr_we_n : out std_logic;`
128			`cntrl0_ddr_dm : out std_logic_vector(3 downto 0);`
129			`sys_clk_p : in std_logic;`
130			`sys_clk_n : in std_logic;`
131			`clk200_p : in std_logic;`
132			`clk200_n : in std_logic;`
133			`clk_100_top : in std_logic;`
134			`clk_200_top : in std_logic;`
135			`init_done : out std_logic;`
136			`sys_reset_in_n : in std_logic;`
137			`cntrl0_clk_tb : out std_logic;`
138			`cntrl0_reset_tb : out std_logic;`
139			`cntrl0_wdf_almost_full : out std_logic;`
140			`cntrl0_af_almost_full : out std_logic;`
141			`cntrl0_read_data_valid : out std_logic;`
142			`cntrl0_app_wdf_wren : in std_logic;`
143			`cntrl0_app_af_wren : in std_logic;`
144			`cntrl0_burst_length_div2 : out std_logic_vector(2 downto 0);`
145			`cntrl0_app_af_addr : in std_logic_vector(35 downto 0);`
146			`cntrl0_app_wdf_data : in std_logic_vector(63 downto 0);`
147			`cntrl0_read_data_fifo_out : out std_logic_vector(63 downto 0);`
148			`cntrl0_app_mask_data : in std_logic_vector(7 downto 0);`
149			`cntrl0_ddr_dqs : inout std_logic_vector(3 downto 0);`
150			`cntrl0_ddr_ck : out std_logic_vector(1 downto 0);`
151			`cntrl0_ddr_ck_n : out std_logic_vector(1 downto 0)`
152			`);`
153			`end Component;`
154
155			`--signal cntrl0_ddr_dq : std_logic_vector(31 downto 0);`
156			`--signal cntrl0_ddr_a : std_logic_vector(12 downto 0);`
157			`--signal cntrl0_ddr_ba : std_logic_vector(1 downto 0);`
158			`--signal cntrl0_ddr_cke : std_logic;`
159			`--signal cntrl0_ddr_cs_n : std_logic;`
160			`--signal cntrl0_ddr_ras_n : std_logic;`
161			`--signal cntrl0_ddr_cas_n : std_logic;`
162			`--signal cntrl0_ddr_we_n : std_logic;`
163			`--signal cntrl0_ddr_dm : std_logic_vector(3 downto 0);`
164			`signal sys_clk_p : std_logic;`
165			`signal sys_clk_n : std_logic;`
166			`signal clk200_p : std_logic;`
167			`signal clk200_n : std_logic;`
168			`signal init_done : std_logic := '0';`
169			`signal sys_reset_in_n : std_logic;`
170			`signal cntrl0_clk_tb : std_logic;`
171			`signal cntrl0_reset_tb : std_logic;`
172			`signal cntrl0_wdf_almost_full : std_logic;`
173			`signal cntrl0_af_almost_full : std_logic;`
174			`signal cntrl0_read_data_valid : std_logic;`
175			`signal cntrl0_app_wdf_wren : std_logic;`
176			`signal cntrl0_app_af_wren : std_logic;`
177			`signal cntrl0_burst_length_div2 : std_logic_vector(2 downto 0);`
178			`signal cntrl0_app_af_addr : std_logic_vector(35 downto 0);`
179			`signal cntrl0_app_wdf_data : std_logic_vector(63 downto 0);`
180			`signal cntrl0_read_data_fifo_out : std_logic_vector(63 downto 0);`
181			`signal cntrl0_app_mask_data : std_logic_vector(7 downto 0);`
182			`--signal cntrl0_ddr_dqs : std_logic_vector(3 downto 0);`
183			`--signal cntrl0_ddr_ck : std_logic_vector(1 downto 0);`
184			`--signal cntrl0_ddr_ck_n : std_logic_vector(1 downto 0);`
185			`signal bkend_wraddr_en_s : std_logic;`
186			`signal clk_100_top : std_logic;`
187			`signal clk_200_top : std_logic;`
188			`signal system_clock_100, system_clock_200 : std_logic;`
189			`signal clk_100_top_fb : std_logic;`
190			`signal dcm_lock : std_logic;`
191
192			`signal DCM_reset : std_logic;`
193			`signal DCM_reset_0 : std_logic;`
194			`signal DCM_reset_1 : std_logic;`
195			`signal DCM_reset_2 : std_logic;`
196			`signal DCM_reset_3 : std_logic;`
197
198			`signal system_reset : std_logic;`
199			`signal system_reset_0 : std_logic;`
200			`signal system_reset_1 : std_logic;`
201			`signal system_reset_2 : std_logic;`
202			`signal system_reset_3 : std_logic;`
203			`signal phy_reset_dummy : std_logic;`
204			`signal wrcount : std_logic_vector(11 downto 0);`
205
206			`component MIG_addr_gen is`
207			`port (`
208			`clk0 : in std_logic;`
209			`rst : in std_logic;`
210			`bkend_wraddr_en : in std_logic;`
211			`rx : in std_logic;`
212			`tx : out std_logic;`
213			`-- leds : out std_logic_vector(8 downto 0);`
214			`cntrl0_app_af_addr : out std_logic_vector(35 downto 0);`
215			`cntrl0_app_af_wren : out std_logic;`
216			`cntrl0_app_mask_data : out std_logic_vector(7 downto 0);`
217			`cntrl0_app_wdf_wren : out std_logic;`
218			`cntrl0_app_wdf_data : out std_logic_vector(63 downto 0);`
219			`cntrl0_read_data_valid : in std_logic;`
220			`cntrl0_read_data_fifo_out : in std_logic_vector(63 downto 0);`
221			`init_done : in std_logic;`
222			`FIFO_empty : out std_logic;`
223			`read_enable : out std_logic;`
224			`write_enable : out std_logic;`
225
226			`-- eRCP and EmPAC Signals to/from top level`
227			`phy_clock : in std_logic;`
228			`phy_reset : out std_logic;`
229			`phy_data_in : in STD_LOGIC_VECTOR (3 downto 0);`
230			`phy_data_valid_in : in STD_LOGIC;`
231			`WIZ_rx_sdata : in STD_LOGIC;`
232			`WIZ_tx_sdata : out STD_LOGIC;`
233
234			`-- Debug Signals to top level`
235			`-- rdcount : out std_logic_vector(11 downto 0);`
236			`-- wrcount : out std_logic_vector(11 downto 0);`
237			`-- empac_empty_debug: out std_logic;`
238			`-- empac_full_debug : out std_logic;`
239
240			`---==========================================================--`
241			`----===========Virtex-4 SRAM Port============================--`
242			`wd : out std_logic;`
243			`sram_clk : out std_logic;`
244			`sram_feedback_clk : out std_logic;`
245
246			`sram_addr : out std_logic_vector(22 downto 0);`
247
248			`sram_we_n : out std_logic;`
249			`sram_oe_n : out std_logic;`
250
251			`sram_data : inout std_logic_vector(31 downto 0);`
252
253			`sram_bw0: out std_logic;`
254			`sram_bw1 : out std_logic;`
255
256			`sram_bw2 : out std_Logic;`
257			`sram_bw3 : out std_logic;`
258
259			`sram_adv_ld_n : out std_logic;`
260			`sram_mode : out std_logic;`
261			`sram_cen : out std_logic;`
262			`sram_cen_test : out std_logic;`
263			`sram_zz : out std_logic`
264
265
266			`);`
267			`end component;`
268
269			`Component MT46V16M16 IS`
270			`GENERIC ( -- Timing for -75Z CL2`
271			`tCK : TIME := 7.500 ns;`
272			`tCH : TIME := 3.375 ns; -- 0.45*tCK`
273			`tCL : TIME := 3.375 ns; -- 0.45*tCK`
274			`tDH : TIME := 0.500 ns;`
275			`tDS : TIME := 0.500 ns;`
276			`tIH : TIME := 0.900 ns;`
277			`tIS : TIME := 0.900 ns;`
278			`tMRD : TIME := 15.000 ns;`
279			`tRAS : TIME := 40.000 ns;`
280			`tRAP : TIME := 20.000 ns;`
281			`tRC : TIME := 65.000 ns;`
282			`tRFC : TIME := 75.000 ns;`
283			`tRCD : TIME := 20.000 ns;`
284			`tRP : TIME := 20.000 ns;`
285			`tRRD : TIME := 15.000 ns;`
286			`tWR : TIME := 15.000 ns;`
287			`addr_bits : INTEGER := 13;`
288			`data_bits : INTEGER := 16;`
289			`cols_bits : INTEGER := 9`
290			`);`
291			`PORT (`
292			`Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');`
293			`Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";`
294			`Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);`
295			`Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);`
296			`Clk : IN STD_LOGIC;`
297			`Clk_n : IN STD_LOGIC;`
298			`Cke : IN STD_LOGIC;`
299			`Cs_n : IN STD_LOGIC;`
300			`Ras_n : IN STD_LOGIC;`
301			`Cas_n : IN STD_LOGIC;`
302			`We_n : IN STD_LOGIC;`
303			`Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)`
304			`);`
305			`END component;`
306
307
308			`begin`
309			`phy_reset <= fpga_reset;`
310			`MEMORY_DESIGN : MIG`
311			`port map(`
312			`cntrl0_ddr_dq => cntrl0_ddr_dq,`
313			`cntrl0_ddr_a => cntrl0_ddr_a,`
314			`cntrl0_ddr_ba => cntrl0_ddr_ba,`
315			`cntrl0_ddr_cke => cntrl0_ddr_cke,`
316			`cntrl0_ddr_cs_n => cntrl0_ddr_cs_n,`
317			`cntrl0_ddr_ras_n => cntrl0_ddr_ras_n,`
318			`cntrl0_ddr_cas_n => cntrl0_ddr_cas_n,`
319			`cntrl0_ddr_we_n => cntrl0_ddr_we_n,`
320			`cntrl0_ddr_dm => cntrl0_ddr_dm,`
321			`sys_clk_p => sys_clk_p,`
322			`sys_clk_n => sys_clk_n,`
323			`clk200_p => clk200_p,`
324			`clk200_n => clk200_n,`
325			`clk_100_top => clk_100_top,`
326			`clk_200_top => clk_200_top,`
327			`init_done => init_done,`
328			`sys_reset_in_n => system_reset,`
329			`cntrl0_clk_tb => cntrl0_clk_tb,`
330			`cntrl0_reset_tb => cntrl0_reset_tb,`
331			`cntrl0_wdf_almost_full => cntrl0_wdf_almost_full,`
332			`cntrl0_af_almost_full => cntrl0_af_almost_full,`
333			`cntrl0_read_data_valid => cntrl0_read_data_valid,`
334			`cntrl0_app_wdf_wren => cntrl0_app_wdf_wren,`
335			`cntrl0_app_af_wren => cntrl0_app_af_wren,`
336			`cntrl0_burst_length_div2 => cntrl0_burst_length_div2,`
337			`cntrl0_app_af_addr => cntrl0_app_af_addr,`
338			`cntrl0_app_wdf_data => cntrl0_app_wdf_data,`
339			`cntrl0_read_data_fifo_out => cntrl0_read_data_fifo_out,`
340			`cntrl0_app_mask_data => cntrl0_app_mask_data,`
341			`cntrl0_ddr_dqs => cntrl0_ddr_dqs,`
342			`cntrl0_ddr_ck => cntrl0_ddr_ck,`
343			`cntrl0_ddr_ck_n => cntrl0_ddr_ck_n`
344			`);`
345
346			`Address_Generation : MIG_addr_gen`
347			`port map(`
348			`clk0 => cntrl0_clk_tb,`
349			`rst => cntrl0_reset_tb,`
350			`bkend_wraddr_en => bkend_wraddr_en_s,`
351			`rx => rx,`
352			`tx => tx,`
353			`-- leds => leds,`
354			`cntrl0_app_af_addr => cntrl0_app_af_addr,`
355			`cntrl0_app_af_wren => cntrl0_app_af_wren,`
356			`cntrl0_app_mask_data => cntrl0_app_mask_data,`
357			`cntrl0_app_wdf_wren => cntrl0_app_wdf_wren,`
358			`cntrl0_app_wdf_data => cntrl0_app_wdf_data,`
359			`cntrl0_read_data_valid => cntrl0_read_data_valid,`
360			`cntrl0_read_data_fifo_out => cntrl0_read_data_fifo_out,`
361			`init_done => init_done,`
362			`FIFO_empty => FIFO_empty,`
363			`read_enable => read_enable,`
364			`write_enable => write_enable,`
365
366			`-- eRCP and EmPAC Signals to/from top level`
367			`phy_clock => phy_clock,`
368			`phy_reset => phy_reset_dummy, --open,--phy_reset,`
369			`phy_data_in => phy_data_in,`
370			`phy_data_valid_in => phy_data_valid_in,`
371			`WIZ_rx_sdata => WIZ_rx_sdata,`
372			`WIZ_tx_sdata => WIZ_tx_sdata,`
373			`-- ,`
374
375			`-- Debug Signals to top level`
376			`-- rdcount => rdcount,`
377			`-- wrcount => wrcount,`
378			`-- empac_empty_debug => empac_empty_debug,`
379			`-- empac_full_debug => empac_full_debug,`
380
381			`---==========================================================--`
382			`----===========Virtex-4 SRAM Port============================--`
383			`wd => wd,`
384			`sram_clk => sram_clk,`
385			`sram_feedback_clk => sram_feedback_clk,`
386
387			`sram_addr => sram_addr,`
388
389			`sram_we_n => sram_we_n,`
390			`sram_oe_n => sram_oe_n,`
391
392			`sram_data => sram_data,`
393
394			`sram_bw0 => sram_bw0,`
395			`sram_bw1 => sram_bw1,`
396
397			`sram_bw2 => sram_bw2,`
398			`sram_bw3 => sram_bw3,`
399
400			`sram_adv_ld_n => sram_adv_ld_n,`
401			`sram_mode => sram_mode,`
402			`sram_cen => sram_cen,`
403			`sram_cen_test => sram_cen_test,`
404			`sram_zz =>sram_zz`
405
406			`---=========================================================---`
407			`---=========================================================---`
408
409			`);`
410			`--wrcount0 <= wrcount(6 downto 0);`
411			`--SIM_RAM_0 : MT46V16M16`
412			`-- -- GENERIC MAP( -- Timing for -75Z CL2`
413			`---- tCK : TIME := 7.500 ns;`
414			`---- tCH : TIME := 3.375 ns; -- 0.45*tCK`
415			`---- tCL : TIME := 3.375 ns; -- 0.45*tCK`
416			`---- tDH : TIME := 0.500 ns;`
417			`---- tDS : TIME := 0.500 ns;`
418			`---- tIH : TIME := 0.900 ns;`
419			`---- tIS : TIME := 0.900 ns;`
420			`---- tMRD : TIME := 15.000 ns;`
421			`---- tRAS : TIME := 40.000 ns;`
422			`---- tRAP : TIME := 20.000 ns;`
423			`---- tRC : TIME := 65.000 ns;`
424			`---- tRFC : TIME := 75.000 ns;`
425			`---- tRCD : TIME := 20.000 ns;`
426			`---- tRP : TIME := 20.000 ns;`
427			`---- tRRD : TIME := 15.000 ns;`
428			`---- tWR : TIME := 15.000 ns;`
429			`---- addr_bits : INTEGER := 13;`
430			`-- -- data_bits : INTEGER := 32;`
431			`---- cols_bits : INTEGER := 9`
432			`---- );`
433			`-- PORT MAP(`
434			`-- Dq => cntrl0_ddr_dq(15 downto 0),`
435			`-- Dqs => cntrl0_ddr_dqs(1 downto 0),`
436			`-- Addr => cntrl0_ddr_a,`
437			`-- Ba => cntrl0_ddr_ba,`
438			`-- Clk => cntrl0_ddr_ck(0),`
439			`-- Clk_n => cntrl0_ddr_ck_n(0),`
440			`-- Cke => cntrl0_ddr_cke,`
441			`-- Cs_n => cntrl0_ddr_cs_n,`
442			`-- Ras_n => cntrl0_ddr_ras_n,`
443			`-- Cas_n => cntrl0_ddr_cas_n,`
444			`-- We_n => cntrl0_ddr_we_n,`
445			`-- Dm => cntrl0_ddr_dm(1 downto 0)`
446			`-- );`
447			`--`
448			`--`
449			`--SIM_RAM_1 : MT46V16M16`
450			`-- -- GENERIC MAP( -- Timing for -75Z CL2`
451			`---- tCK : TIME := 7.500 ns;`
452			`---- tCH : TIME := 3.375 ns; -- 0.45*tCK`
453			`---- tCL : TIME := 3.375 ns; -- 0.45*tCK`
454			`---- tDH : TIME := 0.500 ns;`
455			`---- tDS : TIME := 0.500 ns;`
456			`---- tIH : TIME := 0.900 ns;`
457			`---- tIS : TIME := 0.900 ns;`
458			`---- tMRD : TIME := 15.000 ns;`
459			`---- tRAS : TIME := 40.000 ns;`
460			`---- tRAP : TIME := 20.000 ns;`
461			`---- tRC : TIME := 65.000 ns;`
462			`---- tRFC : TIME := 75.000 ns;`
463			`---- tRCD : TIME := 20.000 ns;`
464			`---- tRP : TIME := 20.000 ns;`
465			`---- tRRD : TIME := 15.000 ns;`
466			`---- tWR : TIME := 15.000 ns;`
467			`---- addr_bits : INTEGER := 13;`
468			`-- -- data_bits : INTEGER := 32;`
469			`---- cols_bits : INTEGER := 9`
470			`---- );`
471			`-- PORT MAP(`
472			`-- Dq => cntrl0_ddr_dq(31 downto 16),`
473			`-- Dqs => cntrl0_ddr_dqs(3 downto 2),`
474			`-- Addr => cntrl0_ddr_a,`
475			`-- Ba => cntrl0_ddr_ba,`
476			`-- Clk => cntrl0_ddr_ck(0),`
477			`-- Clk_n => cntrl0_ddr_ck_n(0),`
478			`-- Cke => cntrl0_ddr_cke,`
479			`-- Cs_n => cntrl0_ddr_cs_n,`
480			`-- Ras_n => cntrl0_ddr_ras_n,`
481			`-- Cas_n => cntrl0_ddr_cas_n,`
482			`-- We_n => cntrl0_ddr_we_n,`
483			`-- Dm => cntrl0_ddr_dm(3 downto 2)`
484			`-- );`
485			`--`
486			`DCM_BASE0: DCM_BASE`
487			`generic map(`
488			`CLKDV_DIVIDE => 16.0,`
489			`CLKFX_DIVIDE => 8,`
490			`CLKFX_MULTIPLY => 2,`
491			`DCM_PERFORMANCE_MODE => "MAX_SPEED",`
492			`DFS_FREQUENCY_MODE => "LOW",`
493			`DLL_FREQUENCY_MODE => "LOW",`
494			`DUTY_CYCLE_CORRECTION => TRUE,`
495			`FACTORY_JF => X"F0F0"`
496			`)`
497			`port map(`
498			`CLK0 => clk_100_top,`
499			`CLK180 => open,`
500			`CLK270 => open,`
501			`CLK2X => clk_200_top,`
502			`CLK2X180 => open,`
503			`CLK90 => open,`
504			`CLKDV => open,`
505			`CLKFX => open,`
506			`CLKFX180 => open,`
507			`LOCKED => dcm_lock,`
508			`CLKFB => clk_100_top_fb,`
509			`CLKIN => FPGA_clk_100_top,`
510			`RST => DCM_reset`
511			`);`
512
513			`system_clock_100_bufg: BUFG`
514			`port map (`
515			`O => clk_100_top_fb,`
516			`I => clk_100_top`
517			`);`
518
519			`reset_DCM : process(FPGA_clk_100_top,FPGA_reset)`
520			`begin`
521			`if(FPGA_reset = '0') then`
522			`DCM_reset <= '1';`
523			`DCM_reset_0 <= '1';`
524			`DCM_reset_1 <= '1';`
525			`DCM_reset_2 <= '1';`
526			`DCM_reset_3 <= '1';`
527			`elsif (FPGA_clk_100_top'event and FPGA_clk_100_top = '1') then`
528			`DCM_reset <= DCM_reset_0;`
529			`DCM_reset_0 <= DCM_reset_1;`
530			`DCM_reset_1 <= DCM_reset_2;`
531			`DCM_reset_2 <= DCM_reset_3;`
532			`DCM_reset_3 <= '0';`
533			`end if;`
534			`end process reset_DCM;`
535
536			`-- Backup Version`
537			`--reset_DCM : process(FPGA_clk_100_top,FPGA_reset)`
538			`--begin`
539			`-- if(FPGA_reset = '0') then`
540			`-- DCM_reset <= '1';`
541			`-- DCM_reset_0 <= '1';`
542			`-- DCM_reset_1 <= '1';`
543			`-- DCM_reset_2 <= '1';`
544			`-- DCM_reset_3 <= '1';`
545			`-- else`
546			`-- DCM_reset <= DCM_reset_0;`
547			`-- DCM_reset_0 <= DCM_reset_1;`
548			`-- DCM_reset_1 <= DCM_reset_2;`
549			`-- DCM_reset_2 <= DCM_reset_3;`
550			`-- DCM_reset_3 <= '0';`
551			`-- end if;`
552			`--end process reset_DCM;`
553
554			`process(clk_100_top, dcm_lock)`
555			`begin`
556			`if (dcm_lock = '0') then`
557			`system_reset <= '0';`
558			`system_reset_0 <= '0';`
559			`system_reset_1 <= '0';`
560			`system_reset_2 <= '0';`
561			`system_reset_3 <= '0';`
562			`elsif (clk_100_top'event and clk_100_top = '1') then`
563			`system_reset <= system_reset_0;`
564			`system_reset_0 <= system_reset_1;`
565			`system_reset_1 <= system_reset_2;`
566			`system_reset_2 <= system_reset_3;`
567			`system_reset_3 <= '1';`
568			`end if;`
569			`end process;`
570
571
572			`end Behavioral;`
573