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mcwaccent |
############################################################################
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##
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## Xilinx, Inc. 2006 www.xilinx.com
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## Mon Nov 5 13:16:46 2007
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## Generated by MIG Version 2.0
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##
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############################################################################
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## File name : MIG.ucf
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##
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## Details : Constraints file
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## FPGA family: virtex4
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## FPGA: xc4vfx12-ff668
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## Speedgrade: -10
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## Design Entry: vhdl
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## Frequency: 100 MHz
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## Design: without Test bench
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## DCM Used: Enable
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## No.Of Controllers: 1
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##
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############################################################################
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############################################################################
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# Clock constraints #
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############################################################################
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#NET "infrastructure0/sys_clk_in" TNM_NET = "SYS_CLK";
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#TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 10 ns HIGH 50 %;
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#
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#NET "infrastructure0/ref_clk200_in" TNM_NET = "CLK_200";
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#TIMESPEC "TS_SYS_CLK200" = PERIOD "CLK_200" 5 ns HIGH 50 %;
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#
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#NET "infrastructure0/clk_100_top" TNM_NET = "SYS_CLK";
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#TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 10 ns HIGH 50 %;
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#
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#NET "infrastructure0/clk_200_top" TNM_NET = "CLK_200";
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#TIMESPEC "TS_SYS_CLK200" = PERIOD "CLK_200" 5 ns HIGH 50 %;
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###UNCOMMENT THIS. JUST A QUICK TEST FOR CLOCKS
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NET "MEMORY_DESIGN/infrastructure0/clk0_bufg_in" TNM_NET = "SYS_CLK";
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TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 10 ns HIGH 50 %;
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NET "Address_Generation/Wizardry_Top_Level/EmPAC_Component/clkdiv/clk_div_s" TNM_NET = "DIV_PHY_CLK";
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TIMESPEC "TS_DIV_PHY_CLK" = PERIOD "DIV_PHY_CLK" 80 ns HIGH 50 %;
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NET "PHY_CLOCK" TNM_NET = "PHY_CLK";
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TIMESPEC "TS_PHY_CLK" = PERIOD "PHY_CLK" 40 ns HIGH 50 %;
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NET "MEMORY_DESIGN/infrastructure0/clk90_bufg_in" TNM_NET = "SYS_CLK_90";
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TIMESPEC "TS_SYS_CLK_90" = PERIOD "SYS_CLK_90" 10 ns HIGH 50 %;
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########################################################################
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# Controller 0
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# Memory Device: DDR_SDRAM->Components->Infineon2 #
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# Datawidth: 32 #
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########################################################################
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######################################################################################################
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# I/O STANDARDS
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######################################################################################################
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#NET "cntrl0_ddr_dq[*]" IOSTANDARD = SSTL2_II_DCI;
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#NET "cntrl0_ddr_a[*]" IOSTANDARD = SSTL2_I;
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#NET "cntrl0_ddr_ba[*]" IOSTANDARD = SSTL2_I;
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#NET "cntrl0_ddr_cke" IOSTANDARD = SSTL2_I;
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#NET "cntrl0_ddr_cs_n" IOSTANDARD = SSTL2_I;
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#NET "cntrl0_ddr_ras_n" IOSTANDARD = SSTL2_I;
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#NET "cntrl0_ddr_cas_n" IOSTANDARD = SSTL2_I;
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#NET "cntrl0_ddr_we_n" IOSTANDARD = SSTL2_I;
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#NET "cntrl0_ddr_dm[*]" IOSTANDARD = SSTL2_II;
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##NET "sys_clk_p" IOSTANDARD = LVPECL_25;
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##NET "sys_clk_n" IOSTANDARD = LVPECL_25;
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#NET "FPGA_clk_100_top" IOSTANDARD = LVCMOS25;
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##NET "clk_200_top" IOSTANDARD = SSTL2_I;
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##NET "clk200_p" IOSTANDARD = LVPECL_25;
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##NET "clk200_n" IOSTANDARD = LVPECL_25;
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##NET "init_done" IOSTANDARD = LVCMOS25;
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NET "FPGA_reset" IOSTANDARD = LVCMOS25;
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NET "phy_clock" IOSTANDARD = LVCMOS25;
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NET "phy_reset" IOSTANDARD = LVCMOS25;
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#NET "cntrl0_ddr_dqs[*]" IOSTANDARD = SSTL2_II_DCI;
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#NET "cntrl0_ddr_ck[*]" IOSTANDARD = DIFF_SSTL2_II;
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#NET "cntrl0_ddr_ck_n[*]" IOSTANDARD = DIFF_SSTL2_II;
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NET "cntrl0_DDR_DQ[*]" IOSTANDARD = SSTL2_II;
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NET "cntrl0_DDR_A[*]" IOSTANDARD = SSTL2_II;
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NET "cntrl0_DDR_BA[*]" IOSTANDARD = SSTL2_II;
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NET "cntrl0_DDR_CKE" IOSTANDARD = SSTL2_II;
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NET "cntrl0_DDR_CS_N" IOSTANDARD = SSTL2_II;
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NET "cntrl0_DDR_RAS_N" IOSTANDARD = SSTL2_II;
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NET "cntrl0_DDR_CAS_N" IOSTANDARD = SSTL2_II;
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NET "cntrl0_DDR_WE_N" IOSTANDARD = SSTL2_II;
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NET "cntrl0_DDR_DM[*]" IOSTANDARD = SSTL2_II;
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#NET "SYS_CLK_P" IOSTANDARD = LVDS_25;
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#NET "SYS_CLK_N" IOSTANDARD = LVDS_25;
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#NET "FPGA_clk_100_top" IOSTANDARD = LVCMOS25;
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#NET "cntrl0_ERROR" IOSTANDARD = LVCMOS25;
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NET "FPGA_clk_100_top" IOSTANDARD = LVCMOS25;
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#NET "rx" IOSTANDARD = LVCMOS33;#SSTL2_II;
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#NET "tx" IOSTANDARD = LVCMOS33;#SSTL2_II;
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#NET UART_state_leds[*] IOSTANDARD = LVCMOS25;
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NET "cntrl0_DDR_DQS[*]" IOSTANDARD = SSTL2_II;
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NET "cntrl0_DDR_CK[*]" IOSTANDARD = DIFF_SSTL2_II;
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NET "cntrl0_DDR_CK_N[*]" IOSTANDARD = DIFF_SSTL2_II;
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######################################################################################################
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# Area Group Constraints
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######################################################################################################
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INST "MEMORY_DESIGN/top_00/iobs_00/data_path_iobs_00/v4_dqs_iob0*" AREA_GROUP=dqs_gp0;
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AREA_GROUP "dqs_gp0" COMPRESSION = 0; # no compression
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INST "MEMORY_DESIGN/top_00/iobs_00/data_path_iobs_00/v4_dqs_iob1*" AREA_GROUP=dqs_gp1;
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AREA_GROUP "dqs_gp1" COMPRESSION = 0; # no compression
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INST "MEMORY_DESIGN/top_00/iobs_00/data_path_iobs_00/v4_dqs_iob2*" AREA_GROUP=dqs_gp2;
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AREA_GROUP "dqs_gp2" COMPRESSION = 0; # no compression
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INST "MEMORY_DESIGN/top_00/iobs_00/data_path_iobs_00/v4_dqs_iob3*" AREA_GROUP=dqs_gp3;
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AREA_GROUP "dqs_gp3" COMPRESSION = 0; # no compression
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INST "MEMORY_DESIGN/top_00/data_path_00/tap_logic_00/data_tap_inc_0*" AREA_GROUP=data_tap_gp0;
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AREA_GROUP "data_tap_gp0" COMPRESSION = 0; # no compression
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#NET "cntrl0_ddr_dq[0]" LOC = "C17" ; #Bank 5
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#NET "cntrl0_ddr_dq[1]" LOC = "D17" ; #Bank 5
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#NET "cntrl0_ddr_dq[2]" LOC = "C20" ; #Bank 5
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#NET "cntrl0_ddr_dq[3]" LOC = "B20" ; #Bank 5
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#NET "cntrl0_ddr_dq[4]" LOC = "B18" ; #Bank 5
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#NET "cntrl0_ddr_dq[5]" LOC = "A18" ; #Bank 5
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#NET "cntrl0_ddr_dq[6]" LOC = "D20" ; #Bank 5
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#NET "cntrl0_ddr_dq[7]" LOC = "E17" ; #Bank 5
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#NET "cntrl0_ddr_dq[8]" LOC = "C21" ; #Bank 5
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#NET "cntrl0_ddr_dq[9]" LOC = "B21" ; #Bank 5
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#NET "cntrl0_ddr_dq[10]" LOC = "C19" ; #Bank 5
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#NET "cntrl0_ddr_dq[11]" LOC = "D18" ; #Bank 5
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#NET "cntrl0_ddr_dq[12]" LOC = "B24" ; #Bank 5
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#NET "cntrl0_ddr_dq[13]" LOC = "B23" ; #Bank 5
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#NET "cntrl0_ddr_dq[14]" LOC = "F18" ; #Bank 5
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#NET "cntrl0_ddr_dq[15]" LOC = "E18" ; #Bank 5
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#NET "cntrl0_ddr_dq[16]" LOC = "A20" ; #Bank 5
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#NET "cntrl0_ddr_dq[17]" LOC = "A19" ; #Bank 5
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#NET "cntrl0_ddr_dq[18]" LOC = "D22" ; #Bank 5
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#NET "cntrl0_ddr_dq[19]" LOC = "C22" ; #Bank 5
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#NET "cntrl0_ddr_dq[20]" LOC = "A22" ; #Bank 5
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#NET "cntrl0_ddr_dq[21]" LOC = "A21" ; #Bank 5
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#NET "cntrl0_ddr_dq[22]" LOC = "D24" ; #Bank 5
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#NET "cntrl0_ddr_dq[23]" LOC = "C24" ; #Bank 5
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#NET "cntrl0_ddr_dq[24]" LOC = "F19" ; #Bank 5
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#NET "cntrl0_ddr_dq[25]" LOC = "E23" ; #Bank 5
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#NET "cntrl0_ddr_dq[26]" LOC = "E22" ; #Bank 5
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#NET "cntrl0_ddr_dq[27]" LOC = "F20" ; #Bank 5
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#NET "cntrl0_ddr_dq[28]" LOC = "E20" ; #Bank 5
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#NET "cntrl0_ddr_dq[29]" LOC = "C26" ; #Bank 5
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#NET "cntrl0_ddr_dq[30]" LOC = "D23" ; #Bank 5
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#NET "cntrl0_ddr_dq[31]" LOC = "C23" ; #Bank 5
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#NET "cntrl0_ddr_a[12]" LOC = "A23" ; #Bank 5
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#NET "cntrl0_ddr_a[11]" LOC = "G17" ; #Bank 5
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#NET "cntrl0_ddr_a[10]" LOC = "G20" ; #Bank 5
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#NET "cntrl0_ddr_a[9]" LOC = "F23" ; #Bank 5
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#NET "cntrl0_ddr_a[8]" LOC = "D25" ; #Bank 5
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#NET "cntrl0_ddr_a[7]" LOC = "G24" ; #Bank 5
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#NET "cntrl0_ddr_a[6]" LOC = "F26" ; #Bank 5
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#NET "cntrl0_ddr_a[5]" LOC = "E26" ; #Bank 5
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#NET "cntrl0_ddr_a[4]" LOC = "H24" ; #Bank 5
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#NET "cntrl0_ddr_a[3]" LOC = "H23" ; #Bank 5
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#NET "cntrl0_ddr_a[2]" LOC = "G26" ; #Bank 5
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#NET "cntrl0_ddr_a[1]" LOC = "G25" ; #Bank 5
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#NET "cntrl0_ddr_a[0]" LOC = "H26" ; #Bank 5
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#NET "cntrl0_ddr_ba[1]" LOC = "H25" ; #Bank 5
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#NET "cntrl0_ddr_ba[0]" LOC = "V21" ; #Bank 7
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#NET "cntrl0_ddr_cke" LOC = "V22" ; #Bank 7
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#NET "cntrl0_ddr_cs_n" LOC = "W25" ; #Bank 7
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#NET "cntrl0_ddr_ras_n" LOC = "W26" ; #Bank 7
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#NET "cntrl0_ddr_cas_n" LOC = "W21" ; #Bank 7
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#NET "cntrl0_ddr_we_n" LOC = "W22" ; #Bank 7
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#NET "cntrl0_ddr_dm[0]" LOC = "F17" ; #Bank 5
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#NET "cntrl0_ddr_dm[1]" LOC = "E21" ; #Bank 5
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#NET "cntrl0_ddr_dm[2]" LOC = "G19" ; #Bank 5
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#NET "cntrl0_ddr_dm[3]" LOC = "H20" ; #Bank 5
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##NET "sys_clk_p" LOC = "B15" ; #Bank 3
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##NET "sys_clk_n" LOC = "B14" ; #Bank 3
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##NET "clk200_p" LOC = "A12" ; #Bank 3
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##NET "clk200_n" LOC = "A11" ; #Bank 3
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##NET "init_done" LOC = "W23" ; #Bank 7
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#NET "FPGA_reset" LOC = "W20" ; #Bank 7
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#NET "cntrl0_ddr_dqs[0]" LOC = "A24" ; #Bank 5
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#NET "cntrl0_ddr_dqs[1]" LOC = "G18" ; #Bank 5
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#NET "cntrl0_ddr_dqs[2]" LOC = "F24" ; #Bank 5
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#NET "cntrl0_ddr_dqs[3]" LOC = "D26" ; #Bank 5
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#NET "cntrl0_ddr_ck[0]" LOC = "H22" ; #Bank 5
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#NET "cntrl0_ddr_ck_n[0]" LOC = "H21" ; #Bank 5
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#NET "cntrl0_ddr_ck[1]" LOC = "E25" ; #Bank 5
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#NET "cntrl0_ddr_ck_n[1]" LOC = "E24" ; #Bank 5
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NET "cntrl0_DDR_DQ[0]" LOC = "H20" ;
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NET "cntrl0_DDR_DQ[1]" LOC = "E23" ;
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NET "cntrl0_DDR_DQ[2]" LOC = "H26" ;
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NET "cntrl0_DDR_DQ[3]" LOC = "H22" ;
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NET "cntrl0_DDR_DQ[4]" LOC = "E25" ;
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NET "cntrl0_DDR_DQ[5]" LOC = "E26" ;
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NET "cntrl0_DDR_DQ[6]" LOC = "F26" ;
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NET "cntrl0_DDR_DQ[7]" LOC = "E24" ;
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NET "cntrl0_DDR_DQ[8]" LOC = "E20" ;
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NET "cntrl0_DDR_DQ[9]" LOC = "A22" ;
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NET "cntrl0_DDR_DQ[10]" LOC = "C23" ;
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NET "cntrl0_DDR_DQ[11]" LOC = "C24" ;
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NET "cntrl0_DDR_DQ[12]" LOC = "A20" ;
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NET "cntrl0_DDR_DQ[13]" LOC = "A21" ;
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NET "cntrl0_DDR_DQ[14]" LOC = "D24" ;
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NET "cntrl0_DDR_DQ[15]" LOC = "E18" ;
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NET "cntrl0_DDR_DQ[16]" LOC = "F18" ;
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NET "cntrl0_DDR_DQ[17]" LOC = "A19" ;
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NET "cntrl0_DDR_DQ[18]" LOC = "F19" ;
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NET "cntrl0_DDR_DQ[19]" LOC = "B23" ;
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NET "cntrl0_DDR_DQ[20]" LOC = "E21" ;
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NET "cntrl0_DDR_DQ[21]" LOC = "D22" ;
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NET "cntrl0_DDR_DQ[22]" LOC = "D23" ;
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NET "cntrl0_DDR_DQ[23]" LOC = "B24" ;
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NET "cntrl0_DDR_DQ[24]" LOC = "E22" ;
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NET "cntrl0_DDR_DQ[25]" LOC = "F20" ;
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NET "cntrl0_DDR_DQ[26]" LOC = "H23" ;
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NET "cntrl0_DDR_DQ[27]" LOC = "G25" ;
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NET "cntrl0_DDR_DQ[28]" LOC = "G26" ;
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NET "cntrl0_DDR_DQ[29]" LOC = "H25" ;
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NET "cntrl0_DDR_DQ[30]" LOC = "H24" ;
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NET "cntrl0_DDR_DQ[31]" LOC = "H21" ;
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NET "cntrl0_DDR_A[0]" LOC = "C26" ;
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NET "cntrl0_DDR_A[1]" LOC = "E17" ;
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NET "cntrl0_DDR_A[2]" LOC = "D18" ;
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NET "cntrl0_DDR_A[3]" LOC = "C19" ;
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NET "cntrl0_DDR_A[4]" LOC = "F17" ;
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NET "cntrl0_DDR_A[5]" LOC = "B18" ;
|
| 243 |
|
|
NET "cntrl0_DDR_A[6]" LOC = "B20" ;
|
| 244 |
|
|
NET "cntrl0_DDR_A[7]" LOC = "C20" ;
|
| 245 |
|
|
NET "cntrl0_DDR_A[8]" LOC = "D20" ;
|
| 246 |
|
|
NET "cntrl0_DDR_A[9]" LOC = "C21" ;
|
| 247 |
|
|
NET "cntrl0_DDR_A[10]" LOC = "A18" ;
|
| 248 |
|
|
NET "cntrl0_DDR_A[11]" LOC = "B21" ;
|
| 249 |
|
|
NET "cntrl0_DDR_A[12]" LOC = "A24" ;
|
| 250 |
|
|
|
| 251 |
|
|
NET "cntrl0_DDR_BA[0]" LOC = "B12" ;
|
| 252 |
|
|
NET "cntrl0_DDR_BA[1]" LOC = "A16" ;
|
| 253 |
|
|
|
| 254 |
|
|
NET "cntrl0_DDR_CKE" LOC = "G22" ;
|
| 255 |
|
|
NET "cntrl0_DDR_CS_N" LOC = "G21" ;
|
| 256 |
|
|
NET "cntrl0_DDR_RAS_N" LOC = "F24" ;
|
| 257 |
|
|
NET "cntrl0_DDR_CAS_N" LOC = "F23" ;
|
| 258 |
|
|
NET "cntrl0_DDR_WE_N" LOC = "A23" ;
|
| 259 |
|
|
|
| 260 |
|
|
NET "cntrl0_DDR_CK_N[0]" LOC = "B10" ;
|
| 261 |
|
|
NET "cntrl0_DDR_CK[0]" LOC = "A10" ;
|
| 262 |
|
|
|
| 263 |
|
|
NET "cntrl0_DDR_DM[0]" LOC = "G19" ;
|
| 264 |
|
|
NET "cntrl0_DDR_DM[1]" LOC = "G24" ;
|
| 265 |
|
|
NET "cntrl0_DDR_DM[2]" LOC = "G20" ;
|
| 266 |
|
|
NET "cntrl0_DDR_DM[3]" LOC = "C22" ;
|
| 267 |
|
|
|
| 268 |
|
|
NET "cntrl0_DDR_DQS[0]" LOC = "D25" ;
|
| 269 |
|
|
NET "cntrl0_DDR_DQS[1]" LOC = "G18" ;
|
| 270 |
|
|
NET "cntrl0_DDR_DQS[2]" LOC = "G17" ;
|
| 271 |
|
|
NET "cntrl0_DDR_DQS[3]" LOC = "D26" ;
|
| 272 |
|
|
|
| 273 |
|
|
NET "FPGA_clk_100_top" LOC = "AE14"; #100 MHz Clock for IDELAYs
|
| 274 |
|
|
|
| 275 |
|
|
|
| 276 |
|
|
###############################################
|
| 277 |
|
|
#NET "button" LOC = "F10";
|
| 278 |
|
|
|
| 279 |
|
|
#NET "cntrl0_DDR_DQ[0]" LOC = "H20" ;
|
| 280 |
|
|
#NET "cntrl0_DDR_DQ[1]" LOC = "E23" ;
|
| 281 |
|
|
#NET "cntrl0_DDR_DQ[2]" LOC = "H26" ;
|
| 282 |
|
|
#NET "cntrl0_DDR_DQ[3]" LOC = "H22" ;
|
| 283 |
|
|
#NET "cntrl0_DDR_DQ[4]" LOC = "E25" ;
|
| 284 |
|
|
#NET "cntrl0_DDR_DQ[5]" LOC = "E26" ;
|
| 285 |
|
|
#NET "cntrl0_DDR_DQ[6]" LOC = "F26" ;
|
| 286 |
|
|
#NET "cntrl0_DDR_DQ[7]" LOC = "E24" ;
|
| 287 |
|
|
#NET "cntrl0_DDR_DQ[8]" LOC = "E20" ;
|
| 288 |
|
|
#NET "cntrl0_DDR_DQ[9]" LOC = "A22" ;
|
| 289 |
|
|
#NET "cntrl0_DDR_DQ[10]" LOC = "C23" ;
|
| 290 |
|
|
#NET "cntrl0_DDR_DQ[11]" LOC = "C24" ;
|
| 291 |
|
|
#NET "cntrl0_DDR_DQ[12]" LOC = "A20" ;
|
| 292 |
|
|
#NET "cntrl0_DDR_DQ[13]" LOC = "A21" ;
|
| 293 |
|
|
#NET "cntrl0_DDR_DQ[14]" LOC = "D24" ;
|
| 294 |
|
|
#NET "cntrl0_DDR_DQ[15]" LOC = "E18" ;
|
| 295 |
|
|
#NET "cntrl0_DDR_DQ[16]" LOC = "F18" ;
|
| 296 |
|
|
#NET "cntrl0_DDR_DQ[17]" LOC = "A19" ;
|
| 297 |
|
|
#NET "cntrl0_DDR_DQ[18]" LOC = "F19" ;
|
| 298 |
|
|
#NET "cntrl0_DDR_DQ[19]" LOC = "B23" ;
|
| 299 |
|
|
#NET "cntrl0_DDR_DQ[20]" LOC = "E21" ;
|
| 300 |
|
|
#NET "cntrl0_DDR_DQ[21]" LOC = "D22" ;
|
| 301 |
|
|
#NET "cntrl0_DDR_DQ[22]" LOC = "D23" ;
|
| 302 |
|
|
#NET "cntrl0_DDR_DQ[23]" LOC = "B24" ;
|
| 303 |
|
|
#NET "cntrl0_DDR_DQ[24]" LOC = "E22" ;
|
| 304 |
|
|
#NET "cntrl0_DDR_DQ[25]" LOC = "F20" ;
|
| 305 |
|
|
#NET "cntrl0_DDR_DQ[26]" LOC = "H23" ;
|
| 306 |
|
|
#NET "cntrl0_DDR_DQ[27]" LOC = "G25" ;
|
| 307 |
|
|
#NET "cntrl0_DDR_DQ[28]" LOC = "G26" ;
|
| 308 |
|
|
#NET "cntrl0_DDR_DQ[29]" LOC = "H25" ;
|
| 309 |
|
|
#NET "cntrl0_DDR_DQ[30]" LOC = "H24" ;
|
| 310 |
|
|
#NET "cntrl0_DDR_DQ[31]" LOC = "H21" ;
|
| 311 |
|
|
#
|
| 312 |
|
|
#NET "cntrl0_DDR_A[0]" LOC = "C26" ;
|
| 313 |
|
|
#NET "cntrl0_DDR_A[1]" LOC = "E17" ;
|
| 314 |
|
|
#NET "cntrl0_DDR_A[2]" LOC = "D18" ;
|
| 315 |
|
|
#NET "cntrl0_DDR_A[3]" LOC = "C19" ;
|
| 316 |
|
|
#NET "cntrl0_DDR_A[4]" LOC = "F17" ;
|
| 317 |
|
|
#NET "cntrl0_DDR_A[5]" LOC = "B18" ;
|
| 318 |
|
|
#NET "cntrl0_DDR_A[6]" LOC = "B20" ;
|
| 319 |
|
|
#NET "cntrl0_DDR_A[7]" LOC = "C20" ;
|
| 320 |
|
|
#NET "cntrl0_DDR_A[8]" LOC = "D20" ;
|
| 321 |
|
|
#NET "cntrl0_DDR_A[9]" LOC = "C21" ;
|
| 322 |
|
|
#NET "cntrl0_DDR_A[10]" LOC = "A18" ;
|
| 323 |
|
|
#NET "cntrl0_DDR_A[11]" LOC = "B21" ;
|
| 324 |
|
|
#NET "cntrl0_DDR_A[12]" LOC = "A24" ;
|
| 325 |
|
|
#
|
| 326 |
|
|
#NET "cntrl0_DDR_BA[0]" LOC = "B12" ;
|
| 327 |
|
|
#NET "cntrl0_DDR_BA[1]" LOC = "A16" ;
|
| 328 |
|
|
#
|
| 329 |
|
|
#NET "cntrl0_DDR_CKE" LOC = "G22" ;
|
| 330 |
|
|
#NET "cntrl0_DDR_CS_N" LOC = "G21" ;
|
| 331 |
|
|
#NET "cntrl0_DDR_RAS_N" LOC = "F24" ;
|
| 332 |
|
|
#NET "cntrl0_DDR_CAS_N" LOC = "F23" ;
|
| 333 |
|
|
#NET "cntrl0_DDR_WE_N" LOC = "A23" ;
|
| 334 |
|
|
#
|
| 335 |
|
|
#NET "cntrl0_DDR_CK_N[0]" LOC = "B10" ;
|
| 336 |
|
|
#NET "cntrl0_DDR_CK[0]" LOC = "A10" ;
|
| 337 |
|
|
#
|
| 338 |
|
|
#NET "cntrl0_DDR_DM[0]" LOC = "G19" ;
|
| 339 |
|
|
#NET "cntrl0_DDR_DM[1]" LOC = "G24" ;
|
| 340 |
|
|
#NET "cntrl0_DDR_DM[2]" LOC = "G20" ;
|
| 341 |
|
|
#NET "cntrl0_DDR_DM[3]" LOC = "C22" ;
|
| 342 |
|
|
#
|
| 343 |
|
|
#NET "cntrl0_DDR_DQS[0]" LOC = "D25" ;
|
| 344 |
|
|
#NET "cntrl0_DDR_DQS[1]" LOC = "G18" ;
|
| 345 |
|
|
#NET "cntrl0_DDR_DQS[2]" LOC = "G17" ;
|
| 346 |
|
|
#NET "cntrl0_DDR_DQS[3]" LOC = "D26" ;
|
| 347 |
|
|
#
|
| 348 |
|
|
#NET "cntrl0_ERROR" LOC = "V6" ; #Error - Data Mismatch --> Error1 LED ML402 (active high)
|
| 349 |
|
|
#NET "CLK_100" LOC = "AE14"; #100 MHz Clock for IDELAYs
|
| 350 |
|
|
#NET "SYS_CLK_P" LOC = "C13"; #Variable SYS_CLK
|
| 351 |
|
|
#NET "SYS_CLK_N" LOC = "C12"; #Variable SYS_CLK
|
| 352 |
|
|
#NET "SYS_RESET_IN" LOC = "D6"; #Center Push Button ML402 (active high)
|
| 353 |
|
|
#
|
| 354 |
|
|
#
|
| 355 |
|
|
#NET rx LOC = W2;
|
| 356 |
|
|
#NET tx LOC = W1;
|
| 357 |
|
|
|
| 358 |
|
|
#Net FIFO_empty LOC = G5; ##LED_0
|
| 359 |
|
|
#Net read_enable LOC = G6; ##LED
|
| 360 |
|
|
#NET write_enable LOC = A11; ##LED_2
|
| 361 |
|
|
|
| 362 |
|
|
#NET leds<0> LOC = A5; ## | PULLUP;
|
| 363 |
|
|
#NET leds<1> LOC = G5; ## | PULLUP;
|
| 364 |
|
|
#NET leds<2> LOC = G6; ## | PULLUP;
|
| 365 |
|
|
#NET leds<3> LOC = A11; ## | PULLUP;
|
| 366 |
|
|
#NET leds<4> LOC = A12; ## | PULLUP;
|
| 367 |
|
|
#NET leds<5> LOC = E10; ## | PULLUP;
|
| 368 |
|
|
#NET leds<6> LOC = C6; ## | PULLUP;
|
| 369 |
|
|
#NET leds<7> LOC = F9; ## | PULLUP;
|
| 370 |
|
|
#NET leds<8> LOC = E2; ## | PULLUP;
|
| 371 |
|
|
|
| 372 |
|
|
#Net "empac_empty_debug" LOC = A5;
|
| 373 |
|
|
#Net "empac_full_debug" LOC = G5;
|
| 374 |
|
|
#NET rdcount LOC =
|
| 375 |
|
|
#NET wrcount<0> LOC = G6;
|
| 376 |
|
|
#NET wrcount<1> LOC = A11;
|
| 377 |
|
|
#NET wrcount<2> LOC = A12;
|
| 378 |
|
|
#NET wrcount<3> LOC = E10;
|
| 379 |
|
|
#NET wrcount<4> LOC = C6;
|
| 380 |
|
|
#NET wrcount<5> LOC = F9;
|
| 381 |
|
|
#NET wrcount<6> LOC = E2;
|
| 382 |
|
|
|
| 383 |
|
|
|
| 384 |
|
|
##calibration_done : out std_logic;
|
| 385 |
|
|
#NET calibration_done LOC = A5 ;##| PULLUP;
|
| 386 |
|
|
|
| 387 |
|
|
|
| 388 |
|
|
|
| 389 |
|
|
|
| 390 |
|
|
|
| 391 |
|
|
|
| 392 |
|
|
|
| 393 |
|
|
|
| 394 |
|
|
|
| 395 |
|
|
|
| 396 |
|
|
|
| 397 |
|
|
|
| 398 |
|
|
#NET clock TNM_NET = "clock";
|
| 399 |
|
|
#TIMESPEC "TSSYSCLK" = PERIOD "clock" 20 ns HIGH 50%;
|
| 400 |
|
|
#NET clock LOC = AE14;
|
| 401 |
|
|
#NET clock IOSTANDARD = LVCMOS33;
|
| 402 |
|
|
NET phy_clock LOC = B15;
|
| 403 |
|
|
|
| 404 |
|
|
NET rx LOC = W2;
|
| 405 |
|
|
NET rx IOSTANDARD = LVCMOS33;
|
| 406 |
|
|
NET rx TIG;
|
| 407 |
|
|
NET tx LOC = W1;
|
| 408 |
|
|
NET tx IOSTANDARD = LVCMOS33;
|
| 409 |
|
|
NET tx TIG;
|
| 410 |
|
|
|
| 411 |
|
|
#NET WIZ_rx_sdata LOC = W2;
|
| 412 |
|
|
#NET WIZ_rx_sdata IOSTANDARD = LVCMOS33;
|
| 413 |
|
|
#NET WIZ_tx_sdata LOC = W1;
|
| 414 |
|
|
#NET WIZ_tx_sdata IOSTANDARD = LVCMOS33;
|
| 415 |
|
|
|
| 416 |
|
|
|
| 417 |
|
|
NET FPGA_RESET LOC = D6;
|
| 418 |
|
|
#NET leds<0> LOC = A5;# GPIO SOUTH
|
| 419 |
|
|
#NET leds<1> LOC = G5;# GPIO 0
|
| 420 |
|
|
#NET leds<2> LOC = G6;# GPIO 1
|
| 421 |
|
|
#NET leds<3> LOC = A11;# GPIO 2
|
| 422 |
|
|
#NET leds<4> LOC = A12;# GPIO 3
|
| 423 |
|
|
#NET leds<5> LOC = E10;# GPIO E
|
| 424 |
|
|
#NET leds<6> LOC = C6;# GPIO C
|
| 425 |
|
|
#NET leds<7> LOC = F9;# GPIO W
|
| 426 |
|
|
#NET leds<8> LOC = E2;# GPIO N
|
| 427 |
|
|
NET phy_data_in<0> LOC = F1;
|
| 428 |
|
|
NET phy_data_in<1> LOC = E1;
|
| 429 |
|
|
NET phy_data_in<2> LOC = D4;
|
| 430 |
|
|
NET phy_data_in<3> LOC = C4;
|
| 431 |
|
|
NET phy_data_valid_in LOC = A9;
|
| 432 |
|
|
#NET WIZ_phy_data_in<4> LOC = B4;
|
| 433 |
|
|
#NET WIZ_phy_data_in<5> LOC = A4;
|
| 434 |
|
|
#NET WIZ_phy_data_in<6> LOC = B3;
|
| 435 |
|
|
#NET WIZ_phy_data_in<7> LOC = A3;
|
| 436 |
|
|
#NET phy_data_in LOC = A9;
|
| 437 |
|
|
NET phy_reset LOC = D10;
|
| 438 |
|
|
#NET leds<0> LOC = A5;# GPIO SOUTH
|
| 439 |
|
|
#NET leds<1> LOC = G5;# GPIO 0
|
| 440 |
|
|
#NET leds<2> LOC = G6;# GPIO 1
|
| 441 |
|
|
#NET leds<3> LOC = A11;# GPIO 2
|
| 442 |
|
|
#NET leds<4> LOC = A12;# GPIO 3
|
| 443 |
|
|
#NET leds<5> LOC = E10;# GPIO E
|
| 444 |
|
|
#NET leds<6> LOC = C6;# GPIO C
|
| 445 |
|
|
#NET leds<7> LOC = F9;# GPIO W
|
| 446 |
|
|
#NET leds<8> LOC = E2;# GPIO N
|
| 447 |
|
|
|
| 448 |
|
|
NET phy_reset TIG;
|
| 449 |
|
|
|
| 450 |
|
|
#NET "phy_clock" TNM_NET = "RXCLK_GRP";
|
| 451 |
|
|
#TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;
|
| 452 |
|
|
|
| 453 |
|
|
#NET "phy_data_in<0>" IOBDELAY = NONE;
|
| 454 |
|
|
#NET "phy_data_in<1>" IOBDELAY = NONE;
|
| 455 |
|
|
#NET "phy_data_in<2>" IOBDELAY = NONE;
|
| 456 |
|
|
#NET "phy_data_in<3>" IOBDELAY = NONE;
|
| 457 |
|
|
#NET "phy_data_valid_in" IOBDELAY = NONE;
|
| 458 |
|
|
|
| 459 |
|
|
#NET "wrcount<0>" IOBDELAY = NONE;
|
| 460 |
|
|
#NET "wrcount<1>" IOBDELAY = NONE;
|
| 461 |
|
|
#NET "wrcount<2>" IOBDELAY = NONE;
|
| 462 |
|
|
#NET "wrcount<3>" IOBDELAY = NONE;
|
| 463 |
|
|
#NET "wrcount<4>" IOBDELAY = NONE;
|
| 464 |
|
|
#NET "wrcount<5>" IOBDELAY = NONE;
|
| 465 |
|
|
#NET "wrcount<6>" IOBDELAY = NONE;
|
| 466 |
|
|
|
| 467 |
|
|
#TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "clock" TIG;
|
| 468 |
|
|
#TIMESPEC "TS_OPB_PHYRX" = FROM "clock" TO "RXCLK_GRP" TIG;
|
| 469 |
|
|
|
| 470 |
|
|
#NET "leds<0>" PULLDOWN;
|
| 471 |
|
|
#NET "leds<0>" TIG;
|
| 472 |
|
|
#NET "leds<0>" SLEW = SLOW;
|
| 473 |
|
|
#NET "leds<0>" DRIVE = 2;
|
| 474 |
|
|
#
|
| 475 |
|
|
##NET "leds<1>" PULLDOWN;
|
| 476 |
|
|
#NET "leds<1>" TIG;
|
| 477 |
|
|
#NET "leds<1>" SLEW = SLOW;
|
| 478 |
|
|
#NET "leds<1>" DRIVE = 2;
|
| 479 |
|
|
#
|
| 480 |
|
|
##NET "leds<2>" PULLDOWN;
|
| 481 |
|
|
#NET "leds<2>" TIG;
|
| 482 |
|
|
#NET "leds<2>" SLEW = SLOW;
|
| 483 |
|
|
#NET "leds<2>" DRIVE = 2;
|
| 484 |
|
|
#
|
| 485 |
|
|
##NET "leds<3>" PULLDOWN;
|
| 486 |
|
|
#NET "leds<3>" TIG;
|
| 487 |
|
|
#NET "leds<3>" SLEW = SLOW;
|
| 488 |
|
|
#NET "leds<3>" DRIVE = 2;
|
| 489 |
|
|
#
|
| 490 |
|
|
##NET "leds<4>" PULLDOWN;
|
| 491 |
|
|
#NET "leds<4>" TIG;
|
| 492 |
|
|
#NET "leds<4>" SLEW = SLOW;
|
| 493 |
|
|
#NET "leds<4>" DRIVE = 2;
|
| 494 |
|
|
#
|
| 495 |
|
|
##NET "leds<5>" PULLDOWN;
|
| 496 |
|
|
#NET "leds<5>" TIG;
|
| 497 |
|
|
#NET "leds<5>" SLEW = SLOW;
|
| 498 |
|
|
#NET "leds<5>" DRIVE = 2;
|
| 499 |
|
|
#
|
| 500 |
|
|
##NET "leds<6>" PULLDOWN;
|
| 501 |
|
|
#NET "leds<6>" TIG;
|
| 502 |
|
|
#NET "leds<6>" SLEW = SLOW;
|
| 503 |
|
|
#NET "leds<6>" DRIVE = 2;
|
| 504 |
|
|
#
|
| 505 |
|
|
##NET "leds<7>" PULLDOWN;
|
| 506 |
|
|
#NET "leds<7>" TIG;
|
| 507 |
|
|
#NET "leds<7>" SLEW = SLOW;
|
| 508 |
|
|
#NET "leds<7>" DRIVE = 2;
|
| 509 |
|
|
|
| 510 |
|
|
### CONSTRAINTS BELOW NOT REALLY BEING USED ##
|
| 511 |
|
|
#NET leds_out<0> LOC = A5;# GPIO SOUTH #E2;
|
| 512 |
|
|
#NET leds_out<1> LOC = G5;# GPIO 0 #F9;
|
| 513 |
|
|
#NET leds_out<2> LOC = G6;# GPIO 1 #C6;
|
| 514 |
|
|
#NET leds_out<3> LOC = A11;# GPIO 2 #E10;
|
| 515 |
|
|
#NET leds_out<4> LOC = A12;# GPIO 3 #A5;
|
| 516 |
|
|
#NET leds_out<5> LOC = E10;# GPIO E
|
| 517 |
|
|
#NET leds_out<6> LOC = C6;# GPIO C
|
| 518 |
|
|
#NET tab_out LOC = F9;# GPIO W
|
| 519 |
|
|
#NET leds<8> LOC = E2;# GPIO
|
| 520 |
|
|
#NET send_packet LOC = C6;
|
| 521 |
|
|
#NET known_addr LOC = F9;
|
| 522 |
|
|
#NET known_addr2 LOC = C6;
|
| 523 |
|
|
#NET known_protocol<0> LOC = A5;
|
| 524 |
|
|
#NET known_protocol<1> LOC = G5;
|
| 525 |
|
|
#NET known_protocol<2> LOC = G6;
|
| 526 |
|
|
#NET known_protocol<3> LOC = A11;
|
| 527 |
|
|
#NET known_protocol<4> LOC = A12;
|
| 528 |
|
|
#NET known_protocol<5> LOC = F9;
|
| 529 |
|
|
#NET known_protocol<6> LOC = C6;
|
| 530 |
|
|
#NET known_protocol<7> LOC = E10;
|
| 531 |
|
|
#NET count<0> LOC = A5;
|
| 532 |
|
|
#NET count<1> LOC = G5;
|
| 533 |
|
|
#NET count<2> LOC = G6;
|
| 534 |
|
|
#NET count<3> LOC = A11;
|
| 535 |
|
|
#NET count<4> LOC = A12;
|
| 536 |
|
|
#NET count<5> LOC = F9;
|
| 537 |
|
|
#NET count<6> LOC = C6;
|
| 538 |
|
|
#NET count<7> LOC = E10;
|
| 539 |
|
|
#NET send_packet LOC = E2;
|
| 540 |
|
|
|
| 541 |
|
|
NET "sram_clk" LOC = "AF7";
|
| 542 |
|
|
|
| 543 |
|
|
NET "sram_feedback_clk" LOC = "AD17";
|
| 544 |
|
|
#
|
| 545 |
|
|
NET "wd" LOC = "C6";
|
| 546 |
|
|
|
| 547 |
|
|
|
| 548 |
|
|
# SRAM
|
| 549 |
|
|
#
|
| 550 |
|
|
NET "sram_addr<0>" LOC = "Y1";
|
| 551 |
|
|
NET "sram_addr<1>" LOC = "Y2";
|
| 552 |
|
|
NET "sram_addr<2>" LOC = "AA1";
|
| 553 |
|
|
NET "sram_addr<3>" LOC = "AB1";
|
| 554 |
|
|
NET "sram_addr<4>" LOC = "AB2";
|
| 555 |
|
|
NET "sram_addr<5>" LOC = "AC1";
|
| 556 |
|
|
NET "sram_addr<6>" LOC = "AC2";
|
| 557 |
|
|
NET "sram_addr<7>" LOC = "AD1";
|
| 558 |
|
|
NET "sram_addr<8>" LOC = "AD2";
|
| 559 |
|
|
NET "sram_addr<9>" LOC = "AE3";
|
| 560 |
|
|
NET "sram_addr<10>" LOC = "AF3";
|
| 561 |
|
|
NET "sram_addr<11>" LOC = "W3";
|
| 562 |
|
|
NET "sram_addr<12>" LOC = "W6";
|
| 563 |
|
|
NET "sram_addr<13>" LOC = "W5";
|
| 564 |
|
|
NET "sram_addr<14>" LOC = "AA3";
|
| 565 |
|
|
NET "sram_addr<15>" LOC = "AA4";
|
| 566 |
|
|
NET "sram_addr<16>" LOC = "AB3";
|
| 567 |
|
|
NET "sram_addr<17>" LOC = "AB4";
|
| 568 |
|
|
|
| 569 |
|
|
NET "sram_addr<18>" LOC = "AC4";
|
| 570 |
|
|
NET "sram_addr<19>" LOC = "AB5";
|
| 571 |
|
|
NET "sram_addr<20>" LOC = "AC5";
|
| 572 |
|
|
NET "sram_addr<21>" LOC = "T19";
|
| 573 |
|
|
NET "sram_addr<22>" LOC = "U20";
|
| 574 |
|
|
#
|
| 575 |
|
|
NET "sram_we_n" LOC = "AB6";
|
| 576 |
|
|
NET "sram_oe_n" LOC = "AC6";
|
| 577 |
|
|
#
|
| 578 |
|
|
NET "sram_data<0>" LOC = "AD13";
|
| 579 |
|
|
NET "sram_data<1>" LOC = "AC13";
|
| 580 |
|
|
NET "sram_data<2>" LOC = "AC15";
|
| 581 |
|
|
NET "sram_data<3>" LOC = "AC16";
|
| 582 |
|
|
NET "sram_data<4>" LOC = "AA11";
|
| 583 |
|
|
NET "sram_data<5>" LOC = "AA12";
|
| 584 |
|
|
NET "sram_data<6>" LOC = "AD14";
|
| 585 |
|
|
NET "sram_data<7>" LOC = "AC14";
|
| 586 |
|
|
NET "sram_data<8>" LOC = "AA13";
|
| 587 |
|
|
NET "sram_data<9>" LOC = "AB13";
|
| 588 |
|
|
NET "sram_data<10>" LOC = "AA15";
|
| 589 |
|
|
NET "sram_data<11>" LOC = "AA16";
|
| 590 |
|
|
NET "sram_data<12>" LOC = "AC11";
|
| 591 |
|
|
NET "sram_data<13>" LOC = "AC12";
|
| 592 |
|
|
NET "sram_data<14>" LOC = "AB14";
|
| 593 |
|
|
NET "sram_data<15>" LOC = "AA14";
|
| 594 |
|
|
#
|
| 595 |
|
|
|
| 596 |
|
|
NET "sram_bw0" LOC = "Y6";
|
| 597 |
|
|
NET "sram_bw1" LOC = "Y5";
|
| 598 |
|
|
#
|
| 599 |
|
|
NET "sram_data<16>" LOC = "D12";
|
| 600 |
|
|
NET "sram_data<17>" LOC = "E13";
|
| 601 |
|
|
NET "sram_data<18>" LOC = "C16";
|
| 602 |
|
|
NET "sram_data<19>" LOC = "D16";
|
| 603 |
|
|
NET "sram_data<20>" LOC = "D11";
|
| 604 |
|
|
NET "sram_data<21>" LOC = "C11";
|
| 605 |
|
|
NET "sram_data<22>" LOC = "E14";
|
| 606 |
|
|
NET "sram_data<23>" LOC = "D15";
|
| 607 |
|
|
NET "sram_data<24>" LOC = "D13";
|
| 608 |
|
|
NET "sram_data<25>" LOC = "D14";
|
| 609 |
|
|
NET "sram_data<26>" LOC = "F15";
|
| 610 |
|
|
NET "sram_data<27>" LOC = "F16";
|
| 611 |
|
|
NET "sram_data<28>" LOC = "F11";
|
| 612 |
|
|
NET "sram_data<29>" LOC = "F12";
|
| 613 |
|
|
NET "sram_data<30>" LOC = "F13";
|
| 614 |
|
|
NET "sram_data<31>" LOC = "F14";
|
| 615 |
|
|
#
|
| 616 |
|
|
|
| 617 |
|
|
NET "sram_bw2" LOC = "Y4";
|
| 618 |
|
|
NET "sram_bw3" LOC = "Y3";
|
| 619 |
|
|
#
|
| 620 |
|
|
#
|
| 621 |
|
|
NET "sram_adv_ld_n" LOC = "W4";
|
| 622 |
|
|
NET "sram_mode" LOC = "V26";
|
| 623 |
|
|
NET "sram_cen" LOC = "V7";
|
| 624 |
|
|
|
| 625 |
|
|
#
|
| 626 |
|
|
NET sram_clk IOSTANDARD = LVCMOS33;
|
| 627 |
|
|
NET sram_clk DRIVE = 16;
|
| 628 |
|
|
NET sram_clk SLEW = FAST;
|
| 629 |
|
|
|
| 630 |
|
|
NET sram_feedback_clk IOSTANDARD = LVCMOS25;
|
| 631 |
|
|
NET sram_feedback_clk DRIVE = 16;
|
| 632 |
|
|
NET sram_feedback_clk SLEW = FAST;
|
| 633 |
|
|
|
| 634 |
|
|
NET sram_mode IOSTANDARD = LVDCI_33;
|
| 635 |
|
|
NET sram_mode SLEW = FAST;
|
| 636 |
|
|
NET sram_mode DRIVE = 8;
|
| 637 |
|
|
|
| 638 |
|
|
NET sram_addr<0> IOSTANDARD = LVDCI_33;
|
| 639 |
|
|
NET sram_addr<0> SLEW = FAST;
|
| 640 |
|
|
NET sram_addr<0> DRIVE = 8;
|
| 641 |
|
|
|
| 642 |
|
|
NET sram_addr<1> IOSTANDARD = LVDCI_33;
|
| 643 |
|
|
NET sram_addr<1> SLEW = FAST;
|
| 644 |
|
|
NET sram_addr<1> DRIVE = 8;
|
| 645 |
|
|
|
| 646 |
|
|
NET sram_addr<2> IOSTANDARD = LVDCI_33;
|
| 647 |
|
|
NET sram_addr<2> SLEW = FAST;
|
| 648 |
|
|
NET sram_addr<2> DRIVE = 8;
|
| 649 |
|
|
|
| 650 |
|
|
NET sram_addr<3> IOSTANDARD = LVDCI_33;
|
| 651 |
|
|
NET sram_addr<3> SLEW = FAST;
|
| 652 |
|
|
NET sram_addr<3> DRIVE = 8;
|
| 653 |
|
|
|
| 654 |
|
|
NET sram_addr<4> IOSTANDARD = LVDCI_33;
|
| 655 |
|
|
NET sram_addr<4> SLEW = FAST;
|
| 656 |
|
|
NET sram_addr<4> DRIVE = 8;
|
| 657 |
|
|
|
| 658 |
|
|
NET sram_addr<5> IOSTANDARD = LVDCI_33;
|
| 659 |
|
|
NET sram_addr<5> SLEW = FAST;
|
| 660 |
|
|
NET sram_addr<5> DRIVE = 8;
|
| 661 |
|
|
|
| 662 |
|
|
NET sram_addr<6> IOSTANDARD = LVDCI_33;
|
| 663 |
|
|
NET sram_addr<6> SLEW = FAST;
|
| 664 |
|
|
NET sram_addr<6> DRIVE = 8;
|
| 665 |
|
|
|
| 666 |
|
|
NET sram_addr<7> IOSTANDARD = LVDCI_33;
|
| 667 |
|
|
NET sram_addr<7> SLEW = FAST;
|
| 668 |
|
|
NET sram_addr<7> DRIVE = 8;
|
| 669 |
|
|
|
| 670 |
|
|
NET sram_addr<8> IOSTANDARD = LVDCI_33;
|
| 671 |
|
|
NET sram_addr<8> SLEW = FAST;
|
| 672 |
|
|
NET sram_addr<8> DRIVE = 8;
|
| 673 |
|
|
|
| 674 |
|
|
NET sram_addr<9> IOSTANDARD = LVDCI_33;
|
| 675 |
|
|
NET sram_addr<9> SLEW = FAST;
|
| 676 |
|
|
NET sram_addr<9> DRIVE = 8;
|
| 677 |
|
|
|
| 678 |
|
|
NET sram_addr<10> IOSTANDARD = LVDCI_33;
|
| 679 |
|
|
NET sram_addr<10> SLEW = FAST;
|
| 680 |
|
|
NET sram_addr<10> DRIVE = 8;
|
| 681 |
|
|
|
| 682 |
|
|
NET sram_addr<11> IOSTANDARD = LVDCI_33;
|
| 683 |
|
|
NET sram_addr<11> SLEW = FAST;
|
| 684 |
|
|
NET sram_addr<11> DRIVE = 8;
|
| 685 |
|
|
|
| 686 |
|
|
NET sram_addr<12> IOSTANDARD = LVDCI_33;
|
| 687 |
|
|
NET sram_addr<12> SLEW = FAST;
|
| 688 |
|
|
NET sram_addr<12> DRIVE = 8;
|
| 689 |
|
|
|
| 690 |
|
|
NET sram_addr<13> IOSTANDARD = LVDCI_33;
|
| 691 |
|
|
NET sram_addr<13> SLEW = FAST;
|
| 692 |
|
|
NET sram_addr<13> DRIVE = 8;
|
| 693 |
|
|
|
| 694 |
|
|
NET sram_addr<14> IOSTANDARD = LVDCI_33;
|
| 695 |
|
|
NET sram_addr<14> SLEW = FAST;
|
| 696 |
|
|
NET sram_addr<14> DRIVE = 8;
|
| 697 |
|
|
|
| 698 |
|
|
NET sram_addr<15> IOSTANDARD = LVDCI_33;
|
| 699 |
|
|
NET sram_addr<15> SLEW = FAST;
|
| 700 |
|
|
NET sram_addr<15> DRIVE = 8;
|
| 701 |
|
|
|
| 702 |
|
|
NET sram_addr<16> IOSTANDARD = LVDCI_33;
|
| 703 |
|
|
NET sram_addr<16> SLEW = FAST;
|
| 704 |
|
|
NET sram_addr<16> DRIVE = 8;
|
| 705 |
|
|
|
| 706 |
|
|
NET sram_addr<17> IOSTANDARD = LVDCI_33;
|
| 707 |
|
|
NET sram_addr<17> SLEW = FAST;
|
| 708 |
|
|
NET sram_addr<17> DRIVE = 8;
|
| 709 |
|
|
|
| 710 |
|
|
NET sram_addr<18> IOSTANDARD = LVDCI_33;
|
| 711 |
|
|
NET sram_addr<18> SLEW = FAST;
|
| 712 |
|
|
NET sram_addr<18> DRIVE = 8;
|
| 713 |
|
|
|
| 714 |
|
|
NET sram_addr<19> IOSTANDARD = LVDCI_33;
|
| 715 |
|
|
NET sram_addr<19> SLEW = FAST;
|
| 716 |
|
|
NET sram_addr<19> DRIVE = 8;
|
| 717 |
|
|
|
| 718 |
|
|
NET sram_addr<20> IOSTANDARD = LVDCI_33;
|
| 719 |
|
|
NET sram_addr<20> SLEW = FAST;
|
| 720 |
|
|
NET sram_addr<20> DRIVE = 8;
|
| 721 |
|
|
|
| 722 |
|
|
NET sram_addr<21> IOSTANDARD = LVDCI_33;
|
| 723 |
|
|
NET sram_addr<21> SLEW = FAST;
|
| 724 |
|
|
NET sram_addr<21> DRIVE = 8;
|
| 725 |
|
|
|
| 726 |
|
|
NET sram_addr<22> IOSTANDARD = LVDCI_33;
|
| 727 |
|
|
NET sram_addr<22> SLEW = FAST;
|
| 728 |
|
|
NET sram_addr<22> DRIVE = 8;
|
| 729 |
|
|
|
| 730 |
|
|
NET sram_data<0> IOSTANDARD = LVCMOS33;
|
| 731 |
|
|
NET sram_data<0> DRIVE = 12;
|
| 732 |
|
|
NET sram_data<0> SLEW = FAST;
|
| 733 |
|
|
NET sram_data<0> PULLDOWN;
|
| 734 |
|
|
|
| 735 |
|
|
NET sram_data<1> IOSTANDARD = LVCMOS33;
|
| 736 |
|
|
NET sram_data<1> DRIVE = 12;
|
| 737 |
|
|
NET sram_data<1> SLEW = FAST;
|
| 738 |
|
|
NET sram_data<1> PULLDOWN;
|
| 739 |
|
|
|
| 740 |
|
|
NET sram_data<2> IOSTANDARD = LVCMOS33;
|
| 741 |
|
|
NET sram_data<2> DRIVE = 12;
|
| 742 |
|
|
NET sram_data<2> SLEW = FAST;
|
| 743 |
|
|
NET sram_data<2> PULLDOWN;
|
| 744 |
|
|
|
| 745 |
|
|
NET sram_data<3> IOSTANDARD = LVCMOS33;
|
| 746 |
|
|
NET sram_data<3> DRIVE = 12;
|
| 747 |
|
|
NET sram_data<3> SLEW = FAST;
|
| 748 |
|
|
NET sram_data<3> PULLDOWN;
|
| 749 |
|
|
|
| 750 |
|
|
NET sram_data<4> IOSTANDARD = LVCMOS33;
|
| 751 |
|
|
NET sram_data<4> DRIVE = 12;
|
| 752 |
|
|
NET sram_data<4> SLEW = FAST;
|
| 753 |
|
|
NET sram_data<4> PULLDOWN;
|
| 754 |
|
|
|
| 755 |
|
|
NET sram_data<5> IOSTANDARD = LVCMOS33;
|
| 756 |
|
|
NET sram_data<5> DRIVE = 12;
|
| 757 |
|
|
NET sram_data<5> SLEW = FAST;
|
| 758 |
|
|
NET sram_data<5> PULLDOWN;
|
| 759 |
|
|
|
| 760 |
|
|
NET sram_data<6> IOSTANDARD = LVCMOS33;
|
| 761 |
|
|
NET sram_data<6> DRIVE = 12;
|
| 762 |
|
|
NET sram_data<6> SLEW = FAST;
|
| 763 |
|
|
NET sram_data<6> PULLDOWN;
|
| 764 |
|
|
|
| 765 |
|
|
NET sram_data<7> IOSTANDARD = LVCMOS33;
|
| 766 |
|
|
NET sram_data<7> DRIVE = 12;
|
| 767 |
|
|
NET sram_data<7> SLEW = FAST;
|
| 768 |
|
|
NET sram_data<7> PULLDOWN;
|
| 769 |
|
|
|
| 770 |
|
|
NET sram_data<8> IOSTANDARD = LVCMOS33;
|
| 771 |
|
|
NET sram_data<8> DRIVE = 12;
|
| 772 |
|
|
NET sram_data<8> SLEW = FAST;
|
| 773 |
|
|
NET sram_data<8> PULLDOWN;
|
| 774 |
|
|
|
| 775 |
|
|
NET sram_data<9> IOSTANDARD = LVCMOS33;
|
| 776 |
|
|
NET sram_data<9> DRIVE = 12;
|
| 777 |
|
|
NET sram_data<9> SLEW = FAST;
|
| 778 |
|
|
NET sram_data<9> PULLDOWN;
|
| 779 |
|
|
|
| 780 |
|
|
NET sram_data<10> IOSTANDARD = LVCMOS33;
|
| 781 |
|
|
NET sram_data<10> DRIVE = 12;
|
| 782 |
|
|
NET sram_data<10> SLEW = FAST;
|
| 783 |
|
|
NET sram_data<10> PULLDOWN;
|
| 784 |
|
|
|
| 785 |
|
|
NET sram_data<11> IOSTANDARD = LVCMOS33;
|
| 786 |
|
|
NET sram_data<11> DRIVE = 12;
|
| 787 |
|
|
NET sram_data<11> SLEW = FAST;
|
| 788 |
|
|
NET sram_data<11> PULLDOWN;
|
| 789 |
|
|
|
| 790 |
|
|
NET sram_data<12> IOSTANDARD = LVCMOS33;
|
| 791 |
|
|
NET sram_data<12> DRIVE = 12;
|
| 792 |
|
|
NET sram_data<12> SLEW = FAST;
|
| 793 |
|
|
NET sram_data<12> PULLDOWN;
|
| 794 |
|
|
|
| 795 |
|
|
NET sram_data<13> IOSTANDARD = LVCMOS33;
|
| 796 |
|
|
NET sram_data<13> DRIVE = 12;
|
| 797 |
|
|
NET sram_data<13> SLEW = FAST;
|
| 798 |
|
|
NET sram_data<13> PULLDOWN;
|
| 799 |
|
|
|
| 800 |
|
|
NET sram_data<14> IOSTANDARD = LVCMOS33;
|
| 801 |
|
|
NET sram_data<14> DRIVE = 12;
|
| 802 |
|
|
NET sram_data<14> SLEW = FAST;
|
| 803 |
|
|
NET sram_data<14> PULLDOWN;
|
| 804 |
|
|
|
| 805 |
|
|
NET sram_data<15> IOSTANDARD = LVCMOS33;
|
| 806 |
|
|
NET sram_data<15> DRIVE = 12;
|
| 807 |
|
|
NET sram_data<15> SLEW = FAST;
|
| 808 |
|
|
NET sram_data<15> PULLDOWN;
|
| 809 |
|
|
|
| 810 |
|
|
NET sram_data<16> IOSTANDARD = LVCMOS33;
|
| 811 |
|
|
NET sram_data<16> DRIVE = 12;
|
| 812 |
|
|
NET sram_data<16> SLEW = FAST;
|
| 813 |
|
|
NET sram_data<16> PULLDOWN;
|
| 814 |
|
|
|
| 815 |
|
|
NET sram_data<17> IOSTANDARD = LVCMOS33;
|
| 816 |
|
|
NET sram_data<17> DRIVE = 12;
|
| 817 |
|
|
NET sram_data<17> SLEW = FAST;
|
| 818 |
|
|
NET sram_data<17> PULLDOWN;
|
| 819 |
|
|
|
| 820 |
|
|
NET sram_data<18> IOSTANDARD = LVCMOS33;
|
| 821 |
|
|
NET sram_data<18> DRIVE = 12;
|
| 822 |
|
|
NET sram_data<18> SLEW = FAST;
|
| 823 |
|
|
NET sram_data<18> PULLDOWN;
|
| 824 |
|
|
|
| 825 |
|
|
NET sram_data<19> IOSTANDARD = LVCMOS33;
|
| 826 |
|
|
NET sram_data<19> DRIVE = 12;
|
| 827 |
|
|
NET sram_data<19> SLEW = FAST;
|
| 828 |
|
|
NET sram_data<19> PULLDOWN;
|
| 829 |
|
|
|
| 830 |
|
|
NET sram_data<20> IOSTANDARD = LVCMOS33;
|
| 831 |
|
|
NET sram_data<20> DRIVE = 12;
|
| 832 |
|
|
NET sram_data<20> SLEW = FAST;
|
| 833 |
|
|
NET sram_data<20> PULLDOWN;
|
| 834 |
|
|
|
| 835 |
|
|
NET sram_data<21> IOSTANDARD = LVCMOS33;
|
| 836 |
|
|
NET sram_data<21> DRIVE = 12;
|
| 837 |
|
|
NET sram_data<21> SLEW = FAST;
|
| 838 |
|
|
NET sram_data<21> PULLDOWN;
|
| 839 |
|
|
|
| 840 |
|
|
NET sram_data<22> IOSTANDARD = LVCMOS33;
|
| 841 |
|
|
NET sram_data<22> DRIVE = 12;
|
| 842 |
|
|
NET sram_data<22> SLEW = FAST;
|
| 843 |
|
|
NET sram_data<22> PULLDOWN;
|
| 844 |
|
|
|
| 845 |
|
|
NET sram_data<23> IOSTANDARD = LVCMOS33;
|
| 846 |
|
|
NET sram_data<23> DRIVE = 12;
|
| 847 |
|
|
NET sram_data<23> SLEW = FAST;
|
| 848 |
|
|
NET sram_data<23> PULLDOWN;
|
| 849 |
|
|
|
| 850 |
|
|
NET sram_data<24> IOSTANDARD = LVCMOS33;
|
| 851 |
|
|
NET sram_data<24> DRIVE = 12;
|
| 852 |
|
|
NET sram_data<24> SLEW = FAST;
|
| 853 |
|
|
NET sram_data<24> PULLDOWN;
|
| 854 |
|
|
|
| 855 |
|
|
NET sram_data<25> IOSTANDARD = LVCMOS33;
|
| 856 |
|
|
NET sram_data<25> DRIVE = 12;
|
| 857 |
|
|
NET sram_data<25> SLEW = FAST;
|
| 858 |
|
|
NET sram_data<25> PULLDOWN;
|
| 859 |
|
|
|
| 860 |
|
|
NET sram_data<26> IOSTANDARD = LVCMOS33;
|
| 861 |
|
|
NET sram_data<26> DRIVE = 12;
|
| 862 |
|
|
NET sram_data<26> SLEW = FAST;
|
| 863 |
|
|
NET sram_data<26> PULLDOWN;
|
| 864 |
|
|
|
| 865 |
|
|
NET sram_data<27> IOSTANDARD = LVCMOS33;
|
| 866 |
|
|
NET sram_data<27> DRIVE = 12;
|
| 867 |
|
|
NET sram_data<27> SLEW = FAST;
|
| 868 |
|
|
NET sram_data<27> PULLDOWN;
|
| 869 |
|
|
|
| 870 |
|
|
NET sram_data<28> IOSTANDARD = LVCMOS33;
|
| 871 |
|
|
NET sram_data<28> DRIVE = 12;
|
| 872 |
|
|
NET sram_data<28> SLEW = FAST;
|
| 873 |
|
|
NET sram_data<28> PULLDOWN;
|
| 874 |
|
|
|
| 875 |
|
|
NET sram_data<29> IOSTANDARD = LVCMOS33;
|
| 876 |
|
|
NET sram_data<29> DRIVE = 12;
|
| 877 |
|
|
NET sram_data<29> SLEW = FAST;
|
| 878 |
|
|
NET sram_data<29> PULLDOWN;
|
| 879 |
|
|
|
| 880 |
|
|
NET sram_data<30> IOSTANDARD = LVCMOS33;
|
| 881 |
|
|
NET sram_data<30> DRIVE = 12;
|
| 882 |
|
|
NET sram_data<30> SLEW = FAST;
|
| 883 |
|
|
NET sram_data<30> PULLDOWN;
|
| 884 |
|
|
|
| 885 |
|
|
NET sram_data<31> IOSTANDARD = LVCMOS33;
|
| 886 |
|
|
NET sram_data<31> DRIVE = 12;
|
| 887 |
|
|
NET sram_data<31> SLEW = FAST;
|
| 888 |
|
|
NET sram_data<31> PULLDOWN;
|
| 889 |
|
|
|
| 890 |
|
|
NET sram_oe_n IOSTANDARD = LVDCI_33;
|
| 891 |
|
|
NET sram_oe_n SLEW = FAST;
|
| 892 |
|
|
NET sram_oe_n DRIVE = 8;
|
| 893 |
|
|
|
| 894 |
|
|
NET sram_we_n IOSTANDARD = LVDCI_33;
|
| 895 |
|
|
NET sram_we_n SLEW = FAST;
|
| 896 |
|
|
NET sram_we_n DRIVE = 8;
|
| 897 |
|
|
|
| 898 |
|
|
NET sram_bw1 IOSTANDARD = LVDCI_33;
|
| 899 |
|
|
NET sram_bw1 SLEW = FAST;
|
| 900 |
|
|
NET sram_bw1 DRIVE = 8;
|
| 901 |
|
|
|
| 902 |
|
|
NET sram_bw0 IOSTANDARD = LVDCI_33;
|
| 903 |
|
|
NET sram_bw0 SLEW = FAST;
|
| 904 |
|
|
NET sram_bw2 DRIVE = 8;
|
| 905 |
|
|
|
| 906 |
|
|
NET sram_bw3 IOSTANDARD = LVDCI_33;
|
| 907 |
|
|
NET sram_bw3 SLEW = FAST;
|
| 908 |
|
|
NET sram_bw3 DRIVE = 8;
|
| 909 |
|
|
|
| 910 |
|
|
NET sram_bw2 IOSTANDARD = LVDCI_33;
|
| 911 |
|
|
NET sram_bw2 SLEW = FAST;
|
| 912 |
|
|
NET sram_bw2 DRIVE = 8;
|
| 913 |
|
|
|
| 914 |
|
|
NET sram_cen IOSTANDARD = LVDCI_33;
|
| 915 |
|
|
NET sram_cen SLEW = FAST;
|
| 916 |
|
|
NET sram_cen DRIVE = 8;
|
| 917 |
|
|
|
| 918 |
|
|
NET sram_adv_ld_n IOSTANDARD = LVDCI_33;
|
| 919 |
|
|
NET sram_adv_ld_n SLEW = FAST;
|
| 920 |
|
|
NET sram_adv_ld_n DRIVE = 8;
|
