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1 36 diegovalve
`timescale 1ns / 1ps
2
`include "aDefinitions.v"
3
/**********************************************************************************
4
Theia, Ray Cast Programable graphic Processing Unit.
5
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
6
 
7
This program is free software; you can redistribute it and/or
8
modify it under the terms of the GNU General Public License
9
as published by the Free Software Foundation; either version 2
10
of the License, or (at your option) any later version.
11
 
12
This program is distributed in the hope that it will be useful,
13
but WITHOUT ANY WARRANTY; without even the implied warranty of
14
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
GNU General Public License for more details.
16
 
17
You should have received a copy of the GNU General Public License
18
along with this program; if not, write to the Free Software
19
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
20
 
21
***********************************************************************************/
22
//------------------------------------------------
23
module FFD_POSEDGE_ASYNC_RESET # ( parameter SIZE=`WIDTH )
24
        (
25
        input wire Clock,
26
        input wire Clear,
27
        input wire [SIZE-1:0] D,
28
        output reg [SIZE-1:0] Q
29
        );
30
 
31
  always @(posedge Clock or posedge Clear)
32
    begin
33
           if (Clear)
34
        Q = 0;
35
      else
36
        Q = D;
37
    end
38
endmodule
39
//----------------------------------------------------
40
module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
41
(
42
        input wire                              Clock,
43
        input wire                              Reset,
44
        input wire                              Enable,
45
        input wire [SIZE-1:0]    D,
46
        output reg [SIZE-1:0]    Q
47
);
48
 
49
 
50
always @ (posedge Clock)
51
begin
52
        if ( Reset )
53
                Q <= `WIDTH'b0;
54
        else
55
        begin
56
                if (Enable)
57
                        Q <= D;
58
        end
59
 
60
end//always
61
 
62
endmodule
63
//------------------------------------------------
64
module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
65
(
66
input wire Clock, Reset,
67
input wire [SIZE-1:0] Initial,
68
input wire Enable,
69
output reg [SIZE-1:0] Q
70
);
71
 
72
 
73
  always @(posedge Clock )
74
  begin
75
      if (Reset)
76
        Q = Initial;
77
      else
78
                begin
79
                if (Enable)
80
                        Q = Q + 1;
81
 
82
                end
83
  end
84
 
85
endmodule
86
//------------------------------------------------
87
module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
88
 (
89
 input wire [1:0] Sel,
90
 input wire [SIZE-1:0]I1, I2, I3,
91
 output reg [SIZE-1:0] O1
92
 );
93
 
94
always @( * )
95
 
96
  begin
97
 
98
    case (Sel)
99
 
100
      2'b00: O1 = I1;
101
      2'b01: O1 = I2;
102
                2'b10: O1 = I3;
103
                default: O1 = SIZE-1'b0;
104
 
105
    endcase
106
 
107
  end
108
 
109
endmodule
110
 
111
//------------------------------------------------
112
module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
113
 (
114
 input wire [2:0] Sel,
115
 input wire [SIZE-1:0]I1, I2, I3,
116
 output reg [SIZE-1:0] O1
117
 );
118
 
119
always @( * )
120
 
121
  begin
122
 
123
    case (Sel)
124
 
125
      3'b001: O1 = I1;
126
      3'b010: O1 = I2;
127
                3'b100: O1 = I3;
128
                default: O1 = SIZE-1'b0;
129
 
130
    endcase
131
 
132
  end
133
 
134
endmodule
135
//------------------------------------------------
136
module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
137
( input wire Clock,
138
  input wire Reset,
139
  input wire[SIZE-1:0] Initial,
140
  input wire      Enable,
141
  output wire[SIZE-1:0] O
142
);
143
 
144
reg [SIZE-1:0] tmp;
145
 
146
 
147
  always @(posedge Clock)
148
  begin
149
  if (Reset)
150
                tmp <= Initial;
151
        else
152
        begin
153
                if (Enable)
154
                        tmp <= tmp << 1;
155
        end
156
  end
157
 
158
 
159
    assign O  = tmp;
160
endmodule
161
//------------------------------------------------
162
//------------------------------------------------
163
module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
164
( input wire Clock,
165
  input wire Reset,
166
  input wire[SIZE-1:0] Initial,
167
  input wire      Enable,
168
  output wire[SIZE-1:0] O
169
);
170
 
171
reg [SIZE-1:0] tmp;
172
 
173
 
174
  always @(posedge Clock)
175
  begin
176
  if (Reset || tmp[SIZE-1])
177
                tmp <= Initial;
178
        else
179
        begin
180
                if (Enable)
181
                        tmp <= tmp << 1;
182
        end
183
  end
184
 
185
 
186
    assign O  = tmp;
187
endmodule
188
//-----------------------------------------------------------
189
/*
190
        Sorry forgot how this flop is called.
191
        Any way Truth table is this
192
 
193
        Q       S       Q_next R
194
 
195
 
196
        1       0        1                0
197
        1       1       1                0
198
        X       X       0                 1
199
 
200
        The idea is that it toggles from 0 to 1 when S = 1, but if it
201
        gets another S = 1, it keeps the output to 1.
202
*/
203
module FFToggleOnce_1Bit
204
(
205
        input wire Clock,
206
        input wire Reset,
207
        input wire Enable,
208
        input wire S,
209
        output reg Q
210
 
211
);
212
 
213
 
214
reg Q_next;
215
 
216
always @ (negedge Clock)
217
begin
218
        Q <= Q_next;
219
end
220
 
221
always @ ( posedge Clock )
222
begin
223
        if (Reset)
224
                Q_next <= 0;
225
        else if (Enable)
226
                Q_next <= (S && !Q) || Q;
227
        else
228
                Q_next <= Q;
229
end
230
endmodule
231
 
232
//--------------------------------------------------------------
233
//************************OLD MODS***************************//
234
//************************OLD MODS***************************//
235
//************************OLD MODS***************************//
236
//************************OLD MODS***************************//
237
//-----------------------------------------------------------
238
 
239
/*
240
module UpCounterXXX_16
241
(
242
input wire Clock, Reset,
243
input wire [15:0] Initial,
244
output reg [15:0] Q
245
);
246
 
247
 
248
  always @(posedge Clock )
249
    begin
250
      if (Reset)
251
        Q = Initial;
252
      else
253
        Q = Q + 1'b1;
254
      end
255
 
256
endmodule
257
*/
258
//-----------------------------------------------------------
259
module UpCounter_16E
260
(
261
input wire Clock,
262
input wire Reset,
263
input wire [15:0] Initial,
264
input wire Enable,
265
output wire [15:0] Q
266
);
267
        reg [15:0] Temp;
268
 
269
 
270
  always @(posedge Clock or posedge Reset)
271
  begin
272
      if (Reset)
273
         Temp = Initial;
274
      else
275
                        if (Enable)
276
                                Temp =  Temp + 1'b1;
277
  end
278
        assign Q = Temp;
279
 
280
endmodule
281
//-----------------------------------------------------------
282
module UpCounter_32
283
(
284
input wire Clock,
285
input wire Reset,
286
input wire [31:0] Initial,
287
input wire Enable,
288
output wire [31:0] Q
289
);
290
        reg [31:0] Temp;
291
 
292
 
293
  always @(posedge Clock or posedge Reset)
294
  begin
295
      if (Reset)
296
                begin
297
         Temp = Initial;
298
                end
299
      else
300
                begin
301
                        if (Enable)
302
                        begin
303
                                Temp =  Temp + 1'b1;
304
                        end
305
                end
306
  end
307
        assign Q = Temp;
308
 
309
endmodule
310
//-----------------------------------------------------------
311
module UpCounter_3
312
(
313
input wire Clock,
314
input wire Reset,
315
input wire [2:0] Initial,
316
input wire Enable,
317
output wire [2:0] Q
318
);
319
        reg [2:0] Temp;
320
 
321
 
322
  always @(posedge Clock or posedge Reset)
323
  begin
324
      if (Reset)
325
         Temp = Initial;
326
      else
327
                        if (Enable)
328
                                Temp =  Temp + 3'b1;
329
  end
330
        assign Q = Temp;
331
 
332
endmodule
333
 
334
 
335
module FFD32_POSEDGE
336
(
337
        input wire Clock,
338
        input wire[31:0] D,
339
        output reg[31:0] Q
340
);
341
 
342
        always @ (posedge Clock)
343
                Q <= D;
344
 
345
endmodule
346
 
347
//------------------------------------------------
348
module FF_OPCODE_POSEDGE_SYNCRONOUS_RESET
349
        (
350
        input wire Clock,
351
        input wire Clear,
352
        input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
353
        output reg[`INSTRUCTION_OP_LENGTH-1:0]  Q
354
        );
355
 
356
  always @(posedge Clock or posedge Clear)
357
    begin
358
           if (Clear)
359
        Q = `INSTRUCTION_OP_LENGTH'b0;
360
      else
361
        Q = D;
362
    end
363
endmodule
364
//------------------------------------------------
365
module FF32_POSEDGE_SYNCRONOUS_RESET
366
        (
367
        input wire Clock,
368
        input wire Clear,
369
        input wire[31:0] D,
370
        output reg[31:0]  Q
371
        );
372
 
373
  always @(posedge Clock or posedge Clear)
374
    begin
375
           if (Clear)
376
        Q = 32'b0;
377
      else
378
        Q = D;
379
    end
380
endmodule
381
//------------------------------------------------
382
module FF16_POSEDGE_SYNCRONOUS_RESET
383
        (
384
        input wire Clock,
385
        input wire Clear,
386
        input wire[15:0] D,
387
        output reg[15:0]  Q
388
        );
389
 
390
  always @(posedge Clock or posedge Clear)
391
    begin
392
           if (Clear)
393
        Q = 16'b0;
394
      else
395
        Q = D;
396
    end
397
endmodule
398
 
399
//------------------------------------------------
400
module MUXFULLPARALELL_96bits_2SEL
401
 (
402
 input wire Sel,
403
 input wire [95:0]I1, I2,
404
 output reg [95:0] O1
405
 );
406
 
407
 
408
 
409
always @( * )
410
 
411
  begin
412
 
413
    case (Sel)
414
 
415
      1'b0: O1 = I1;
416
      1'b1: O1 = I2;
417
 
418
    endcase
419
 
420
  end
421
 
422
endmodule
423
//------------------------------------------------
424
 
425
module MUXFULLPARALELL_16bits_2SEL_X
426
 (
427
 input wire [1:0] Sel,
428
 input wire [15:0]I1, I2, I3,
429
 output reg [15:0] O1
430
 );
431
 
432
 
433
 
434
always @( * )
435
 
436
  begin
437
 
438
    case (Sel)
439
 
440
      2'b00: O1 = I1;
441
      2'b01: O1 = I2;
442
                2'b10: O1 = I3;
443
                default: O1 = 16'b0;
444
 
445
    endcase
446
 
447
  end
448
 
449
endmodule
450
//------------------------------------------------
451
module MUXFULLPARALELL_16bits_2SEL
452
 (
453
 input wire Sel,
454
 input wire [15:0]I1, I2,
455
 output reg [15:0] O1
456
 );
457
 
458
 
459
 
460
always @( * )
461
 
462
  begin
463
 
464
    case (Sel)
465
 
466
      1'b0: O1 = I1;
467
      1'b1: O1 = I2;
468
 
469
    endcase
470
 
471
  end
472
 
473
endmodule
474
 
475
 
476
//------------------------------------------------
477
module MUXFULLPARALELL_1Bit_1SEL
478
 (
479
 input wire Sel,
480
 input wire I1, I2,
481
 output reg O1
482
 );
483
 
484
 
485
 
486
always @( * )
487
 
488
  begin
489
 
490
    case (Sel)
491
 
492
      1'b0: O1 = I1;
493
      1'b1: O1 = I2;
494
 
495
    endcase
496
 
497
  end
498
 
499
endmodule
500
//--------------------------------------------------------------
501
module FFD_OPCODE_POSEDGE
502
(
503
        input wire Clock,
504
        input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
505
        output reg[`INSTRUCTION_OP_LENGTH-1:0] Q
506
);
507
 
508
        always @ (posedge Clock)
509
                Q <= D;
510
 
511
endmodule
512
//--------------------------------------------------------------
513
module FFD16_POSEDGE
514
(
515
        input wire Clock,
516
        input wire[15:0] D,
517
        output reg[15:0] Q
518
);
519
 
520
        always @ (posedge Clock)
521
                Q <= D;
522
 
523
endmodule
524
//--------------------------------------------------------------
525
 
526
  module FFT1
527
  (
528
   input wire D,
529
   input wire Clock,
530
   input wire Reset ,
531
   output reg Q
532
 );
533
 
534
  always @ ( posedge Clock or posedge Reset )
535
  begin
536
 
537
        if (Reset)
538
        begin
539
    Q <= 1'b0;
540
   end
541
        else
542
        begin
543
                if (D)
544
                        Q <=  ! Q;
545
        end
546
 
547
  end//always
548
 
549
 endmodule
550
//--------------------------------------------------------------

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