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[/] [theia_gpu/] [branches/] [beta_1.1/] [rtl/] [Collaterals/] [Module_ArithmeticComparison.v] - Blame information for rev 65

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1 40 diegovalve
`timescale 1ns / 1ps
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`include "aDefinitions.v"
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//------------------------------------------------------------------
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module ArithmeticComparison
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(
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        input wire                                      Clock,
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        input wire[`WIDTH-1:0]   X,Y,
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        input wire[2:0]                  iOperation,
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        input wire                                      iInputReady,
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        output reg                                      OutputReady,
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        output reg                                      Result
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);
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wire [`WIDTH-1:0] wX,wY;
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wire SignX,SignY;
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reg rGreaterThan;
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wire wUGt,wULT,wEQ;
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assign SignX = (X == 0) ? 0: X[31];
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assign SignY = (Y == 0) ? 0: Y[31];
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assign wX = ( SignX ) ? ~X + 1'b1 : X;
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assign wY = ( SignY ) ? ~Y + 1'b1 : Y;
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assign wUGt = wX > wY;
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assign wULT = wX < wY;
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assign wEQ = wX == wY;
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always @ ( * )
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begin
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        case ( {SignX,SignY} )
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                //Greater than test ( X > Y )
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                2'b00: rGreaterThan = wUGt;             //both numbers positive
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                2'b01: rGreaterThan = 1;                        //X positive, y negative        
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                2'b10: rGreaterThan = 0;                 //X negative, y positive
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                2'b11: rGreaterThan = wULT;             //X negative, y negative
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        endcase
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end
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always @ ( posedge Clock )
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begin
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if (iInputReady)
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begin
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        case ( iOperation )
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                3'b000: Result = rGreaterThan;                  //X > Y
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                3'b001: Result = ~rGreaterThan;                 //X < Y
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                3'b010: Result = wEQ;                                           //X == Y
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                3'b011: Result = ~wEQ;                                          //X != Y
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                3'b100: Result = rGreaterThan || wEQ;   // X >= Y
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                3'b101: Result = ~rGreaterThan || wEQ; // X <= Y
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                default: Result = 0;
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        endcase
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                OutputReady = 1;
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end
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else
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                OutputReady = 0;
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end
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endmodule
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//---------------------------------------------

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