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1 42 diegovalve
/*
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        Fixed point Multiplication Module Qm.n
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        C = (A << n) / B
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*/
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`define FPS_AFTER_RESET_STATE 0
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//-----------------------------------------------------------------
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//This only works if you dividend is power of 2
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//x % 2^n == x & (2^n - 1).
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/*
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module Modulus2N
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(
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input wire                                              Clock,
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input wire                                              Reset,
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input wire [`WIDTH-1:0]         iDividend,iDivisor,
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output reg  [`WIDTH-1:0]        oQuotient,
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input  wire                                             iInputReady,            //Is the input data valid?
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output reg                                              oOutputReady            //Our output data is ready!
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);
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FF1_POSEDGE_SYNCRONOUS_RESET FFOutputReadyDelay2
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(
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        .Clock( Clock ),
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        .Clear( Reset ),
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        .D( iInputReady ),
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        .Q( oOutputReady )
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);
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assign oQuotient = (iDividend & (iDivisor-1'b1));
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endmodule
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*/
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//-----------------------------------------------------------------
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/*
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Be aware that the unsgined division algorith doesn't know or care
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about the sign bit of the Result (bit 31). So if you divisor is very
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small there is a chance that the bit 31 from the usginned division is
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one even thogh the result should be positive
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*/
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module SignedIntegerDivision
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(
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input    wire                   Clock,Reset,
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input  wire [`WIDTH-1:0] iDividend,iDivisor,
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output reg  [`WIDTH-1:0] xQuotient,
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input  wire     iInputReady,            //Is the input data valid?
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output reg      OutputReady             //Our output data is ready!
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);
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parameter SIGN = 31;
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wire Sign;
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//wire [7:0] wExitStatus;
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wire [`WIDTH-1:0] wAbsDividend,wAbsDivisor;
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wire [`WIDTH-1:0] wQuottientTemp;
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wire  [`WIDTH-1:0] wAbsQuotient;
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assign Sign = iDividend[SIGN] ^ iDivisor[SIGN];
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assign wAbsDividend = ( iDividend[SIGN] == 1 )?
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                        ~iDividend + 1'b1 : iDividend;
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assign wAbsDivisor = ( iDivisor[SIGN] == 1 )?
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                ~iDivisor + 1'b1 : iDivisor;
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wire DivReady;
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UnsignedIntegerDivision UDIV
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(
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                .Clock(Clock),
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                .Reset( Reset ),
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                .iDividend( wAbsDividend),
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                .iDivisor( wAbsDivisor ),
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                .xQuotient(wQuottientTemp),
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                .iInputReady( iInputReady ),
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                .OutputReady( DivReady )
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        );
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//Make sure the output from the 'unsigned' operation is really posity
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assign wAbsQuotient = wQuottientTemp & 32'h7FFFFFFF;
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//assign Quotient = wAbsQuotient;
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        //-----------------------------------------------
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        always @ ( posedge Clock )
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        begin
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                if ( DivReady )
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                begin
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                        if ( Sign == 1 )
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                                xQuotient = ~wAbsQuotient + 1'b1;
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                        else
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                                xQuotient = wAbsQuotient;
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                end
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                OutputReady = DivReady;
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                if (Reset == 1)
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                        OutputReady = 0;
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        end
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        //-----------------------------------------------
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endmodule
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//-----------------------------------------------------------------
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/*
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        Returns the integer part (Quotient) of a division.
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        Division is the process of repeated subtraction.
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        Like the long division we learned in grade school,
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        a binary division algorithm works from the high
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        order digits to the low order digits and generates
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        a quotient (division result) with each step.
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        The division algorithm is divided into two steps:
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   * Shift the upper bits of the dividend (the number
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   we are dividing into) into the remainder.
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   * Subtract the divisor from the value in the remainder.
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   The high order bit of the result become a bit of
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   the quotient (division result).
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*/
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//-----------------------------------------------------------------
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/*
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Try to implemet the division as a FSM,
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this basically because the behavioral Division has a for loop,
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with a variable loop limit counter which I think is not friendly
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to the synthetiser (dumb dumb synthetizer :) )
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*/
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module UnsignedIntegerDivision(
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input   wire                            Clock,Reset,
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input   wire [`WIDTH-1:0]        iDividend,iDivisor,
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//output reg    [`WIDTH-1:0]    Quotient,Remainder,
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output reg      [`WIDTH-1:0]     xQuotient,
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input  wire     iInputReady,            //Is the input data valid?
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output reg      OutputReady     //Our output data is ready!
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//output reg  [7:0]                     ExitStatus
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);
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//reg           [`WIDTH-1:0] Dividend, Divisor;
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reg [63:0] Dividend,Divisor;
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//reg   [`WIDTH-1:0] t, q, d, i,Bit,  num_bits; 
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reg     [`WIDTH-1:0]  i,num_bits;
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reg [63:0] t, q, d, Bit;
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reg     [63:0]   Quotient,Remainder;
162
 
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reg     [5:0]    CurrentState, NextState;
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//----------------------------------------
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//Next states logic and Reset sequence
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always @(negedge Clock)
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begin
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        if( Reset!=1 )
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           CurrentState = NextState;
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                  else
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                          CurrentState = `FPS_AFTER_RESET_STATE;
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end
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//----------------------------------------
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always @ (posedge Clock)
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begin
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case (CurrentState)
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        //----------------------------------------
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        `FPS_AFTER_RESET_STATE:
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        begin
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                OutputReady = 0;
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                NextState = ( iInputReady == 1 ) ?
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                        `INITIAL_DIVISION_STATE : `FPS_AFTER_RESET_STATE;
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        end
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        //----------------------------------------
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        `INITIAL_DIVISION_STATE:
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        begin
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                Dividend = iDividend;
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                Dividend =  Dividend << `SCALE;
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                Divisor  = iDivisor;
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                Remainder = 0;
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                Quotient = 0;
194
 
195
                if (Divisor == 0)
196
                begin
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                                Quotient[31:0] = 32'h0FFF_FFFF;
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                //      ExitStatus = `DIVISION_BY_ZERO; 
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                                NextState = `WRITE_DIVISION_RESULT;
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                end
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                else if (Divisor > Dividend)
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                begin
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                Remainder       = Dividend;
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                        //ExitStatus    = `NORMAL_EXIT; 
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                        NextState = `WRITE_DIVISION_RESULT;
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        end
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                else if (Divisor == Dividend)
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                begin
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                Quotient = 1;
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        //      ExitStatus      = `NORMAL_EXIT; 
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                        NextState = `WRITE_DIVISION_RESULT;
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      end
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                else
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                begin
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         NextState = `PRE_CALCULATE_REMAINDER;
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                end
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                  //num_bits = 32;
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                  num_bits = 64;
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        end
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        //----------------------------------------
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        `PRE_CALCULATE_REMAINDER:
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        begin
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                //Bit = (Dividend & 32'h80000000) >> 31;
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                Bit = (Dividend & 64'h8000000000000000 ) >> 63;
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        Remainder = (Remainder << 1) | Bit;
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        d = Dividend;
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        Dividend = Dividend << 1;
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        num_bits = num_bits - 1;
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232
 
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//              $display("num_bits %d Remainder %d Divisor %d\n",num_bits,Remainder,Divisor);
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                NextState = (Remainder < Divisor) ?
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                        `PRE_CALCULATE_REMAINDER : `DIVISION_REVERSE_LAST_ITERATION;
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        end
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        //----------------------------------------
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        /*
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                The loop, above, always goes one iteration too far.
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        To avoid inserting an "if" statement inside the loop
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        the last iteration is simply reversed.
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     */
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        `DIVISION_REVERSE_LAST_ITERATION:
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        begin
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                Dividend = d;
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                Remainder = Remainder >> 1;
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                num_bits = num_bits + 1;
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                i = 0;
249
 
250
                NextState = `CALCULATE_REMAINDER;
251
        end
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        //----------------------------------------
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        `CALCULATE_REMAINDER:
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        begin
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                        //Bit = (Dividend & 32'h80000000) >> 31;
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                        Bit = (Dividend & 64'h8000000000000000 ) >> 63;
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                Remainder = (Remainder << 1) | Bit;
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                t = Remainder - Divisor;
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                //q = !((t & 32'h80000000) >> 31);
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                        q = !((t & 64'h8000000000000000 ) >> 63);
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                Dividend = Dividend << 1;
262
                Quotient = (Quotient << 1) | q;
263
                if ( q != 0 )
264
                        Remainder = t;
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                i = i + 1;
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267
                if (i < num_bits)
268
                        NextState = `CALCULATE_REMAINDER;
269
                else
270
                        NextState = `WRITE_DIVISION_RESULT;
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        end
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        //----------------------------------------
273
        //Will go to the IDLE leaving the Result Registers
274
        //with the current results until next stuff comes
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        //So, stay in this state until our client sets iInputReady
276
        //to 0 telling us he read the result
277
        `WRITE_DIVISION_RESULT:
278
        begin
279
                xQuotient = Quotient[32:0];      //Simply chop to round
280
                OutputReady = 1;
281
//              $display("Quotient = %h - %b \n", Quotient, Quotient);
282
 
283
                NextState = (iInputReady == 0) ?
284
                 `FPS_AFTER_RESET_STATE : `WRITE_DIVISION_RESULT;
285
        end
286
endcase
287
 
288
end //always
289
endmodule
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//-----------------------------------------------------------------

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