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1 37 diegovalve
/**********************************************************************************
2
Theaia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2009  Diego Valverde (diego.valverde.g@gmail.com)
4
 
5
This program is free software; you can redistribute it and/or
6
modify it under the terms of the GNU General Public License
7
as published by the Free Software Foundation; either version 2
8
of the License, or (at your option) any later version.
9
 
10
This program is distributed in the hope that it will be useful,
11
but WITHOUT ANY WARRANTY; without even the implied warranty of
12
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
GNU General Public License for more details.
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15
You should have received a copy of the GNU General Public License
16
along with this program; if not, write to the Free Software
17
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
18
 
19
***********************************************************************************/
20
 
21
 
22
/*******************************************************************************
23
Module Description:
24
 
25
        This module defines constants that are going to be used
26
        all over the code. By know you have may noticed that all
27
        constants are pre-compilation define directives. This is
28
        for simulation perfomance reasons mainly.
29
*******************************************************************************/
30
 
31
 
32
//---------------------------------------------------------------------------------
33
//Verilog provides a `default_nettype none compiler directive.  When
34
//this directive is set, implicit data types are disabled, which will make any
35
//undeclared signal name a syntax error.This is very usefull to avoid annoying
36
//automatic 1 bit long wire declaration where you don't want them to be!
37
`default_nettype none
38
//---------------------------------------------------------------------------------
39
//Defines the Scale. This very important because it sets the fixed point precsision.
40
//The Scale defines the number bits that are used as the decimal part of the number.
41
//The code has been written in such a way that allows you to change the value of the
42
//Scale, so that it is possible to experimet with different scenarios. SCALE can be
43
//no smaller that 1 and no bigger that WIDTH.
44
`define SCALE                   17
45
 
46
//The next 2 defines the length of the registers, buses and other structures, 
47
//do not change this valued unless you really know what you are doing (seriously!)
48
`define WIDTH                   32
49
`define WB_WIDTH     32  //width of wish-bone buses             
50
`define LONG_WIDTH      64
51
 
52
`define WB_SIMPLE_READ_CYCLE 0
53
`define WB_SIMPLE_WRITE_CYCLE 1
54
//---------------------------------------------------------------------------------
55
//Next are the constants that define the size of the instructions.
56
//instructions are formed like this:
57
// Tupe I:
58
// Operand                       (of size INSTRUCTION_OP_LENGTH )
59
// DestinationAddr (of size DATA_ADDRESS_WIDTH )
60
// SourceAddrr1  (of size DATA_ADDRESS_WIDTH )
61
// SourceAddrr2  (of size DATA_ADDRESS_WIDTH )  
62
//Type II:
63
// Operand                       (of size INSTRUCTION_OP_LENGTH )
64
// DestinationAddr (of size DATA_ADDRESS_WIDTH )
65
// InmeadiateValue (of size WIDTH = DATA_ADDRESS_WIDTH * 2 )
66
//You can play around with the size of instuctions, but keep
67
//in mind that Bits 3 and 4 of the Operand have a special meaning
68
//that is used for the jump familiy of instructions (see Documentation).
69
//Also the MSB of Operand is used by the decoder to distinguish 
70
//between Type I and Type II instructions.
71
`define INSTRUCTION_WIDTH               64//55
72
`define INSTRUCTION_OP_LENGTH 16//7
73
`define INSTRUCTION_IMM_BIT     6               //don't change this!
74
 
75
//Defines the Lenght of Memory blocks
76
`define DATA_ROW_WIDTH  96
77
`define DATA_ADDRESS_WIDTH              16
78
`define ROM_ADDRESS_WIDTH               16
79
 
80
//---------------------------------------------------------------------------------
81
//Defines the ucode memory entry point for the various ucode routines
82
`define INITIAL_UCODE_ADDRESS           `ROM_ADDRESS_WIDTH'd0
83
`define CPPU_UCODE_ADDRESS                      `ROM_ADDRESS_WIDTH'd14
84
`define RGU_UCODE_ADDRESS                       `ROM_ADDRESS_WIDTH'd17
85
`define AABBIU_UCODE_ADDRESS            `ROM_ADDRESS_WIDTH'd33
86
`define BIU_UCODE_ADDRESS                       `ROM_ADDRESS_WIDTH'd121
87
`define PSU_UCODE_ADRESS                        `ROM_ADDRESS_WIDTH'd196
88
`define PSU_UCODE_ADRESS2        `ROM_ADDRESS_WIDTH'd212
89
`define TCC_UCODE_ADDRESS        `ROM_ADDRESS_WIDTH'd154
90
`define DEBUG_LOG_REGISTERS             `ROM_ADDRESS_WIDTH'd221
91
`define NPG_UCODE_ADDRESS                       `ROM_ADDRESS_WIDTH'd24
92
 
93
`define USER_AABBIU_UCODE_ADDRESS `ROM_ADDRESS_WIDTH'b1000000000000000
94
//---------------------------------------------------------------------------------
95
//This handy little macro allows me to print stuff either to STDOUT or a file.
96
//Notice that the compilation vairable DUMP_CODE must be set if you want to print
97
//to a file. In XILINX right click 'Simulate Beahvioral Model' -> Properties and
98
//under 'Speceify `define macro name and value' type 'DEBUG=1|DUMP_CODE=1'
99
`ifdef DUMP_CODE
100
 
101
        `define LOGME  $fwrite(ucode_file,
102
`else
103
        `define LOGME  $write(
104
`endif
105
//---------------------------------------------------------------------------------     
106
`define RT_TRUE 48'b1
107
`define RT_FALSE 48'b0
108
//---------------------------------------------------------------------------------     
109
`define VOID                                                                    `DATA_ADDRESS_WIDTH'd0  //0000
110
//** Control register bits **//
111
`define CR_EN_LIGHTS   0
112
`define CR_EN_TEXTURE  1
113
`define CR_USER_AABBIU 2
114
 
115
//** Configurtation Registers **//
116
`define CREG_LIGHT_INFO                                         `DATA_ADDRESS_WIDTH'd0  //0000
117
`define CREG_CAMERA_POSITION                            `DATA_ADDRESS_WIDTH'd1  //0001
118
`define CREG_PROJECTION_WINDOW_MIN              `DATA_ADDRESS_WIDTH'd2  //0002
119
`define CREG_PROJECTION_WINDOW_MAX              `DATA_ADDRESS_WIDTH'd3  //0003
120
`define CREG_RESOLUTION                                         `DATA_ADDRESS_WIDTH'd4  //0004
121
`define CREG_TEXTURE_SIZE                                       `DATA_ADDRESS_WIDTH'd5  //0005
122
`define CREG_PIXEL_2D_POSITION                  `DATA_ADDRESS_WIDTH'd6 //0008
123
`define CREG_FIRST_LIGTH               `DATA_ADDRESS_WIDTH'd7   //0007
124
//OK, so from address 0x06 to 0x0F is where the lights are,watch out values are harcoded
125
//for now!! (look in ROM.v for hardcoded values!!!)
126
 
127
 
128
 
129
 
130
 
131
// ** User Registers **//
132
//General Purpose registers, the user may put what ever he/she
133
//wants in here...
134
`define R1              `DATA_ADDRESS_WIDTH'd20
135
`define R2              `DATA_ADDRESS_WIDTH'd21
136
`define R3              `DATA_ADDRESS_WIDTH'd22
137
`define R4              `DATA_ADDRESS_WIDTH'd23
138
`define R5              `DATA_ADDRESS_WIDTH'd24
139
`define R6              `DATA_ADDRESS_WIDTH'd25
140
`define R7              `DATA_ADDRESS_WIDTH'd26
141
`define R8              `DATA_ADDRESS_WIDTH'd27
142
`define R9              `DATA_ADDRESS_WIDTH'd28
143
`define R10             `DATA_ADDRESS_WIDTH'd29
144
`define R11             `DATA_ADDRESS_WIDTH'd30
145
`define R12             `DATA_ADDRESS_WIDTH'd31
146
 
147
 
148
//** Constant Registers **//
149
//Don't change the order of the registers. CREG_V* and CREG_UV* registers
150
//need to be in that specific order for the trinagle fetcher to work 
151
//correctly!
152
`define CREG_PROJECTION_WINDOW_SCALE    `DATA_ADDRESS_WIDTH'd32
153
`define CREG_UNORMALIZED_DIRECTION              `DATA_ADDRESS_WIDTH'd33
154
`define CREG_RAY_DIRECTION                                      `DATA_ADDRESS_WIDTH'd34
155
`define CREG_E1                                                         `DATA_ADDRESS_WIDTH'd35
156
`define CREG_E2                                                         `DATA_ADDRESS_WIDTH'd36
157
`define CREG_T                                                                  `DATA_ADDRESS_WIDTH'd37
158
`define CREG_P                                                                  `DATA_ADDRESS_WIDTH'd38
159
`define CREG_Q                                                                  `DATA_ADDRESS_WIDTH'd39
160
`define CREG_H1                                                         `DATA_ADDRESS_WIDTH'd40
161
`define CREG_H2                                                         `DATA_ADDRESS_WIDTH'd41
162
`define CREG_H3                                                         `DATA_ADDRESS_WIDTH'd42
163
`define CREG_DELTA                                                      `DATA_ADDRESS_WIDTH'd43
164
`define CREG_t                                                                  `DATA_ADDRESS_WIDTH'd44
165
`define CREG_u                                                                  `DATA_ADDRESS_WIDTH'd45
166
`define CREG_v                                                                  `DATA_ADDRESS_WIDTH'd46
167
`define CREG_AABBMIN                                                    `DATA_ADDRESS_WIDTH'd47
168
`define CREG_AABBMAX                                                    `DATA_ADDRESS_WIDTH'd48
169
`define CREG_V0                                                         `DATA_ADDRESS_WIDTH'd49 //002a
170
`define CREG_UV0                                                                `DATA_ADDRESS_WIDTH'd50 //002b  
171
`define CREG_V1                                                         `DATA_ADDRESS_WIDTH'd51 //002c
172
`define CREG_UV1                                                                `DATA_ADDRESS_WIDTH'd52 //002d
173
`define CREG_V2                                                         `DATA_ADDRESS_WIDTH'd53 //002e
174
`define CREG_UV2                                                                `DATA_ADDRESS_WIDTH'd54 //002f
175
`define CREG_TRI_DIFFUSE                                        `DATA_ADDRESS_WIDTH'd55 //0030
176
`define COLOR_ACC                                                               `DATA_ADDRESS_WIDTH'd56 //0031
177
`define CREG_LAST_t                                                     `DATA_ADDRESS_WIDTH'd58 //0033
178
`define CREG_E1_LAST                                                    `DATA_ADDRESS_WIDTH'd59 //0034
179
`define CREG_E2_LAST                                                    `DATA_ADDRESS_WIDTH'd60 //0035
180
`define CREG_TRI_DIFFUSE_LAST                           `DATA_ADDRESS_WIDTH'd61 //0036
181
`define CREG_LAST_u                                                     `DATA_ADDRESS_WIDTH'd62 //0037
182
`define CREG_LAST_v                                                     `DATA_ADDRESS_WIDTH'd63 //0038
183
 
184
 
185
//Output registers
186
`define OREG_PIXEL_COLOR                                        `DATA_ADDRESS_WIDTH'd57 //0032
187
`define OREG_TEX_COORD1                                         `DATA_ADDRESS_WIDTH'd65 //0032
188
`define OREG_TEX_COORD2                                         `DATA_ADDRESS_WIDTH'd66 //0032
189
`define CREG_TEX_COLOR1                                         `DATA_ADDRESS_WIDTH'd67 //0032
190
`define CREG_TEX_COLOR2                                         `DATA_ADDRESS_WIDTH'd68 //0032
191
`define CREG_TEX_COLOR3                                         `DATA_ADDRESS_WIDTH'd69
192
`define CREG_TEX_COLOR4                                         `DATA_ADDRESS_WIDTH'd70 //This is intentionally COLOR6
193
`define CREG_TEX_COLOR5                                         `DATA_ADDRESS_WIDTH'd71
194
`define CREG_TEX_COLOR6                                         `DATA_ADDRESS_WIDTH'd72
195
`define CREG_TEX_COLOR7                                         `DATA_ADDRESS_WIDTH'd73
196
`define OREG_TEXWEIGHT1                                         `DATA_ADDRESS_WIDTH'd74
197
`define OREG_TEXWEIGHT2                                         `DATA_ADDRESS_WIDTH'd75
198
`define OREG_TEXWEIGHT3                                         `DATA_ADDRESS_WIDTH'd76
199
`define OREG_TEXWEIGHT4                                         `DATA_ADDRESS_WIDTH'd77
200
`define CREG_UV0_LAST                  `DATA_ADDRESS_WIDTH'd78
201
`define CREG_UV1_LAST                  `DATA_ADDRESS_WIDTH'd79
202
`define CREG_UV2_LAST                  `DATA_ADDRESS_WIDTH'd80
203
`define OREG_PIXEL_PITCH                        `DATA_ADDRESS_WIDTH'd81
204
`define CREG_LAST_COL                                           `DATA_ADDRESS_WIDTH'd82 //the last valid column, simply CREG_RESOLUTIONX - 1
205
//-------------------------------------------------------------
206
//*** Instruction Set ***
207
//The order of the instrucitons is important here!. Don't change
208
//it unles you know what you are doing. For example all the 'SET'
209
//family of instructions have the MSB bit in 1. This means that
210
//if you add an instruction and the MSB=1, this instruction will treated
211
//as type II (see manual) meaning the second 32bit argument is expected to be
212
//an inmediate value instead of a register address!
213
//Another example is that in the JUMP family Bits 3 and 4 have a special
214
//meaning: b4b3 = 01 => X jump type, b4b3 = 10 => Y jump type, finally 
215
//b4b3 = 11 means Z jump type.
216
//All this is just to tell you: Don't play with these values!
217
 
218
// *** Type I Instructions (OP DST REG1 REG2) ***
219
`define RETURN `INSTRUCTION_OP_LENGTH'b0_000000         //0
220
`define ADD     `INSTRUCTION_OP_LENGTH'b0_000001        //1
221
`define SUB             `INSTRUCTION_OP_LENGTH'b0_000010        //2
222
`define DIV             `INSTRUCTION_OP_LENGTH'b0_000011        //3
223
`define MUL     `INSTRUCTION_OP_LENGTH'b0_000100        //4
224
`define MAG             `INSTRUCTION_OP_LENGTH'b0_000101        //5
225
`define NOP             `INSTRUCTION_OP_LENGTH'b0_000110        //6
226
`define COPY    `INSTRUCTION_OP_LENGTH'b0_000111        //7
227
`define JGX             `INSTRUCTION_OP_LENGTH'b0_001_000       //8
228
`define JLX             `INSTRUCTION_OP_LENGTH'b0_001_001       //9
229
`define JEQX    `INSTRUCTION_OP_LENGTH'b0_001_010       //10
230
`define JNEX    `INSTRUCTION_OP_LENGTH'b0_001_011       //11
231
`define JGEX    `INSTRUCTION_OP_LENGTH'b0_001_100       //12
232
`define JLEX    `INSTRUCTION_OP_LENGTH'b0_001_101       //13
233
`define INC             `INSTRUCTION_OP_LENGTH'b0_001_110       //14
234
`define ZERO    `INSTRUCTION_OP_LENGTH'b0_001_111       //15
235
`define JGY             `INSTRUCTION_OP_LENGTH'b0_010_000       //16
236
`define JLY             `INSTRUCTION_OP_LENGTH'b0_010_001       //17
237
`define JEQY    `INSTRUCTION_OP_LENGTH'b0_010_010       //18
238
`define JNEY    `INSTRUCTION_OP_LENGTH'b0_010_011       //19
239
`define JGEY    `INSTRUCTION_OP_LENGTH'b0_010_100       //20
240
`define JLEY    `INSTRUCTION_OP_LENGTH'b0_010_101       //21
241
`define CROSS   `INSTRUCTION_OP_LENGTH'b0_010_110       //22
242
`define DOT             `INSTRUCTION_OP_LENGTH'b0_010_111       //23
243
`define JGZ             `INSTRUCTION_OP_LENGTH'b0_011_000       //24
244
`define JLZ             `INSTRUCTION_OP_LENGTH'b0_011_001       //25
245
`define JEQZ    `INSTRUCTION_OP_LENGTH'b0_011_010       //26
246
`define JNEZ    `INSTRUCTION_OP_LENGTH'b0_011_011       //27
247
`define JGEZ    `INSTRUCTION_OP_LENGTH'b0_011_100       //28
248
`define JLEZ    `INSTRUCTION_OP_LENGTH'b0_011_101       //29
249
 
250
//The next instruction is for simulation debug only
251
//not to be synthetized! Pretty much behaves the same
252
//as a NOP, only that prints the register value to
253
//a log file called 'Registers.log'
254
`ifdef DEBUG
255
`define DEBUG_PRINT `INSTRUCTION_OP_LENGTH'b0_011_110   //30
256
`endif
257
 
258
`define MULP `INSTRUCTION_OP_LENGTH'b0_011_111                  //31    R1.z = S1.x * S1.y
259
`define MOD `INSTRUCTION_OP_LENGTH'b0_100_000                   //32    R = MODULO( S1,S2 )
260
`define FRAC `INSTRUCTION_OP_LENGTH'b0_100_001                  //33    R =FractionalPart( S1 )
261
`define INTP `INSTRUCTION_OP_LENGTH'b0_100_010                  //34    R =IntergerPart( S1 )
262
`define NEG  `INSTRUCTION_OP_LENGTH'b0_100_011                  //35    R = -S1
263
`define DEC  `INSTRUCTION_OP_LENGTH'b0_100_100                  //36    R = S1--
264
`define XCHANGEX `INSTRUCTION_OP_LENGTH'b0_100_101              //              R.x = S2.x, R.y = S1.y, R.z = S1.z
265
`define XCHANGEY `INSTRUCTION_OP_LENGTH'b0_100_110              //              R.x = S1.x, R.y = S2.y, R.z = S1.z
266
`define XCHANGEZ `INSTRUCTION_OP_LENGTH'b0_100_111              //              R.x = S1.x, R.y = S1.y, R.z = S2.z
267
`define IMUL     `INSTRUCTION_OP_LENGTH'b0_101_000              //              R = INTEGER( S1 * S2 )
268
`define UNSCALE  `INSTRUCTION_OP_LENGTH'b0_101_001              //              R = S1 >> SCALE
269
`define RESCALE  `INSTRUCTION_OP_LENGTH'b0_101_010              //              R = S1 << SCALE
270
`define INCX     `INSTRUCTION_OP_LENGTH'b0_101_011         //    R.X = S1.X + 1
271
`define INCY     `INSTRUCTION_OP_LENGTH'b0_101_100         //    R.Y = S1.Y + 1
272
`define INCZ     `INSTRUCTION_OP_LENGTH'b0_101_101         //    R.Z = S1.Z + 1
273
 
274
 
275
//*** Type II Instructions (OP DST REG1 IMM) ***
276
`define SETX                            `INSTRUCTION_OP_LENGTH'b1_000000 //64 
277
`define SETY                            `INSTRUCTION_OP_LENGTH'b1_000001 //65
278
`define SETZ                            `INSTRUCTION_OP_LENGTH'b1_000010 //66
279
`define SWIZZLE3D                       `INSTRUCTION_OP_LENGTH'b1_000011 //67 
280
`define JMP                                     `INSTRUCTION_OP_LENGTH'b1_011_000       //56
281
//-------------------------------------------------------------
282
 
283
 
284
`define SWIZZLE_XXX             32'd0
285
`define SWIZZLE_YYY             32'd1
286
`define SWIZZLE_ZZZ             32'd2
287
`define SWIZZLE_XYY             32'd3
288
`define SWIZZLE_XXY             32'd4
289
`define SWIZZLE_XZZ             32'd5
290
`define SWIZZLE_XXZ             32'd6
291
`define SWIZZLE_YXX             32'd7
292
`define SWIZZLE_YYX             32'd8
293
`define SWIZZLE_YZZ             32'd9
294
`define SWIZZLE_YYZ             32'd10
295
`define SWIZZLE_ZXX             32'd11
296
`define SWIZZLE_ZZX             32'd12
297
`define SWIZZLE_ZYY             32'd13
298
`define SWIZZLE_ZZY             32'd14
299
`define SWIZZLE_XZX             32'd15
300
`define SWIZZLE_XYX             32'd16
301
`define SWIZZLE_YXY             32'd17
302
`define SWIZZLE_YZY             32'd18
303
`define SWIZZLE_ZXZ             32'd19
304
`define SWIZZLE_ZYZ             32'd20
305
`define SWIZZLE_YXZ             32'd21
306
 
307
 
308
 
309
 
310
//`define REG_BUS_OWNED_BY_BCU   0      //0000
311
`define REG_BUS_OWNED_BY_NULL  0 //0010
312
`define REG_BUS_OWNED_BY_GFU     1 //0001
313
`define REG_BUS_OWNED_BY_UCODE 2 //0011
314
 
315
 
316
`define OP_WIDTH                                `INSTRUCTION_OP_LENGTH
317
`define INST_WIDTH                      5
318
 
319
 
320
`define MULTIPLICATION  0
321
`define DIVISION                        1
322
 
323
 
324
`define ENABLE_ALU_AB   3'b001
325
`define ENABLE_ALU_CD   3'b010
326
`define ENABLE_ALU_EF   3'b100
327
`define ALU_CONTROL_IS_NULL     0
328
`define ALU_CONTROL_IS_RGU      1
329
`define ALU_CONTROL_IS_AABBIU 2
330
`define ALU_CONTROL_IS_CPPU     3
331
 
332
`define UCODE_CONTROL_IS_CU             0
333
`define UCODE_CONTROL_IS_IFU            1
334
 
335
 
336
 
337
`define FLOATING_POINT_WIDTH 32
338
`define FIXED_POINT_WIDTH        32//128
339
`define IEEE754_BIAS             127
340
`define NORMAL_EXIT                      0
341
`define DIVISION_BY_ZERO         1
342
`define NULL                                     0
343
`define RAY_TYPE_I              1
344
`define RAY_TYPE_II             2
345
`define RAY_TYPE_III            3
346
 
347
//Scheduler commands
348
`define SCHEDULER_NULL_COMMAND          0
349
`define REG_SELECTOR_WIDTH                              5
350
//Main state machine control values
351
`define READ_CONFIGURATION_DATA                         2
352
`define WRITE_NO_HIT                                                                            20
353
//Control values for BusUnitInterface
354
`define INITIAL_PROTOCOL_STATE                                          0
355
`define GET_NEXT_CONFIGURATION_PACKET                   4
356
`define READ_COMMAND_DATA                                                       5
357
`define WAIT_FOR_CONTROL_UNIT_COMMAND                   6
358
`define READ_COMMAND                                                                    7
359
`define GET_NEXT_DATA_PACKET                                            8
360
`define IDLE                                                                                    9
361
`define READ_CONFIGURATION_DATA_FROM_BUS                10
362
`define READ_TASK_DATA_FROM_BUS                                 12
363
`define WRITE_TASK_RESULTS_TO_BUS                               13
364
`define ACK_LAST_GO_IDLE                                                14
365
`define REQUEST_BUS_FOR_WRITE_OPERATION 23
366
`define WAIT_FOR_BUS_WRITE_PERMISSION           24
367
`define WRITE_DATA_TO_BUS                                               25
368
`define ACK_BUS_READ_OPERATION                          26
369
`define WAIT_FOR_NEXT_DATA_PACKET                       27
370
`define BCU_READ_LANES                                                  28
371
`define CONFIGURATION_3LANE_DATA_PACKET         12
372
`define BCU_WAIT_FOR_RAM_WRITE                          29
373
`define BCU_READ_DATA_LANE_C                                    30
374
`define BCU_READ_DATA_LANE_D                                    31
375
`define BCU_WRITE_LAST_LANE_TO_RAM                      32
376
`define BCU_WRITE_NO_HIT_TO_BUS                         33
377
`define BCU_ACK_BUS_WRITE_DATA                          34
378
`define BCU_REQUEST_COLOR_ACC_FROM_RAM          35
379
`define BCU_READ_COLOR_ACC_FROM_RAM                     36
380
`define WAIT_FOR_CONTROL_UNIT_ACK                       37
381
`define BCU_REQUEST_COLOR_FROM_RAM                      38
382
`define BCU_RAM_READ_DELAY                                              39
383
`define BCU_READ_COLOR_FROM_RAM                         40
384
 
385
`define FETCH_GEOMETRY                                                  1
386
 
387
//Controlo values for RGU
388
`define RG_AFTER_RESET_STATE                                    1
389
`define RG_WAIT_FOR_CONTROL_UNIT_COMMAND        2
390
`define EXECUTE_TASK_STEP1                                              3
391
`define EXECUTE_TASK_STEP2                                              4
392
`define EXECUTE_TASK_STEP3                                              5
393
`define EXECUTE_TASK_STEP4                                              6
394
`define EXECUTE_TASK_STEP5                                              7
395
 
396
 
397
//Cnotrol values for GFU
398
`define REQUSET_PARENT_CUBE                                     5
399
`define FETCH_CUBE_STAGE_I                                              6
400
`define FETCH_CUBE_STAGE_I_ACK                          7
401
`define FETCH_CUBE_STAGE_II                                     8
402
`define FETCH_CUBE_STAGE_II_ACK                         9
403
`define TRIGGER_CUBE_INTERSECTION_UNIT          10
404
 
405
//Control values for AABBIU
406
`define RAY_INSIDE_BOX_TEST                                     5
407
`define WAIT_FOR_T_DIVISION_RESULTS                     6
408
`define CALCULE_AABB_INTERSECTION                       7
409
`define WAIT_FOR_T_MULTIPLICATION_RESULTS       8
410
`define CALCULATE_AABB_HIT                                              9
411
`define AABB_WRITE_RESULTS                                              10
412
 
413
//RegisterFileVariables
414
`define AGENT_WRITING_VALUE_TO_REGISTER_BUS             1
415
`define AGENT_READING_VALUE_FROM_REGISTER_BUS           0
416
 
417
//Division State Machine Constants
418
`define INITIAL_DIVISION_STATE                                  6'd1
419
`define DIVISION_REVERSE_LAST_ITERATION         6'd2
420
`define PRE_CALCULATE_REMAINDER                                 6'd3
421
`define CALCULATE_REMAINDER                                             6'd4
422
`define WRITE_DIVISION_RESULT                                           6'd5
423
 
424
//Square Root State Machine Constants
425
`define SQUARE_ROOT_LOOP                                        1
426
`define WRITE_SQUARE_ROOT_RESULT                        2
427
 
428
//Multiplication State Machine Constants
429
`define MULTIPLCATION_LOOP                                      1
430
`define WRITE_MULTIPLCATION_RESULT              2
431
 
432
//------------------------------------
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//endmodule

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