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[/] [theia_gpu/] [branches/] [beta_1.1/] [rtl/] [EXE/] [Module_ExecutionFSM.v] - Blame information for rev 65

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1 26 diegovalve
`timescale 1ns / 1ps
2
`include "aDefinitions.v"
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/**********************************************************************************
4
Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
6
 
7
This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
11
 
12
This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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17
You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
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***********************************************************************************/
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`define EXEU_AFTER_RESET                                                        0
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`define EXEU_INITIAL_STATE                                              1
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`define EXEU_WAIT_FOR_DECODE                                            2
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`define EXEU_FETCH_DECODED_INST                                 3
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`define EXEU_WAIT_FOR_ALU_EXECUTION                             4
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`define EXEU_WRITE_BACK_TO_RAM                                  5
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`define EXEU_HANDLE_JUMP                                                        7
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30
 
31
 
32
module ExecutionFSM
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(
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input wire                                                              Clock,
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input wire                                                              Reset,
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input   wire                                                                            iDecodeDone,
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input wire[`INSTRUCTION_OP_LENGTH-1:0]   iOperation,
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input wire[`DATA_ROW_WIDTH-1:0]                          iSource0,iSource1,
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input wire[`DATA_ADDRESS_WIDTH-1:0]              iDestination,
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inout wire[`DATA_ROW_WIDTH-1:0]                          RAMBus,
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//output        reg                                                                     ReadyForNextInstruction,
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output wire                                                                     oJumpFlag                       ,
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output  wire [`ROM_ADDRESS_WIDTH-1:0]    oJumpIp                                 ,
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output  wire                                                                    oRAMWriteEnable         ,
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output  wire [`DATA_ADDRESS_WIDTH-1:0]   oRAMWriteAddress        ,
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output  wire                                                                    oExeLatchedValues,
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output  reg                                                                             oBusy ,
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//ALU ports and control signals
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output  wire [`INSTRUCTION_OP_LENGTH-1:0]                                oALUOperation,
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output  wire [`WIDTH-1:0]                                                                        oALUChannelX1,
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output  wire [`WIDTH-1:0]                                                                        oALUChannelY1,
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output  wire [`WIDTH-1:0]                                                                        oALUChannelZ1,
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output  wire [`WIDTH-1:0]                                                                        oALUChannelX2,
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output  wire [`WIDTH-1:0]                                                                        oALUChannelY2,
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output  wire [`WIDTH-1:0]                                                                        oALUChannelZ2,
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output  wire                                                                                                    oTriggerALU,
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input  wire   [`WIDTH-1:0]                                                                       iALUResultX,
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input  wire       [`WIDTH-1:0]                                                                   iALUResultY,
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input wire        [`WIDTH-1:0]                                                                   iALUResultZ,
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input wire                                                                                                              iALUOutputReady,
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input   wire                                                                                                            iBranchTaken,
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input wire                                                                                                              iBranchNotTaken,
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`ifdef DEBUG
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        input wire[`ROM_ADDRESS_WIDTH-1:0]  iDebug_CurrentIP,
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`endif
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//Data forward Signals
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output wire [`DATA_ADDRESS_WIDTH-1:0] oLastDestination
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73
 
74
);
75
 
76
wire wLatchNow;
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reg rInputLatchesEnabled;
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79
//If ALU says jump, just pass along
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assign oJumpFlag = iBranchTaken;
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//JumpIP is the instruction destination (= oRAMWriteAddress)
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assign oJumpIp = oRAMWriteAddress;
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84
assign wLatchNow = iDecodeDone & rInputLatchesEnabled;
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assign oExeLatchedValues = wLatchNow;
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assign oTriggerALU = wLatchNow;
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wire wOperationIsJump;
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assign wOperationIsJump = iBranchTaken || iBranchNotTaken;
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//Don't allow me to write back back if the operation is a NOP
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`ifdef DEBUG
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        assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump &&
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                (oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT;
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`else
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        assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && oALUOperation != `NOP;
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`endif
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assign RAMBus = ( oRAMWriteEnable ) ? {iALUResultX,iALUResultY,iALUResultZ} : `DATA_ROW_WIDTH'bz;
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FF32_POSEDGE_SYNCRONOUS_RESET SourceX1
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(
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        .Clock( wLatchNow ),
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        .Clear( Reset ),
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        .D( iSource1[95:64] ),
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        .Q( oALUChannelX1 )
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);
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FF32_POSEDGE_SYNCRONOUS_RESET SourceY1
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(
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        .Clock( wLatchNow ),
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        .Clear( Reset ),
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        .D( iSource1[63:32] ),
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        .Q( oALUChannelY1 )
116
);
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118
FF32_POSEDGE_SYNCRONOUS_RESET SourceZ1
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(
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        .Clock( wLatchNow ),
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        .Clear( Reset ),
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        .D( iSource1[31:0] ),
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        .Q( oALUChannelZ1 )
124
);
125
 
126
 
127
FF32_POSEDGE_SYNCRONOUS_RESET SourceX2
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(
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        .Clock( wLatchNow ),
130
        .Clear( Reset ),
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        .D( iSource0[95:64] ),
132
        .Q( oALUChannelX2 )
133
);
134
 
135
FF32_POSEDGE_SYNCRONOUS_RESET SourceY2
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(
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        .Clock( wLatchNow ),
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        .Clear( Reset ),
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        .D( iSource0[63:32] ),
140
        .Q( oALUChannelY2 )
141
);
142
 
143
FF32_POSEDGE_SYNCRONOUS_RESET SourceZ2
144
(
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        .Clock( wLatchNow ),
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        .Clear( Reset ),
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        .D( iSource0[31:0] ),
148
        .Q( oALUChannelZ2 )
149
);
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151
//Finally one more latch to store 
152
//the iOperation and the destination
153
 
154
/*
155
FF6_POSEDGE_SYNCRONOUS_RESET FFOperation
156
(
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        .Clock( wLatchNow ),
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        .Clear( Reset ),
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        .D( iOperation  ),
160
        .Q( oALUOperation )
161
 
162
);
163
*/
164
 
165
FF_OPCODE_POSEDGE_SYNCRONOUS_RESET FFOperation
166
(
167
        .Clock( wLatchNow ),
168
        .Clear( Reset ),
169
        .D( iOperation  ),
170
        .Q( oALUOperation )
171
 
172
);
173
 
174
 
175
FF16_POSEDGE_SYNCRONOUS_RESET PSRegDestination
176
(
177
        .Clock( wLatchNow  ),
178
        .Clear( Reset ),
179
        .D( iDestination  ),
180
        .Q( oRAMWriteAddress )
181
 
182
);
183
//Data forwarding
184
assign oLastDestination = oRAMWriteAddress;
185
 
186
reg [7:0] CurrentState;
187
reg [7:0] NextState;
188
 
189
 
190
//------------------------------------------------
191
  always @(posedge Clock or posedge Reset)
192
  begin
193
 
194
 
195
 
196
    if (Reset)
197
                CurrentState <= `EXEU_AFTER_RESET;
198
    else
199
                CurrentState <= NextState;
200
 
201
  end
202
//------------------------------------------------
203
 
204
 
205
always @( * )
206
   begin
207
        case (CurrentState)
208
                  //------------------------------------------
209
                  `EXEU_AFTER_RESET:
210
                  begin
211
                                //ReadyForNextInstruction <= 1;
212
                                oBusy                                                   <= 0;
213
                                rInputLatchesEnabled            <=      1;
214
 
215
 
216
                                NextState       <= `EXEU_WAIT_FOR_DECODE;
217
                  end
218
                  //------------------------------------------
219
                  /**
220
                        At the same time iDecodeDone goes to 1, our Flops
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                        will store the value, so next clock cycle we can
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                        tell IDU to go ahead and decode the next instruction
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                        in the pipeline.
224
                  */
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                  `EXEU_WAIT_FOR_DECODE:
226
                  begin
227
 
228
 
229
                                //ReadyForNextInstruction <= 1;
230
                                oBusy                                                   <= 0;
231
                                rInputLatchesEnabled            <=      1;
232
 
233
 
234
                        if ( iDecodeDone )      //This same thing triggers the ALU
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                                NextState       <= `EXEU_WAIT_FOR_ALU_EXECUTION;
236
                        else
237
                                NextState       <= `EXEU_WAIT_FOR_DECODE;
238
                  end
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                  //------------------------------------------
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                  /*
241
                  If the instruction is aritmetic then pass the parameters
242
                  the ALU, else if it store iOperation then...
243
                  */
244
                  `EXEU_WAIT_FOR_ALU_EXECUTION:
245
                  begin
246
 
247
                                //ReadyForNextInstruction <= 0;                                         //*
248
                                oBusy                                                   <= 1;
249
                                rInputLatchesEnabled            <=      0;               //NO INTERRUPTIONS WHILE WE WAIT!!
250
 
251
 
252
 
253
                                if ( iALUOutputReady )  /////This same thing enables writing th results to RAM
254
                                        NextState <= `EXEU_WAIT_FOR_DECODE;
255
                                else
256
                                        NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
257
                  end
258
                  //------------------------------------------
259
                  `EXEU_WRITE_BACK_TO_RAM:
260
                  begin
261
 
262
                                //ReadyForNextInstruction <= 0;                                         
263
                                oBusy                                                   <= 1;
264
                                rInputLatchesEnabled            <=      1;
265
 
266
                        if ( iDecodeDone )
267
                                NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
268
                        else
269
                                NextState <= `EXEU_WAIT_FOR_DECODE;
270
 
271
                  end
272
 
273
                  //------------------------------------------
274
                  default:
275
                  begin
276
 
277
                                //ReadyForNextInstruction <= 1;
278
                                oBusy                                                   <= 0;
279
                                rInputLatchesEnabled            <=      1;
280
 
281
                                NextState <= `EXEU_AFTER_RESET;
282
                  end
283
                  //------------------------------------------
284
        endcase
285
end
286
 
287
//-----------------------------------------------------------------------
288
`ifdef DUMP_CODE
289
integer ucode_file;
290
integer reg_log;
291
initial
292
begin
293
 
294
        $display("Opening ucode dump file....\n");
295
        ucode_file = $fopen("Code.log","w");
296
        $fwrite(ucode_file,"\n\n************ Theia UCODE DUMP *******\n\n\n\n");
297
        $display("Opening Register lof file...\n");
298
        reg_log = $fopen("Registers.log","w");
299
 
300
end
301
 
302
`endif //Ucode dump
303
 
304
//-----------------------------------------------------------------------
305
`ifdef DEBUG
306
        always @ (posedge iDecodeDone)
307
        begin
308
                `LOGME"IP:%d", iDebug_CurrentIP);
309
        end
310
 
311
        always @ (negedge  Clock )
312
        begin
313
        if ( iALUOutputReady )
314
        begin
315
 
316
 
317
                if (iBranchTaken)
318
                        `LOGME"<BT>");
319
 
320
                if (iBranchNotTaken     )
321
                        `LOGME"<BNT>");
322
 
323
                if (oRAMWriteEnable)
324
                        `LOGME"<WE>");
325
 
326
                `LOGME "(%dns ",$time);
327
                                        case ( oALUOperation )
328
                                        `RETURN: `LOGME"RETURN");
329
                                        `ADD:   `LOGME"ADD");
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                                        `SUB:           `LOGME"SUB");
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                                        `DIV:           `LOGME"DIV");
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                                        `MUL:   `LOGME"MUL");
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                                        `MAG:           `LOGME"MAG");
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                                        `JGX:           `LOGME"JGX");
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                                        `JGEX:  `LOGME"JGEX");
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                                        `JGEY:  `LOGME"JGEY");
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                                        `JGEZ:  `LOGME"JGEZ");
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                                        `JLEX:  `LOGME"JLEX");
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                                        `JLEY:  `LOGME"JLEY");
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                                        `JLEZ:  `LOGME"JLEZ");
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                                        `JMP:           `LOGME"JMP");
342
                                        `ZERO:  `LOGME"ZERO");
343
                                        `JNEX:  `LOGME"JNEX");
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                                        `JNEY:  `LOGME"JNEY");
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                                        `JNEZ:  `LOGME"JNEZ");
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                                        `JEQX:  `LOGME"JEQX");
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                                        `JEQY:  `LOGME"JEQY");
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                                        `JEQZ:  `LOGME"JEQZ");
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                                        `CROSS: `LOGME"CROSS");
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                                        `DOT:           `LOGME"DOT");
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                                        `SETX:  `LOGME"SETX");
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                                        `SETY:  `LOGME"SETY");
353
                                        `SETZ:  `LOGME"SETZ");
354
                                        `NOP:   `LOGME"NOP");
355
                                        `COPY:  `LOGME"COPY");
356
                                        `INC:           `LOGME"INC");
357
                                        `DEC:           `LOGME"DEC");
358
                                        `MOD:           `LOGME"MOD");
359
                                        `FRAC:  `LOGME"FRAC");
360
                                        `NEG:    `LOGME"NEG");
361
                                        `SWIZZLE3D: `LOGME"SWIZZLE3D");
362
                                        `MULP:          `LOGME"MULP");
363
                                        `XCHANGEX:      `LOGME"XCHANGEX");
364
                                        `IMUL:      `LOGME"IMUL");
365
                                        `UNSCALE:      `LOGME"UNSCALE");
366
                                        `INCX: `LOGME"INCX");
367
                                        `INCY: `LOGME"INCY");
368
                                        `INCZ: `LOGME"INCZ");
369
                                        `DEBUG_PRINT:
370
                                        begin
371
                                                `LOGME"DEBUG_PRINT");
372
 
373
                                        end
374
                                        default:
375
                                        begin
376
                                                `LOGME"**********ERROR UNKNOWN OP*********");
377
                                                $display("%dns EXE: Error Unknown Instruction : %d", $time,oALUOperation);
378
                                        //      $stop();
379
                                        end
380
                                        endcase
381
 
382
                                        `LOGME"\t %h [ %h %h %h ][ %h %h %h ] = ",
383
                                        oRAMWriteAddress,
384
                                        oALUChannelX1,oALUChannelY1,oALUChannelZ1,
385
                                        oALUChannelX2,oALUChannelY2,oALUChannelZ2
386
 
387
                                        );
388
 
389
                                        if (oALUOperation == `RETURN)
390
                                                `LOGME"\n\n\n");
391
 
392
                end
393
        end //always
394
 
395
        always @ ( negedge Clock )
396
        begin
397
        if ( iALUOutputReady )
398
                `LOGME" [ %h %h %h ])\n",iALUResultX,iALUResultY,iALUResultZ);
399
        end //always
400
`endif
401
 
402
endmodule

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