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[/] [theia_gpu/] [branches/] [beta_1.1/] [rtl/] [EXE/] [Module_InstructionDecode.v] - Blame information for rev 65

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1 24 diegovalve
`timescale 1ns / 1ps
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`include "aDefinitions.v"
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
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***********************************************************************************/
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`define IDU_AFTER_RESET 0
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`define IDU_WAIT_FOR_NEXT_INSTRUCTION   1
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`define IDU_WAIT_FOR_RAM        2
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`define IDU_DISPATCH_DECODE_INSTRUCTION 3
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`define IDU_LATCH_RAM_VALUES    4
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`define IDU_WAIT_FOR_FIRST_INTRUCTION 5
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`define IDU_INITIAL_DELAY       6
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30
 
31
 
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module InstructionDecode
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(
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input wire                                                                                      Clock,
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input wire                                                                                      Reset,
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input wire                                                                                      iTrigger,
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input   wire[`INSTRUCTION_WIDTH-1:0]                     iEncodedInstruction,
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input wire                                                                                      iExecutioUnitLatchedValues,
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input   wire                                                                                    iInstructionAvailable,
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output reg                                                                                      oBusy,
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input   wire[`DATA_ROW_WIDTH-1:0]                                        iRamValue0,
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input   wire[`DATA_ROW_WIDTH-1:0]                                        iRamValue1,
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output  wire[`DATA_ADDRESS_WIDTH-1:0]            oRamAddress0,oRamAddress1,
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output  wire[`INSTRUCTION_OP_LENGTH-1:0] oOperation,
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output  wire [`DATA_ROW_WIDTH-1:0]                               oSource0,oSource1,
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output reg oInputsLatched,
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//output reg oBusBusy,
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output reg oDataReadyForExe,
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//input wire iExecutionReady,
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53
 
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output  wire [`DATA_ADDRESS_WIDTH-1:0]   oDestination,
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`ifdef DEBUG
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        input wire [`ROM_ADDRESS_WIDTH-1:0] iDebug_CurrentIP,
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        output wire [`ROM_ADDRESS_WIDTH-1:0] oDebug_CurrentIP,
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`endif
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61
input wire [`DATA_ROW_WIDTH-1:0] iDataForward,
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input wire [`DATA_ADDRESS_WIDTH-1:0] iLastDestination
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);
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65
 
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`ifdef DEBUG
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assign oDebug_CurrentIP = iDebug_CurrentIP;
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69
`endif
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71
 
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reg rFirstInstruction;
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wire wLatchNow;
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wire[`DATA_ADDRESS_WIDTH-1:0] wFF16_2_SourceAddress0;
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76
 
77
 
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`define IFU_WAIT_FOR_FIRST_INSTRUCTION          0
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`define IFU_WAIT_FOR_EXE_TO_LATCH                               1
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`define IFU_WAIT_FOR_INSTRUCTION_AVAILABLE      2
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`define SELECT_ZERO                     1'd0
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`define SELECT_IAVAILABLE       1'd1
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`define INSTRUCTION_OPCODE iEncodedInstruction[`INSTRUCTION_WIDTH-1:`INSTRUCTION_WIDTH-`INSTRUCTION_OP_LENGTH]
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//The next logic is to control when to latch incoming values.
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//Values coming from IFU will be latched by IDU everytime the
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//'wLatchNow' signal is set to 1. We need to garanteed that the wLatchNow is set only if: 
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// 1) There is a instruction available from IFU. ie 'iInstructionAvailable' is set.
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// 2) EXE unit already latched the decoded values we provided from the previous cycle.
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// ie. we won't read new values until we are sure EXE latched the previous values
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//Since the previous 2 conditions don't necesarily happens cocurrently and the pipeline
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//is asynchronous, a FSM is implemented to correctly represent this behavior.
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//This FSM has only 2 states and also controls the 'oBusy' signal, the 'oDataReadyForExe'
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//signal and the 'oInputsLatched' signal.
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97
reg rLatchNowSelector;
98
 
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MUXFULLPARALELL_1Bit_1SEL iInstructionAvailable_MUX
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 (
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 .Sel( rLatchNowSelector ),
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 .I1( 1'b0 ),
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 .I2( iInstructionAvailable ),
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 .O1( wLatchNow )
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 );
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107
 
108
 
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reg[1:0] rLatchNow_CurrentState;
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reg[1:0] rLatchNow_NextState;
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//Next State logic for the LatchNow signal
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always @ (posedge Clock)
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begin
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        if (Reset)
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                rLatchNow_CurrentState <= `IFU_WAIT_FOR_INSTRUCTION_AVAILABLE;
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        else
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                rLatchNow_CurrentState <= rLatchNow_NextState;
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end
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always @ ( * )
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begin
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        case ( rLatchNow_CurrentState )
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                //--------------------------------------
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                `IFU_WAIT_FOR_INSTRUCTION_AVAILABLE:
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                begin
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                        rLatchNowSelector <= `SELECT_IAVAILABLE;
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                        oDataReadyForExe  <= 0;
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                        oBusy                                   <= 0;
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                        oInputsLatched          <= 0;
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                        if ( iInstructionAvailable )
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                                rLatchNow_NextState <= `IFU_WAIT_FOR_EXE_TO_LATCH;
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                        else
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                                rLatchNow_NextState <= `IFU_WAIT_FOR_INSTRUCTION_AVAILABLE;
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                end
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                //--------------------------------------
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                `IFU_WAIT_FOR_EXE_TO_LATCH:
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                begin
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                        rLatchNowSelector <= `SELECT_ZERO;
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                        oDataReadyForExe  <= 1;
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                        oBusy                                   <= 1;
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                        oInputsLatched          <= 1;
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145
                        if ( iExecutioUnitLatchedValues )
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                                rLatchNow_NextState <= `IFU_WAIT_FOR_INSTRUCTION_AVAILABLE;
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                        else
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                                rLatchNow_NextState <= `IFU_WAIT_FOR_EXE_TO_LATCH;
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                end
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                //--------------------------------------
151
        endcase
152
end
153
 
154
 
155
//There are 2 types of operations to be decoded:
156
//1) Operations that read thier parameters from memory locations. 
157
//2) Operations that use inmediate values instead of address locations.
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//The way IDU distinguishes between both is via the wInmediateOperand bit.
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//This is bit 5 of the operation part of the instruction.
160
 
161
wire wInmediateOperand;
162
assign wInmediateOperand = (oOperation[`INSTRUCTION_IMM_BIT ] == 1 || oOperation == `INSTRUCTION_OP_LENGTH'b0) ? 1 : 0;
163
 
164
//Here we decode the 2 Data sources for the instruction: wSource0 and wSource1.
165
//wSource0 will always be assigned to the contents of memory address location,
166
//however wSource1 can either the contents of a memory location or inmediate 
167
//operand.
168
 
169
wire[`DATA_ROW_WIDTH-1:0] wSource0,wSource1;
170
 
171
assign wSource0 = iRamValue0;
172
assign wSource1 = ( wInmediateOperand ) ? {oRamAddress1,wFF16_2_SourceAddress0,32'b0,32'b0} : iRamValue1;
173
 
174
//Since we are implementing a pipeline, data hazards such as RAW may arise.
175
//in order to avoid such race conditions without inserting aditional stall cycles,
176
//a data forward approach has been taken. 2 separe data forwarding signals are available
177
//to indicate weather fordwarding is needed on either of the Source ports.
178
 
179
wire rTriggerSource0DataForward,rTriggerSource1DataForward;
180
wire wSource0AddrssEqualsLastDestination,wSource1AddrssEqualsLastDestination;
181
 
182
assign wSource0AddrssEqualsLastDestination = (oRamAddress0 == iLastDestination) ? 1'b1: 1'b0;
183
assign wSource1AddrssEqualsLastDestination = (oRamAddress1 == iLastDestination) ? 1'b1: 1'b0;
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assign rTriggerSource0DataForward = wSource0AddrssEqualsLastDestination;
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assign rTriggerSource1DataForward = wSource1AddrssEqualsLastDestination && !wInmediateOperand;
186
 
187
//Once we made a decicions on weather the Sources must be forwarded or not, a series of muxes
188
//are used to routed the correct data into the decoded Source outputs
189
 
190
MUXFULLPARALELL_96bits_2SEL Source0_Mux
191
(
192
        .Sel( rTriggerSource0DataForward ),
193
        .I1( wSource0  ),
194
        .I2( iDataForward ),
195
        .O1( oSource0 )
196
);
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198
MUXFULLPARALELL_96bits_2SEL Source1_Mux
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(
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        .Sel( rTriggerSource1DataForward ),
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        .I1( wSource1  ),
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        .I2( iDataForward ),
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        .O1( oSource1 )
204
);
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206
//Next we instance the pipestage Flip Flops to store the stage's data
207
FF16_POSEDGE_SYNCRONOUS_RESET PSRegSource0Address
208
(
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        .Clock( wLatchNow ),
210
        .Clear( Reset ),
211
        .D( iEncodedInstruction[15:0] ),
212
        .Q( wFF16_2_SourceAddress0 )
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214
);
215
 
216
 
217
MUXFULLPARALELL_16bits_2SEL RAMAddr0MUX
218
 (
219
  .Sel( wInmediateOperand ),
220
  .I1( wFF16_2_SourceAddress0 ),
221
  .I2( oDestination ),
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  .O1( oRamAddress0 )
223
 );
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225
FF16_POSEDGE_SYNCRONOUS_RESET PSRegSource1Address
226
(
227
        .Clock( wLatchNow ),
228
        .Clear( Reset ),
229
        .D( iEncodedInstruction[31:16] ),
230
        .Q( oRamAddress1 )
231
);
232
 
233
 
234
FFD16_POSEDGE PSRegDestination
235
(
236
        .Clock( wLatchNow ),
237
        .D( iEncodedInstruction[47:32]  ),
238
        .Q( oDestination )
239
 
240
);
241
 
242
/*
243
FFD6_POSEDGE PSRegOperation
244
(
245
        .Clock( wLatchNow ),
246
        .D( `INSTRUCTION_OPCODE  ),
247
        .Q( oOperation )
248
 
249
);
250
*/
251
FFD_OPCODE_POSEDGE PSRegOperation
252
(
253
        .Clock( wLatchNow ),
254
        .D( `INSTRUCTION_OPCODE  ),
255
        .Q( oOperation )
256
 
257
);
258
//------------------------------------------------
259
 
260
 
261
`ifdef DEBUG2
262
always @ ( negedge Clock  )
263
begin
264
        if ( iInstructionAvailable )
265
        begin
266
 
267
                if ( oRamAddress0 == iLastDestination || oRamAddress1 == iLastDestination)
268
                        $display("%d Data Forward %h ",$time, iDataForward);
269
        end
270
end
271
`endif
272
 
273
 
274
//------------------------------------------------
275
 
276
 
277
 
278
reg     [6:0]    CurrentState,   NextState;
279
//------------------------------------------------
280
  always @(posedge Clock or posedge Reset)
281
  begin
282
 
283
    if (Reset)// || iTrigger )  
284
                CurrentState <= `IDU_AFTER_RESET;
285
    else
286
                CurrentState <= NextState;
287
 
288
  end
289
//------------------------------------------------
290
 
291
always @ ( * )
292
begin
293
        case ( CurrentState )
294
        //------------------------------------
295
        /*
296
                By the time the trigger gets to 1,
297
                there will be data already waiting..
298
 
299
        */
300
        `IDU_AFTER_RESET:
301
        begin
302
 
303
        //      oBusBusy                                <= 0;
304
                rFirstInstruction <= 1;
305
 
306
                if (iInstructionAvailable)
307
                        NextState <= `IDU_WAIT_FOR_NEXT_INSTRUCTION;
308
                else
309
                        NextState <= `IDU_AFTER_RESET;
310
        end
311
                //------------------------------------
312
        `IDU_WAIT_FOR_NEXT_INSTRUCTION:
313
        begin
314
 
315
                //oBusBusy                              <= 0;
316
                rFirstInstruction <= 0;
317
 
318
                if ( iExecutioUnitLatchedValues )
319
                        NextState <= `IDU_WAIT_FOR_RAM;
320
                else
321
                        NextState <= `IDU_WAIT_FOR_NEXT_INSTRUCTION;
322
 
323
        end
324
        //------------------------------------
325
        `IDU_WAIT_FOR_RAM:
326
        begin
327
                //oBusBusy                              <= 1;
328
                rFirstInstruction <= 0;
329
 
330
                if (iInstructionAvailable ||  oOperation == `INSTRUCTION_OP_LENGTH'd0)
331
                        NextState <= `IDU_WAIT_FOR_NEXT_INSTRUCTION;
332
                else
333
                        NextState <= `IDU_WAIT_FOR_RAM;
334
 
335
        end
336
 
337
        //------------------------------------
338
        default:
339
        begin
340
                //oBusBusy                              <= 0;
341
                rFirstInstruction <= 0;
342
 
343
                NextState <= `IDU_WAIT_FOR_NEXT_INSTRUCTION;
344
 
345
        end
346
        //------------------------------------
347
        endcase
348
end
349
 
350
 
351
 
352
 
353
 
354
`ifdef DEBUG2
355
always @ ( posedge wLatchNow )
356
begin
357
 
358
                $display("( %d %d [%d %d] - %d)",
359
                iEncodedInstruction[53:48],iEncodedInstruction[47:32],
360
                iEncodedInstruction[31:16],iEncodedInstruction[15:0], $time );
361
 
362
end
363
`endif
364
 
365
 
366
endmodule

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