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[/] [theia_gpu/] [branches/] [beta_1.1/] [rtl/] [GEO/] [Module_TreeNodeFetcher.v] - Blame information for rev 93

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`timescale 1ns / 1ps
`include "aDefinitions.v"
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
***********************************************************************************/
`define TNF_AFTER_RESET                                 0
`define TNF_IDLE                                                        1
`define TNF_REQUEST_AABBMIN                     2
`define TNF_WAIT_FOR_AABBMIN                    3
`define TNF_REQUEST_AABBMAX                     4
`define TNF_WAIT_FOR_AABBMAX                    5
 
`define TNF_REQUEST_NUMBER_OF_TRIANGLES 10
`define TNF_WAIT_FOR_NUMBER_OF_TRIANGLES 11
`define TNF_LATCH_NUMBER_OF_TRIANGLES    12
`define TNF_WAIT_NODE_READ_ACK                   13
`define TNF_REQUEST_DATA_OFFSET                  14
`define TNF_WAIT_FOR_DATA_OFFSET                         15
`define TNF_LATCH_DATA_OFFSET                            16
`define TNF_REQUEST_NODE_BROTHER_ADDRESS        17
`define TNF_WAIT_FOR_NODE_BROTHER_ADDRESS 18
`define TNF_LACTH_NODE_BROTHER_ADDRESS          19
`define TNF_REQUEST_NODE_PARENT_BROTHER_ADDRESS 20
`define TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS            21
`define TNF_LATCH_NODE_PARENT_BROTHER_ADDRESS   22
`define TNF_RAM_WRITE_DELAY1                                                    23
`define TNF_INC1        24
`define TNF_INC2        25
`define TNF_INC3        26
 
/*
 
        To fetch node, we need to ask WBM to perform several read cycles.
        Each read cycle reads 32 bits. The first 6 read cycles requests
        consecutive addresses that represent AABBMAX and AABBMIN corners.
        These 6 values must be stored into RAM for the ucode to use.
        Next value represents the number of vertices this AABB has, or
        zero is is not a LEAF.
        Next value is the offset where of the vertex data.
*/
 
module TreeNodeFetcher
(
        input wire                                      Clock,
        input wire                                      Reset,
        input   wire[`WIDTH-1:0] iData,
        input   wire                                    iDataAvailable,
        input   wire                                    iTrigger,
        input wire[`WIDTH-1:0]   iInitialAddress,
 
        //wires that go into WBM
        output reg                                              oSetAddressWBM,
        output reg                                              oEnableWBM,
        output wire[`WIDTH-1:0]          oAddressWBM,
        //The parsed node info
        output wire                                             oNode_IsLeaf,
        output wire[`WIDTH-1:0]          oNode_DataOffset,
        output wire     [`WIDTH-1:0]     oNode_TriangleCount,    //Change to 16 bits
        //output wire [`WIDTH-1:0]      oNode_ChildCount,               //Change to 16 bits
 
        output wire [`WIDTH-1:0] oNode_Brother_Address,                  //*
        output wire [`WIDTH-1:0] oParents_Brother_Address,               //*
        //output reg [`WIDTH-1:0]               oNode_FirstChild_Address,
 
        output reg                                              oNodeReadDone,
        output reg                                              oRAMWriteEnable,
 
        output  reg [`DATA_ADDRESS_WIDTH-1:0] oRAMWriteAddress
);
 
reg [4:0]                        CurrentState;
reg [4:0]                        NextState;
 
 
assign oAddressWBM = iInitialAddress;
 
reg rFFEnNumVertices;
 
//Flip Flop D
//FFD_SYNCH_RST_GENERIC FFD32_TNF
FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_TNF
(
        .Clock(         Clock ),
        .Reset(         Reset ),
        .Enable( rFFEnNumVertices ),
        .D( iData ),
        .Q( oNode_TriangleCount )
 
);
 
 
reg rFFEnBrotherAddress;
//Flip Flop D
FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_TNF_NC
//FFD_SYNCH_RST_GENERIC FFD32_TNF_NC
(
        .Clock(         Clock ),
        .Reset(         Reset ),
        .Enable( rFFEnBrotherAddress ),
        .D( iData ),
        .Q( oNode_Brother_Address )
 
);
 
reg rFFEnParentsBroAddr;
//Flip Flop D
FFD_POSEDGE_SYNCRONOUS_RESET  # (`WIDTH) FFD32_TNF_NC2
//FFD_SYNCH_RST_GENERIC FFD32_TNF_NC2
(
        .Clock(         Clock ),
        .Reset(         Reset ),
        .Enable( rFFEnParentsBroAddr ),
        .D( iData ),
        .Q( oParents_Brother_Address )
 
);
 
 
reg rFFEnDataOffset;
//Flip Flop D
FFD_POSEDGE_SYNCRONOUS_RESET  # (`WIDTH) FFD32_TNF2
//FFD_SYNCH_RST_GENERIC FFD32_TNF2
(
        .Clock(         Clock ),
        .Reset(         Reset ),
        .Enable( rFFEnDataOffset ),
        .D( iData ),
        .Q( oNode_DataOffset )
 
);
 
 
assign oNode_IsLeaf = (oNode_TriangleCount != 32'h0);
 
//------------------------------------------------
  always @(posedge Clock or posedge Reset)
  begin
 
    if (Reset)
                CurrentState <= `TNF_AFTER_RESET;
    else
                CurrentState <= NextState;
 
  end
 
//------------------------------------
/*
        IDLE State just waiting for something
        to do...
*/
 
always @( * )
   begin
   case (CurrentState)
        //------------------------------------
        `TNF_AFTER_RESET:
        begin
 
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 0;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                oRAMWriteEnable <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                NextState <= `TNF_IDLE;
        end
        //------------------------------------
        `TNF_IDLE:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 0;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                oRAMWriteEnable <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
           if (iTrigger)
                        NextState <= `TNF_REQUEST_AABBMIN;
                else
                        NextState <= `TNF_IDLE;
 
        end
        //------------------------------------
        /*
        Here tell WBM to read from address iInitialAddress by seeting
        oSetAddressWBM = 1.
        By setting oRAMWriteEnable = 1, we are also telling WBM to
        store the the value in iInitialAddress, iInitialAddress+1,
        and iInitialAddress+2 into RAM, so the WBMAddress is going
        to increment by 3.
        */
        `TNF_REQUEST_AABBMIN:
        begin
                oRAMWriteAddress        <= `CREG_AABBMIN;
                oEnableWBM      <= 1; //*
                oSetAddressWBM          <= 1; //*
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 1; //*
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                NextState <= `TNF_WAIT_FOR_AABBMIN;
 
        end
        //------------------------------------
        `TNF_WAIT_FOR_AABBMIN:
        begin
                oRAMWriteAddress        <= `CREG_AABBMIN;
                oEnableWBM      <= 1;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 1;//*
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                if ( iDataAvailable )
                        NextState <= `TNF_REQUEST_AABBMAX;
                else
                        NextState <= `TNF_WAIT_FOR_AABBMIN;
        end
        //------------------------------------
        `TNF_REQUEST_AABBMAX:
        begin
                oRAMWriteAddress        <= `CREG_AABBMAX;
                oEnableWBM      <= 1;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 1;//*
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                NextState <= `TNF_WAIT_FOR_AABBMAX;
        end
        //------------------------------------
        `TNF_WAIT_FOR_AABBMAX:
        begin
                oRAMWriteAddress        <= `CREG_AABBMAX;
                oEnableWBM      <= 1;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 1;//*
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                if ( iDataAvailable )
                        NextState <= `TNF_REQUEST_NUMBER_OF_TRIANGLES;
                else
                        NextState <= `TNF_WAIT_FOR_AABBMAX;
        end
        //------------------------------------
        `TNF_REQUEST_NUMBER_OF_TRIANGLES:
        begin
                oRAMWriteAddress        <= `CREG_AABBMAX;
                oEnableWBM      <= 1; //*
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 0; //* to give more time to write
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                NextState <= `TNF_WAIT_FOR_NUMBER_OF_TRIANGLES;
        end
        //------------------------------------
        `TNF_WAIT_FOR_NUMBER_OF_TRIANGLES:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 1;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
                oRAMWriteEnable    <= 0;
 
                if ( iDataAvailable )
                        NextState <= `TNF_LATCH_NUMBER_OF_TRIANGLES;
                else
                        NextState <= `TNF_WAIT_FOR_NUMBER_OF_TRIANGLES;
 
        end
        //------------------------------------
        `TNF_LATCH_NUMBER_OF_TRIANGLES:
        begin
 
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 0;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;    //* 
                rFFEnNumVertices        <= 1;
                rFFEnDataOffset <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
                oRAMWriteEnable         <= 0;
 
                NextState <= `TNF_REQUEST_DATA_OFFSET;
        end
        //------------------------------------
        `TNF_REQUEST_DATA_OFFSET:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 1; //*
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                NextState <= `TNF_WAIT_FOR_DATA_OFFSET;
        end
        //------------------------------------
        `TNF_WAIT_FOR_DATA_OFFSET:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 1; //* 
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                if ( iDataAvailable )
                        NextState <= `TNF_LATCH_DATA_OFFSET;
                else
                        NextState <= `TNF_WAIT_FOR_DATA_OFFSET;
 
        end
        //------------------------------------
        `TNF_LATCH_DATA_OFFSET:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 0;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 1; //*
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                NextState <= `TNF_REQUEST_NODE_BROTHER_ADDRESS;
        end
        //------------------------------------
        `TNF_REQUEST_NODE_BROTHER_ADDRESS:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 1;   //*
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 1;
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                NextState <= `TNF_WAIT_FOR_NODE_BROTHER_ADDRESS;
        end
        //------------------------------------
        `TNF_WAIT_FOR_NODE_BROTHER_ADDRESS:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 1;   //*
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                if ( iDataAvailable )
                        NextState <= `TNF_LACTH_NODE_BROTHER_ADDRESS;
                else
                        NextState <= `TNF_WAIT_FOR_NODE_BROTHER_ADDRESS;
        end
        //------------------------------------
        `TNF_LACTH_NODE_BROTHER_ADDRESS:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 0;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 1;   //*
                rFFEnParentsBroAddr     <=      0;
 
                NextState <= `TNF_REQUEST_NODE_PARENT_BROTHER_ADDRESS;
        end
        //------------------------------------
        `TNF_REQUEST_NODE_PARENT_BROTHER_ADDRESS:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 1;   //*
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
                //rLastAddress                                          <= 1;
 
                NextState <= `TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS;
        end
        //------------------------------------
        `TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 1;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                if ( iDataAvailable )
                        NextState <= `TNF_LATCH_NODE_PARENT_BROTHER_ADDRESS;
                else
                        NextState <= `TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS;
        end
        //------------------------------------
        `TNF_LATCH_NODE_PARENT_BROTHER_ADDRESS:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 0;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      1;
 
                NextState <= `TNF_WAIT_NODE_READ_ACK;
 
        end
        //------------------------------------
        `TNF_WAIT_NODE_READ_ACK:
        begin
 
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 0;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 1;   //*
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                if (    iTrigger == 0 )
                        NextState <= `TNF_IDLE;
                else
                        NextState <= `TNF_WAIT_NODE_READ_ACK;
        end
        //------------------------------------
        default:
        begin
                oRAMWriteAddress        <= 0;
                oEnableWBM      <= 0;
                oSetAddressWBM          <= 0;
                oNodeReadDone           <= 0;
                rFFEnNumVertices        <= 0;
                rFFEnDataOffset <= 0;
                oRAMWriteEnable         <= 0;
                rFFEnBrotherAddress     <= 0;
                rFFEnParentsBroAddr     <=      0;
 
                NextState <= `TNF_IDLE;
        end
        //------------------------------------
        endcase
end //always    
endmodule

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[/] [theia_gpu/] [branches/] [beta_1.1/] [rtl/] [GEO/] [Module_TreeNodeFetcher.v] - Blame information for rev 93

Line No.	Rev	Author	Line
1	29	diegovalve	`timescale 1ns / 1ps
2			`include "aDefinitions.v"
3			`/**********************************************************************************`
4			`Theia, Ray Cast Programable graphic Processing Unit.`
5			`Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)`
6
7			`This program is free software; you can redistribute it and/or`
8			`modify it under the terms of the GNU General Public License`
9			`as published by the Free Software Foundation; either version 2`
10			`of the License, or (at your option) any later version.`
11
12			`This program is distributed in the hope that it will be useful,`
13			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
15			`GNU General Public License for more details.`
16
17			`You should have received a copy of the GNU General Public License`
18			`along with this program; if not, write to the Free Software`
19			`Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
20
21			`***********************************************************************************/`
22			`define TNF_AFTER_RESET 0
23			`define TNF_IDLE 1
24			`define TNF_REQUEST_AABBMIN 2
25			`define TNF_WAIT_FOR_AABBMIN 3
26			`define TNF_REQUEST_AABBMAX 4
27			`define TNF_WAIT_FOR_AABBMAX 5
28
29			`define TNF_REQUEST_NUMBER_OF_TRIANGLES 10
30			`define TNF_WAIT_FOR_NUMBER_OF_TRIANGLES 11
31			`define TNF_LATCH_NUMBER_OF_TRIANGLES 12
32			`define TNF_WAIT_NODE_READ_ACK 13
33			`define TNF_REQUEST_DATA_OFFSET 14
34			`define TNF_WAIT_FOR_DATA_OFFSET 15
35			`define TNF_LATCH_DATA_OFFSET 16
36			`define TNF_REQUEST_NODE_BROTHER_ADDRESS 17
37			`define TNF_WAIT_FOR_NODE_BROTHER_ADDRESS 18
38			`define TNF_LACTH_NODE_BROTHER_ADDRESS 19
39			`define TNF_REQUEST_NODE_PARENT_BROTHER_ADDRESS 20
40			`define TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS 21
41			`define TNF_LATCH_NODE_PARENT_BROTHER_ADDRESS 22
42			`define TNF_RAM_WRITE_DELAY1 23
43			`define TNF_INC1 24
44			`define TNF_INC2 25
45			`define TNF_INC3 26
46
47			`/*`
48
49			`To fetch node, we need to ask WBM to perform several read cycles.`
50			`Each read cycle reads 32 bits. The first 6 read cycles requests`
51			`consecutive addresses that represent AABBMAX and AABBMIN corners.`
52			`These 6 values must be stored into RAM for the ucode to use.`
53			`Next value represents the number of vertices this AABB has, or`
54			`zero is is not a LEAF.`
55			`Next value is the offset where of the vertex data.`
56			`*/`
57
58			`module TreeNodeFetcher`
59			`(`
60			`input wire Clock,`
61			`input wire Reset,`
62			input wire[`WIDTH-1:0] iData,
63			`input wire iDataAvailable,`
64			`input wire iTrigger,`
65			input wire[`WIDTH-1:0] iInitialAddress,
66
67			`//wires that go into WBM`
68			`output reg oSetAddressWBM,`
69			`output reg oEnableWBM,`
70			output wire[`WIDTH-1:0] oAddressWBM,
71			`//The parsed node info`
72			`output wire oNode_IsLeaf,`
73			output wire[`WIDTH-1:0] oNode_DataOffset,
74			output wire [`WIDTH-1:0] oNode_TriangleCount, //Change to 16 bits
75			//output wire [`WIDTH-1:0] oNode_ChildCount, //Change to 16 bits
76
77			output wire [`WIDTH-1:0] oNode_Brother_Address, //*
78			output wire [`WIDTH-1:0] oParents_Brother_Address, //*
79			//output reg [`WIDTH-1:0] oNode_FirstChild_Address,
80
81			`output reg oNodeReadDone,`
82			`output reg oRAMWriteEnable,`
83
84			output reg [`DATA_ADDRESS_WIDTH-1:0] oRAMWriteAddress
85			`);`
86
87			`reg [4:0] CurrentState;`
88			`reg [4:0] NextState;`
89
90
91			`assign oAddressWBM = iInitialAddress;`
92
93			`reg rFFEnNumVertices;`
94
95			`//Flip Flop D`
96			`//FFD_SYNCH_RST_GENERIC FFD32_TNF`
97			FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_TNF
98			`(`
99			`.Clock( Clock ),`
100			`.Reset( Reset ),`
101			`.Enable( rFFEnNumVertices ),`
102			`.D( iData ),`
103			`.Q( oNode_TriangleCount )`
104
105			`);`
106
107
108			`reg rFFEnBrotherAddress;`
109			`//Flip Flop D`
110			FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_TNF_NC
111			`//FFD_SYNCH_RST_GENERIC FFD32_TNF_NC`
112			`(`
113			`.Clock( Clock ),`
114			`.Reset( Reset ),`
115			`.Enable( rFFEnBrotherAddress ),`
116			`.D( iData ),`
117			`.Q( oNode_Brother_Address )`
118
119			`);`
120
121			`reg rFFEnParentsBroAddr;`
122			`//Flip Flop D`
123			FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_TNF_NC2
124			`//FFD_SYNCH_RST_GENERIC FFD32_TNF_NC2`
125			`(`
126			`.Clock( Clock ),`
127			`.Reset( Reset ),`
128			`.Enable( rFFEnParentsBroAddr ),`
129			`.D( iData ),`
130			`.Q( oParents_Brother_Address )`
131
132			`);`
133
134
135			`reg rFFEnDataOffset;`
136			`//Flip Flop D`
137			FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_TNF2
138			`//FFD_SYNCH_RST_GENERIC FFD32_TNF2`
139			`(`
140			`.Clock( Clock ),`
141			`.Reset( Reset ),`
142			`.Enable( rFFEnDataOffset ),`
143			`.D( iData ),`
144			`.Q( oNode_DataOffset )`
145
146			`);`
147
148
149			`assign oNode_IsLeaf = (oNode_TriangleCount != 32'h0);`
150
151			`//------------------------------------------------`
152			`always @(posedge Clock or posedge Reset)`
153			`begin`
154
155			`if (Reset)`
156			CurrentState <= `TNF_AFTER_RESET;
157			`else`
158			`CurrentState <= NextState;`
159
160			`end`
161
162			`//------------------------------------`
163			`/*`
164			`IDLE State just waiting for something`
165			`to do...`
166			`*/`
167
168			`always @( * )`
169			`begin`
170			`case (CurrentState)`
171			`//------------------------------------`
172			`TNF_AFTER_RESET:
173			`begin`
174
175			`oRAMWriteAddress <= 0;`
176			`oEnableWBM <= 0;`
177			`oSetAddressWBM <= 0;`
178			`oNodeReadDone <= 0;`
179			`oRAMWriteEnable <= 0;`
180			`rFFEnNumVertices <= 0;`
181			`rFFEnDataOffset <= 0;`
182			`rFFEnBrotherAddress <= 0;`
183			`rFFEnParentsBroAddr <= 0;`
184
185			NextState <= `TNF_IDLE;
186			`end`
187			`//------------------------------------`
188			`TNF_IDLE:
189			`begin`
190			`oRAMWriteAddress <= 0;`
191			`oEnableWBM <= 0;`
192			`oSetAddressWBM <= 0;`
193			`oNodeReadDone <= 0;`
194			`oRAMWriteEnable <= 0;`
195			`rFFEnNumVertices <= 0;`
196			`rFFEnDataOffset <= 0;`
197			`rFFEnBrotherAddress <= 0;`
198			`rFFEnParentsBroAddr <= 0;`
199
200			`if (iTrigger)`
201			NextState <= `TNF_REQUEST_AABBMIN;
202			`else`
203			NextState <= `TNF_IDLE;
204
205			`end`
206			`//------------------------------------`
207			`/*`
208			`Here tell WBM to read from address iInitialAddress by seeting`
209			`oSetAddressWBM = 1.`
210			`By setting oRAMWriteEnable = 1, we are also telling WBM to`
211			`store the the value in iInitialAddress, iInitialAddress+1,`
212			`and iInitialAddress+2 into RAM, so the WBMAddress is going`
213			`to increment by 3.`
214			`*/`
215			`TNF_REQUEST_AABBMIN:
216			`begin`
217			oRAMWriteAddress <= `CREG_AABBMIN;
218			`oEnableWBM <= 1; //*`
219			`oSetAddressWBM <= 1; //*`
220			`oNodeReadDone <= 0;`
221			`rFFEnNumVertices <= 0;`
222			`rFFEnDataOffset <= 0;`
223			`oRAMWriteEnable <= 1; //*`
224			`rFFEnBrotherAddress <= 0;`
225			`rFFEnParentsBroAddr <= 0;`
226
227			NextState <= `TNF_WAIT_FOR_AABBMIN;
228
229			`end`
230			`//------------------------------------`
231			`TNF_WAIT_FOR_AABBMIN:
232			`begin`
233			oRAMWriteAddress <= `CREG_AABBMIN;
234			`oEnableWBM <= 1;`
235			`oSetAddressWBM <= 0;`
236			`oNodeReadDone <= 0;`
237			`rFFEnNumVertices <= 0;`
238			`rFFEnDataOffset <= 0;`
239			`oRAMWriteEnable <= 1;//*`
240			`rFFEnBrotherAddress <= 0;`
241			`rFFEnParentsBroAddr <= 0;`
242
243			`if ( iDataAvailable )`
244			NextState <= `TNF_REQUEST_AABBMAX;
245			`else`
246			NextState <= `TNF_WAIT_FOR_AABBMIN;
247			`end`
248			`//------------------------------------`
249			`TNF_REQUEST_AABBMAX:
250			`begin`
251			oRAMWriteAddress <= `CREG_AABBMAX;
252			`oEnableWBM <= 1;`
253			`oSetAddressWBM <= 0;`
254			`oNodeReadDone <= 0;`
255			`rFFEnNumVertices <= 0;`
256			`rFFEnDataOffset <= 0;`
257			`oRAMWriteEnable <= 1;//*`
258			`rFFEnBrotherAddress <= 0;`
259			`rFFEnParentsBroAddr <= 0;`
260
261			NextState <= `TNF_WAIT_FOR_AABBMAX;
262			`end`
263			`//------------------------------------`
264			`TNF_WAIT_FOR_AABBMAX:
265			`begin`
266			oRAMWriteAddress <= `CREG_AABBMAX;
267			`oEnableWBM <= 1;`
268			`oSetAddressWBM <= 0;`
269			`oNodeReadDone <= 0;`
270			`rFFEnNumVertices <= 0;`
271			`rFFEnDataOffset <= 0;`
272			`oRAMWriteEnable <= 1;//*`
273			`rFFEnBrotherAddress <= 0;`
274			`rFFEnParentsBroAddr <= 0;`
275
276			`if ( iDataAvailable )`
277			NextState <= `TNF_REQUEST_NUMBER_OF_TRIANGLES;
278			`else`
279			NextState <= `TNF_WAIT_FOR_AABBMAX;
280			`end`
281			`//------------------------------------`
282			`TNF_REQUEST_NUMBER_OF_TRIANGLES:
283			`begin`
284			oRAMWriteAddress <= `CREG_AABBMAX;
285			`oEnableWBM <= 1; //*`
286			`oSetAddressWBM <= 0;`
287			`oNodeReadDone <= 0;`
288			`rFFEnNumVertices <= 0;`
289			`rFFEnDataOffset <= 0;`
290			`oRAMWriteEnable <= 0; //* to give more time to write`
291			`rFFEnBrotherAddress <= 0;`
292			`rFFEnParentsBroAddr <= 0;`
293
294			NextState <= `TNF_WAIT_FOR_NUMBER_OF_TRIANGLES;
295			`end`
296			`//------------------------------------`
297			`TNF_WAIT_FOR_NUMBER_OF_TRIANGLES:
298			`begin`
299			`oRAMWriteAddress <= 0;`
300			`oEnableWBM <= 1;`
301			`oSetAddressWBM <= 0;`
302			`oNodeReadDone <= 0;`
303			`rFFEnNumVertices <= 0;`
304			`rFFEnDataOffset <= 0;`
305			`rFFEnBrotherAddress <= 0;`
306			`rFFEnParentsBroAddr <= 0;`
307			`oRAMWriteEnable <= 0;`
308
309			`if ( iDataAvailable )`
310			NextState <= `TNF_LATCH_NUMBER_OF_TRIANGLES;
311			`else`
312			NextState <= `TNF_WAIT_FOR_NUMBER_OF_TRIANGLES;
313
314			`end`
315			`//------------------------------------`
316			`TNF_LATCH_NUMBER_OF_TRIANGLES:
317			`begin`
318
319			`oRAMWriteAddress <= 0;`
320			`oEnableWBM <= 0;`
321			`oSetAddressWBM <= 0;`
322			`oNodeReadDone <= 0; //*`
323			`rFFEnNumVertices <= 1;`
324			`rFFEnDataOffset <= 0;`
325			`rFFEnBrotherAddress <= 0;`
326			`rFFEnParentsBroAddr <= 0;`
327			`oRAMWriteEnable <= 0;`
328
329			NextState <= `TNF_REQUEST_DATA_OFFSET;
330			`end`
331			`//------------------------------------`
332			`TNF_REQUEST_DATA_OFFSET:
333			`begin`
334			`oRAMWriteAddress <= 0;`
335			`oEnableWBM <= 1; //*`
336			`oSetAddressWBM <= 0;`
337			`oNodeReadDone <= 0;`
338			`rFFEnNumVertices <= 0;`
339			`rFFEnDataOffset <= 0;`
340			`oRAMWriteEnable <= 0;`
341			`rFFEnBrotherAddress <= 0;`
342			`rFFEnParentsBroAddr <= 0;`
343
344			NextState <= `TNF_WAIT_FOR_DATA_OFFSET;
345			`end`
346			`//------------------------------------`
347			`TNF_WAIT_FOR_DATA_OFFSET:
348			`begin`
349			`oRAMWriteAddress <= 0;`
350			`oEnableWBM <= 1; //*`
351			`oSetAddressWBM <= 0;`
352			`oNodeReadDone <= 0;`
353			`rFFEnNumVertices <= 0;`
354			`rFFEnDataOffset <= 0;`
355			`oRAMWriteEnable <= 0;`
356			`rFFEnBrotherAddress <= 0;`
357			`rFFEnParentsBroAddr <= 0;`
358
359			`if ( iDataAvailable )`
360			NextState <= `TNF_LATCH_DATA_OFFSET;
361			`else`
362			NextState <= `TNF_WAIT_FOR_DATA_OFFSET;
363
364			`end`
365			`//------------------------------------`
366			`TNF_LATCH_DATA_OFFSET:
367			`begin`
368			`oRAMWriteAddress <= 0;`
369			`oEnableWBM <= 0;`
370			`oSetAddressWBM <= 0;`
371			`oNodeReadDone <= 0;`
372			`rFFEnNumVertices <= 0;`
373			`rFFEnDataOffset <= 1; //*`
374			`oRAMWriteEnable <= 0;`
375			`rFFEnBrotherAddress <= 0;`
376			`rFFEnParentsBroAddr <= 0;`
377
378			NextState <= `TNF_REQUEST_NODE_BROTHER_ADDRESS;
379			`end`
380			`//------------------------------------`
381			`TNF_REQUEST_NODE_BROTHER_ADDRESS:
382			`begin`
383			`oRAMWriteAddress <= 0;`
384			`oEnableWBM <= 1; //*`
385			`oSetAddressWBM <= 0;`
386			`oNodeReadDone <= 0;`
387			`rFFEnNumVertices <= 0;`
388			`rFFEnDataOffset <= 1;`
389			`oRAMWriteEnable <= 0;`
390			`rFFEnBrotherAddress <= 0;`
391			`rFFEnParentsBroAddr <= 0;`
392
393			NextState <= `TNF_WAIT_FOR_NODE_BROTHER_ADDRESS;
394			`end`
395			`//------------------------------------`
396			`TNF_WAIT_FOR_NODE_BROTHER_ADDRESS:
397			`begin`
398			`oRAMWriteAddress <= 0;`
399			`oEnableWBM <= 1; //*`
400			`oSetAddressWBM <= 0;`
401			`oNodeReadDone <= 0;`
402			`rFFEnNumVertices <= 0;`
403			`rFFEnDataOffset <= 0;`
404			`oRAMWriteEnable <= 0;`
405			`rFFEnBrotherAddress <= 0;`
406			`rFFEnParentsBroAddr <= 0;`
407
408			`if ( iDataAvailable )`
409			NextState <= `TNF_LACTH_NODE_BROTHER_ADDRESS;
410			`else`
411			NextState <= `TNF_WAIT_FOR_NODE_BROTHER_ADDRESS;
412			`end`
413			`//------------------------------------`
414			`TNF_LACTH_NODE_BROTHER_ADDRESS:
415			`begin`
416			`oRAMWriteAddress <= 0;`
417			`oEnableWBM <= 0;`
418			`oSetAddressWBM <= 0;`
419			`oNodeReadDone <= 0;`
420			`rFFEnNumVertices <= 0;`
421			`rFFEnDataOffset <= 0;`
422			`oRAMWriteEnable <= 0;`
423			`rFFEnBrotherAddress <= 1; //*`
424			`rFFEnParentsBroAddr <= 0;`
425
426			NextState <= `TNF_REQUEST_NODE_PARENT_BROTHER_ADDRESS;
427			`end`
428			`//------------------------------------`
429			`TNF_REQUEST_NODE_PARENT_BROTHER_ADDRESS:
430			`begin`
431			`oRAMWriteAddress <= 0;`
432			`oEnableWBM <= 1; //*`
433			`oSetAddressWBM <= 0;`
434			`oNodeReadDone <= 0;`
435			`rFFEnNumVertices <= 0;`
436			`rFFEnDataOffset <= 0;`
437			`oRAMWriteEnable <= 0;`
438			`rFFEnBrotherAddress <= 0;`
439			`rFFEnParentsBroAddr <= 0;`
440			`//rLastAddress <= 1;`
441
442			NextState <= `TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS;
443			`end`
444			`//------------------------------------`
445			`TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS:
446			`begin`
447			`oRAMWriteAddress <= 0;`
448			`oEnableWBM <= 1;`
449			`oSetAddressWBM <= 0;`
450			`oNodeReadDone <= 0;`
451			`rFFEnNumVertices <= 0;`
452			`rFFEnDataOffset <= 0;`
453			`oRAMWriteEnable <= 0;`
454			`rFFEnBrotherAddress <= 0;`
455			`rFFEnParentsBroAddr <= 0;`
456
457			`if ( iDataAvailable )`
458			NextState <= `TNF_LATCH_NODE_PARENT_BROTHER_ADDRESS;
459			`else`
460			NextState <= `TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS;
461			`end`
462			`//------------------------------------`
463			`TNF_LATCH_NODE_PARENT_BROTHER_ADDRESS:
464			`begin`
465			`oRAMWriteAddress <= 0;`
466			`oEnableWBM <= 0;`
467			`oSetAddressWBM <= 0;`
468			`oNodeReadDone <= 0;`
469			`rFFEnNumVertices <= 0;`
470			`rFFEnDataOffset <= 0;`
471			`oRAMWriteEnable <= 0;`
472			`rFFEnBrotherAddress <= 0;`
473			`rFFEnParentsBroAddr <= 1;`
474
475			NextState <= `TNF_WAIT_NODE_READ_ACK;
476
477			`end`
478			`//------------------------------------`
479			`TNF_WAIT_NODE_READ_ACK:
480			`begin`
481
482			`oRAMWriteAddress <= 0;`
483			`oEnableWBM <= 0;`
484			`oSetAddressWBM <= 0;`
485			`oNodeReadDone <= 1; //*`
486			`rFFEnNumVertices <= 0;`
487			`rFFEnDataOffset <= 0;`
488			`oRAMWriteEnable <= 0;`
489			`rFFEnBrotherAddress <= 0;`
490			`rFFEnParentsBroAddr <= 0;`
491
492			`if ( iTrigger == 0 )`
493			NextState <= `TNF_IDLE;
494			`else`
495			NextState <= `TNF_WAIT_NODE_READ_ACK;
496			`end`
497			`//------------------------------------`
498			`default:`
499			`begin`
500			`oRAMWriteAddress <= 0;`
501			`oEnableWBM <= 0;`
502			`oSetAddressWBM <= 0;`
503			`oNodeReadDone <= 0;`
504			`rFFEnNumVertices <= 0;`
505			`rFFEnDataOffset <= 0;`
506			`oRAMWriteEnable <= 0;`
507			`rFFEnBrotherAddress <= 0;`
508			`rFFEnParentsBroAddr <= 0;`
509
510			NextState <= `TNF_IDLE;
511			`end`
512			`//------------------------------------`
513			`endcase`
514			`end //always`
515			`endmodule`