OpenCores
URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

[/] [theia_gpu/] [branches/] [beta_1.1/] [rtl/] [IO/] [Module_WishBoneSlave.v] - Blame information for rev 65

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 33 diegovalve
`timescale 1ns / 1ps
2
`include "aDefinitions.v"
3
 
4
 
5
 
6
`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b10
7
`define TAG_DATA_ADDRESS_TYPE    2'b01
8
/**********************************************************************************
9
Theia, Ray Cast Programable graphic Processing Unit.
10
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
11
 
12
This program is free software; you can redistribute it and/or
13
modify it under the terms of the GNU General Public License
14
as published by the Free Software Foundation; either version 2
15
of the License, or (at your option) any later version.
16
 
17
This program is distributed in the hope that it will be useful,
18
but WITHOUT ANY WARRANTY; without even the implied warranty of
19
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20
GNU General Public License for more details.
21
 
22
You should have received a copy of the GNU General Public License
23
along with this program; if not, write to the Free Software
24
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
25
 
26
***********************************************************************************/
27
//------------------------------------------------------------------------------
28
module WishBoneSlaveUnit
29
(
30
//WB Input signals
31
input wire                                                 CLK_I,
32
input wire                                                 RST_I,
33
input wire                    STB_I,
34
input wire                    WE_I,
35
input wire[`WB_WIDTH-1:0]     DAT_I,
36
input wire[`WB_WIDTH-1:0]     ADR_I,
37
input wire [1:0]              TGA_I,
38
output wire                   ACK_O,
39
input wire                    MST_I,   //Master In!
40
input wire                    CYC_I,
41
output wire[`DATA_ADDRESS_WIDTH-1:0]     oDataWriteAddress,
42
output wire [`DATA_ROW_WIDTH-1:0]                oDataBus,
43
output wire [`ROM_ADDRESS_WIDTH-1:0]   oInstructionWriteAddress,
44
output wire [`INSTRUCTION_WIDTH-1:0]     oInstructionBus,
45
output wire                                                                             oDataWriteEnable,
46
output wire                                                                             oInstructionWriteEnable
47
 
48
);
49
 
50
FFD_POSEDGE_SYNCRONOUS_RESET # (16) FFADR
51
(
52
        .Clock( CYC_I ),
53
        .Reset( RST_I ),
54
        .Enable(1'b1),
55
        .D( ADR_I[15:0] ),
56
        .Q( oInstructionWriteAddress )
57
);
58
 
59
assign oDataWriteAddress = oInstructionWriteAddress;
60
 
61
wire[1:0] wTGA_Latched;
62
 
63
FFD_POSEDGE_SYNCRONOUS_RESET # (2) FFADDRTYPE
64
(
65
        .Clock( CYC_I ),
66
        .Reset( RST_I ),
67
        .Enable(1'b1),
68
        .D( TGA_I ),
69
        .Q( wTGA_Latched )
70
);
71
 
72
 
73
 
74
wire Clock,Reset;
75
assign Clock = CLK_I;
76
assign Reset = RST_I;
77
 
78
 
79
wire wLatchNow;
80
assign wLatchNow = STB_I & WE_I;
81
 
82
//1 Clock cycle after we assert the latch signal
83
//then the FF has the data ready to propagate
84
wire wDelay;
85
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFOutputDelay
86
(
87
        .Clock( Clock ),
88
        .Enable( 1'b1 ),
89
        .Reset( Reset ),
90
        .D( wLatchNow ),
91
        .Q( wDelay )
92
);
93
 
94
assign ACK_O = wDelay & STB_I; //make sure we set ACK_O back to zero when STB_I is zero
95
 
96
 
97
wire [2:0] wXYZSel;
98
 
99
SHIFTLEFT_POSEDGE #(3) SHL
100
(
101
  .Clock(CLK_I),
102
  .Enable(STB_I & ~ACK_O),
103
  .Reset(~CYC_I),
104
  .Initial(3'b1),
105
  .O(wXYZSel)
106
 
107
);
108
 
109
 
110
//Flip Flop to Store Vx
111
wire [`WIDTH-1:0] wVx;
112
FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_WBS2MEM_Vx
113
(
114
        .Clock(         Clock ),
115
        .Reset(         Reset ),
116
        .Enable( wXYZSel[0] &  STB_I ),
117
        .D( DAT_I ),
118
        .Q( wVx )
119
 
120
);
121
 
122
 
123
//Flip Flop to Store Vy
124
wire [`WIDTH-1:0] wVy;
125
FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_WBS2MEM_Vy
126
(
127
        .Clock(         Clock ),
128
        .Reset(         Reset ),
129
        .Enable(  wXYZSel[1] &  STB_I ),
130
        .D( DAT_I ),
131
        .Q( wVy )
132
 
133
);
134
 
135
//Flip Flop to Store Vz
136
wire [`WIDTH-1:0] wVz;
137
 
138
FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_WBS2MEM_Vz
139
(
140
        .Clock(         Clock ),
141
        .Reset(         Reset ),
142
        .Enable(  wXYZSel[2] &  STB_I ),
143
        .D( DAT_I ),
144
        .Q( wVz )
145
);
146
 
147
assign oDataBus                   = {wVx,wVy,wVz};
148
assign oInstructionBus = {wVx,wVy};
149
wire wIsInstructionAddress,wIsDataAddress;
150
assign wIsInstructionAddress = (wTGA_Latched == `TAG_INSTRUCTION_ADDRESS_TYPE)  ? 1'b1 : 1'b0;
151
assign wIsDataAddress = (wTGA_Latched == `TAG_DATA_ADDRESS_TYPE )  ? 1'b1 : 1'b0;
152
 
153
assign oDataWriteEnable = (MST_I && !CYC_I && wIsInstructionAddress) ? 1'b1 : 1'b0;
154
assign oInstructionWriteEnable = ( MST_I && !CYC_I && wIsDataAddress) ? 1'b1 : 1'b0;
155
 
156
 
157
 
158
endmodule
159
//------------------------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.