OpenCores
URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

[/] [theia_gpu/] [branches/] [beta_1.1/] [rtl/] [IO/] [Unit_IO.v] - Blame information for rev 65

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 31 diegovalve
`timescale 1ns / 1ps
2
`include "aDefinitions.v"
3
`define ADR_IMM 1
4
`define ADR_POINTER 0
5
/**********************************************************************************
6
Theia, Ray Cast Programable graphic Processing Unit.
7
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
8
 
9
This program is free software; you can redistribute it and/or
10
modify it under the terms of the GNU General Public License
11
as published by the Free Software Foundation; either version 2
12
of the License, or (at your option) any later version.
13
 
14
This program is distributed in the hope that it will be useful,
15
but WITHOUT ANY WARRANTY; without even the implied warranty of
16
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17
GNU General Public License for more details.
18
 
19
You should have received a copy of the GNU General Public License
20
along with this program; if not, write to the Free Software
21
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
22
 
23
***********************************************************************************/
24
//--------------------------------------------------------------------------
25
module IO_Unit
26
(
27
 input wire                            Clock,
28
 input wire                            Reset,
29
 input wire                            iEnable,
30
 input wire [`DATA_ADDRESS_WIDTH-1:0]  iDat_O_Pointer,     //Pointer to what we want to send via DAT_O
31
 input wire [`WIDTH-1:0]               iAdr_O_Imm,         //Value to assign to ADR_O
32
 input wire [`DATA_ADDRESS_WIDTH-1:0]  iAdr_O_Pointer,     //Pointer to value to assing to ADR_O
33
 input wire                            iAdr_O_Type,        //Should we use iAdr_O_Imm or iAdr_O_Pointer
34
 input wire                            iAdr_O_Set,                   //Should we set 
35
 input wire                            iBusCyc_Type,       //Bus cycle type: simple read/write, etc.
36
 input wire                            iStore,             //Should we store read data into MEM
37
 input wire [`DATA_ROW_WIDTH-1:0]      iReadDataBus,       //MEM Data read bus 1
38
 input wire [`DATA_ROW_WIDTH-1:0]      iReadDataBus2,      //MEM Data read bus 2
39
 input wire[`DATA_ADDRESS_WIDTH-1:0]   iAdr_DataWriteBack, //Where in MEM we want to store DAT_I
40
 input wire                            iWriteBack_Set,     //We want to set the Write back Address?
41
 
42
 
43
 output wire[`DATA_ADDRESS_WIDTH-1:0]  oDataReadAddress,
44
 output wire[`DATA_ADDRESS_WIDTH-1:0]  oDataReadAddress2,
45
 output wire[`DATA_ADDRESS_WIDTH-1:0]  oDataWriteAddress,
46
 output wire                           oDataWriteEnable,
47
 output wire [`DATA_ROW_WIDTH-1:0]     oDataBus,
48
 output wire [`INSTRUCTION_WIDTH-1:0]  oInstructionBus,
49
 output wire                           oInstructionWriteEnable,
50
 output wire [`ROM_ADDRESS_WIDTH-1:0]  oInstructionWriteAddress,
51
 inout wire [`WIDTH-1:0]               oData,
52
 output wire                           oDone,
53
 //Theia specific interfaces
54
 input wire MST_I,
55
 //Wish Bone Interfaces
56
output wire [31:0]   DAT_O,
57
input wire [31:0]    DAT_I,
58
input wire           ACK_I,
59
output wire          ACK_O,
60
output wire [31:0]   ADR_O,
61
output wire [31:0]   ADR_I,
62
output wire          WE_O,
63
input wire           WE_I,
64
output wire          STB_O,
65
input wire           STB_I,
66
output wire          CYC_O,
67
input wire           CYC_I,
68
input wire  [1:0]    TGA_I,
69
output wire     [1:0]    TGC_O
70
);
71
 
72
 
73
wire [`WIDTH-1:0]          wMEMToWBM2__ReadDataElement;
74
wire [`WIDTH-1:0]          wMEMToWBM2__ReadDataElement2;
75
wire                       wMEMToWBM_2__Enable;
76
wire                       wWBMToMEM2__Done;
77
wire                       wWBM_2_WBMToMEM_DataAvailable;
78
wire [`WIDTH-1:0]          wWBM_2_WBMToMEM_Data;
79
wire [`WIDTH-1:0]          wWBS_2__WBMToMEM_Frame;
80
wire                       wWBMToMEM_2_WBM_Enable;
81
wire [`WIDTH-1:0]          wWBMToMEM_2_WBM_Address;
82
wire                       wWBMToMEM2__oDataWriteEnable;
83
wire                       wAddrerssSelector2_oDataWriteEnable;
84
wire [`DATA_ROW_WIDTH-1:0] wWBMToMEM2__oDataBus;
85
wire [`DATA_ROW_WIDTH-1:0] wWBSToMEM2__oDataBus;
86
wire                       wAddressSelector_2__SetAddress;
87
wire [`WIDTH-1:0]          wMEMToWBM_2__Address;
88
wire                       wMEMToWBM_2__Done;
89
wire                       w2WBMToMEM__Enable;
90
wire                       w2WBMToMEM__SetAddress;
91
wire                       wWBS_2__WBSToMEM_FrameAvailable;
92
wire[`WIDTH-1:0]           wWBS_2__WBMToMEM_Address;
93
wire                       wWBSToMEM2__oDataWriteEnable;
94
wire[`DATA_ADDRESS_WIDTH-1:0] wWBSToMEM2__oDataWriteAddress;
95
wire[`DATA_ADDRESS_WIDTH-1:0] wWBMToMEM2__oDataWriteAddress;
96
 
97
wire wReadOperation;
98
assign wReadOperation = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? 0 : 1;
99
 
100
 
101
assign wMEMToWBM_2__Address    = ( iAdr_O_Type == `ADR_IMM ) ? iAdr_O_Imm  : wMEMToWBM2__ReadDataElement;
102
assign w2WBMToMEM__Enable    = ( iAdr_O_Type == `ADR_IMM ) ? iEnable       : wMEMToWBM_2__Enable;
103
//assign oDone                  = ( (iAdr_O_Type == `ADR_IMM) && !(iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ) 
104
//? wWBMToMEM2__Done : wMEMToWBM_2__Done;
105
 
106
//TODO: WHEN ADR_POINTER Then Done is not until we got the 3 values from X,Y,Z in iAdr_O_Pointer
107
assign oDone = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE || iAdr_O_Type == `ADR_POINTER ) ? wMEMToWBM_2__Done : wWBMToMEM2__Done;
108
 
109
assign oDataWriteEnable  = (MST_I == 1'b1) ? wWBSToMEM2__oDataWriteEnable : (wWBMToMEM2__oDataWriteEnable);// ^ wAddrerssSelector2_oDataWriteEnable);
110
assign oDataWriteAddress = (MST_I == 1'b1) ? wWBSToMEM2__oDataWriteAddress : wWBMToMEM2__oDataWriteAddress;
111
assign oDataBus          = (MST_I == 1'b1) ? wWBSToMEM2__oDataBus : wWBMToMEM2__oDataBus;
112
 
113
 
114
 
115
 
116
 
117
 wire [`DATA_ADDRESS_WIDTH-1:0] wMEMToWBM2_WBMToMEM_RAMWriteAddr;
118
 wire [`DATA_ADDRESS_WIDTH-1:0] w2WBMToMEM_MEMWriteAddress;
119
 
120
assign w2WBMToMEM_MEMWriteAddress = ( iAdr_O_Type == `ADR_IMM) ? iAdr_DataWriteBack : wMEMToWBM2_WBMToMEM_RAMWriteAddr;
121
 
122
wire w2MEMToWBM_BusOperationComplete;
123
assign w2MEMToWBM_BusOperationComplete = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? ACK_I  :  wWBMToMEM2__Done;
124
 
125
 
126
wire [`DATA_ADDRESS_WIDTH-1:0] w2MEMToWBM_DataPointer;
127
assign w2MEMToWBM_DataPointer = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? iDat_O_Pointer : iAdr_O_Pointer;
128
//------------------------------------------------------------------------------
129
MEM2WBMUnitB MEMToWBM
130
(
131
.Clock(                        Clock                                           ),
132
.Reset(                        Reset                                           ),
133
.iEnable(                      iEnable & (~iAdr_O_Type | iBusCyc_Type)         ),
134
.iMEMDataPointer(           w2MEMToWBM_DataPointer                          ),
135
.iMEMDataPointer2(           iAdr_O_Pointer                          ),
136
.iReadDataBus(                 iReadDataBus                                                                     ),   //3 Elements comming from DMEM
137
.iReadDataBus2(                iReadDataBus2                                   ),
138
.oReadDataElement(             wMEMToWBM2__ReadDataElement                     ),       //1 out of 3 elements we read
139
.oReadDataElement2(            wMEMToWBM2__ReadDataElement2                     ),      //1 out of 3 elements we read
140
.oDataReadAddress(              oDataReadAddress                                ),
141
.oDataReadAddress2(              oDataReadAddress2                             ),
142
.oDataWriteEnable(              wAddrerssSelector2_oDataWriteEnable             ),   //Always zero
143
.oDataAvailable(              wMEMToWBM_2__Enable                             ),    //Data from MEM available
144
.iRequestNextElement(          w2MEMToWBM_BusOperationComplete                 ),
145
.iDataInitialStorageAddress(    iAdr_DataWriteBack                              ), ////########
146
.oDataWriteAddress(             wMEMToWBM2_WBMToMEM_RAMWriteAddr        ), ////########
147
.oDone(                        wMEMToWBM_2__Done                               )
148
);
149
//------------------------------------------------------------------------------
150
wire [`DATA_ADDRESS_WIDTH-1:0] wTemp1;
151
 assign wWBMToMEM2__oDataWriteAddress = (iAdr_O_Type == `ADR_IMM) ? iAdr_DataWriteBack : wTemp1;
152
WBM2MEMUnit WBMToMEM
153
(
154
.Clock(                 Clock                                     ),
155
.Reset(                 Reset                                     ),
156
.iEnable(              w2WBMToMEM__Enable & (wReadOperation | MST_I)  ), //Don't write stuff to MEM unless is Read bus cycle
157
 
158
.iStore(                iStore | ~iAdr_O_Type                     ),
159
.iWriteBack_Set( iWriteBack_Set ),
160
.iAdr_DataWriteBack(w2WBMToMEM_MEMWriteAddress              ),
161
//.iAdr_DataWriteBack(      iAdr_DataWriteBack ),
162
.iWBMDataAvailable(     wWBM_2_WBMToMEM_DataAvailable             ),
163
.iWBMData(              wWBM_2_WBMToMEM_Data                      ),
164
 
165
.oDataBus(               wWBMToMEM2__oDataBus                     ),
166
.oData(                 oData                                     ),
167
.oEnableWBM(           wWBMToMEM_2_WBM_Enable                   ),
168
.oDataWriteAddress(      wTemp1            ),///*******************!!!!!!!!!!!!!!
169
.oDataWriteEnable(       wWBMToMEM2__oDataWriteEnable             ),
170
.oDone(                 wWBMToMEM2__Done                          )
171
);
172
 
173
 
174
 
175
wire [`WIDTH-1:0] wADR_O_InitialAddress;
176
assign wADR_O_InitialAddress = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? wMEMToWBM2__ReadDataElement2 : wMEMToWBM_2__Address;
177
wire wIncrement_Address_O;
178
assign wIncrement_Address_O = iEnable & ACK_I;
179
 
180
 
181
 
182
wire                 wMEMToWBM2__Done;
183
wire                 wMEMToWBM2__Trigger;
184
wire[`WB_WIDTH-1:0]  wMEMToWBM_2_Data;
185
wire                 w2MEMToWBM__Trigger;
186
wire                 wWBM2_MEMToWBM_DataWriteDone;
187
 
188
 
189
wire w2WBM_iEnable;
190
//wire wWBMEnable_tempWire;
191
//assign wWBMEnable_tempWire = (iAdr_O_Type == `ADR_IMM) ? wWBMToMEM_2_WBM_Enable;
192
//assign w2WBM_iEnable = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? wMEMToWBM_2__Enable : wWBMToMEM_2_WBM_Enable;
193
assign w2WBM_iEnable = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? wMEMToWBM_2__Enable : iEnable;
194
//assign w2WBM_iEnable = iEnable;// & wWBMToMEM_2_WBM_Enable;
195
//------------------------------------------------------------------------------
196
wire wSTB_O;
197
 
198
//If the address is a pointer, we need 1 cycle to read the data back from MEM
199
//before we can the set the value into WBM
200
wire wAddress_Set_Delayed;
201
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD32_SetDelay
202
(
203
        .Clock(         Clock ),
204
        .Reset(         Reset ),
205
        .Enable( 1'b1 ),
206
        .D( iAdr_O_Set ),
207
        .Q( wAddress_Set_Delayed )
208
 
209
);
210
 
211
//If the Addr is IMM then just set it whenever iAdr_O_Set is set, but if we have a pointer, then use
212
//wAddress_Set_Delayed at the beginning and then wWBMToMEM2__Done
213
wire wWBM_iAddress_Set = (iAdr_O_Type == `ADR_POINTER) ? (wAddress_Set_Delayed | wWBMToMEM2__Done) :    iAdr_O_Set;
214
 
215
assign STB_O = wSTB_O & ~oDone;
216
 
217
        WishBoneMasterUnit WBM
218
        (
219
                .CLK_I(         Clock ),
220
                .RST_I(         Reset ),
221
                .DAT_I(         DAT_I ),
222
                .DAT_O(  DAT_O ),
223
                .ACK_I(         ACK_I ),
224
                .ADR_O(         ADR_O ),
225
                .WE_O(  WE_O ),
226
                .STB_O( wSTB_O ),
227
                .CYC_O( CYC_O   ),
228
                .TGC_O( TGC_O   ),
229
 
230
                .iEnable(                       w2WBM_iEnable            ),
231
                .iBusCyc_Type(    iBusCyc_Type                     ),
232
                .iAddress_Set(  wWBM_iAddress_Set  ),//ERROR!!!!!!!!!! we should have:  wWBMToMEM2__Done  
233
                .iAddress(            wADR_O_InitialAddress            ),
234
                .oDataReady(            wWBM_2_WBMToMEM_DataAvailable    ),
235
                .iData(           wMEMToWBM2__ReadDataElement      ),
236
                .oData(                                 wWBM_2_WBMToMEM_Data                       )
237
        );
238
//------------------------------------------------------------------------------
239
WishBoneSlaveUnit WBS
240
(
241
 
242
                .CLK_I(         Clock  ),
243
                .RST_I(         Reset  ),
244
                .STB_I(  STB_I  ),
245
           .WE_I(   WE_I   ),
246
                .DAT_I(  DAT_I  ),
247
           .ADR_I(  ADR_I  ),
248
                .TGA_I(  TGA_I  ),
249
                .ACK_O(  ACK_O  ),
250
                .CYC_I(  CYC_I  ),
251
                .MST_I(  MST_I ),
252
 
253
                .oDataBus(               wWBSToMEM2__oDataBus                    ),
254
                .oInstructionBus(        oInstructionBus                         ),
255
                .oDataWriteAddress(      wWBSToMEM2__oDataWriteAddress           ),
256
                .oDataWriteEnable(       wWBSToMEM2__oDataWriteEnable            ),
257
                .oInstructionWriteAddress(      oInstructionWriteAddress         ),
258
                .oInstructionWriteEnable(       oInstructionWriteEnable          )
259
 
260
 
261
 
262
);
263
//------------------------------------------------------------------------------
264
 
265
 
266
endmodule
267
//--------------------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.