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[/] [theia_gpu/] [branches/] [beta_1.1/] [rtl/] [MEM/] [Module_ControlRegister.v] - Blame information for rev 65

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`timescale 1ns / 1ps
`include "aDefinitions.v"
 
//-------------------------------------------------------------------
module ControlRegister
(
        input wire Clock,
        input wire Reset,
        input wire[15:0] iControlRegister,
        output wire[15:0] oControlRegister
);
 
reg [15:0] rControlRegister;
 
assign oControlRegister = rControlRegister;
 
always @ (posedge Clock)
begin
        if ( Reset )
                rControlRegister <= 16'b0;
        else
        begin
                rControlRegister <= iControlRegister;
        end
end
 
endmodule
//-------------------------------------------------------------------

Line No.	Rev	Author	Line
1	53	diegovalve	`timescale 1ns / 1ps
2			`include "aDefinitions.v"
3
4			`//-------------------------------------------------------------------`
5			`module ControlRegister`
6			`(`
7			`input wire Clock,`
8			`input wire Reset,`
9			`input wire[15:0] iControlRegister,`
10			`output wire[15:0] oControlRegister`
11			`);`
12
13			`reg [15:0] rControlRegister;`
14
15			`assign oControlRegister = rControlRegister;`
16
17			`always @ (posedge Clock)`
18			`begin`
19			`if ( Reset )`
20			`rControlRegister <= 16'b0;`
21			`else`
22			`begin`
23			`rControlRegister <= iControlRegister;`
24			`end`
25			`end`
26
27			`endmodule`
28			`//-------------------------------------------------------------------`

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[/] [theia_gpu/] [branches/] [beta_1.1/] [rtl/] [MEM/] [Module_ControlRegister.v] - Blame information for rev 65