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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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/**********************************************************************************
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Description:
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This is the top level block for THEIA.
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THEIA core has 5 main logical blocks called Units.
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This module implements the interconections between the Units.
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Units:
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> EXE: Mananges execution logic for the SHADERS.
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> GEO: Manages geometry data structures.
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> IO: Input/Output (Wishbone).
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> MEM: Internal memory, separate for Instructions and data.
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> CONTROL: Main control Finite state machine.
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Internal Buses:
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THEIA has separate instruction and data buses.
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THEIA avoids using tri-state buses by having separate input/output
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for each bus.
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There are 2 separate data buses since the Data memory
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has a Dual read channel.
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Please see the MEM unit chapter in the documentation for more details.
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External Buses:
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External buses are managed by the IO Unit.
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External buses follow the wishbone protocol.
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Please see the IO unit chapter in the documentation for more details.
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**********************************************************************************/
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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module THEIACORE
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(
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input wire CLK_I, //Input clock
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input wire RST_I, //Input reset
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//Theia Interfaces
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input wire MST_I, //Master signal, THEIA enters configuration mode
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//when this gets asserted (see documentation)
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//Wish Bone Interface
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input wire [`WB_WIDTH-1:0] DAT_I, //Input data bus (Wishbone)
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output wire [`WB_WIDTH-1:0] DAT_O, //Output data bus (Wishbone)
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input wire ACK_I, //Input ack
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output wire ACK_O, //Output ack
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output wire [`WB_WIDTH-1:0] ADR_O, //Output address
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input wire [`WB_WIDTH-1:0] ADR_I, //Input address
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output wire WE_O, //Output write enable
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input wire WE_I, //Input write enable
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output wire STB_O, //Strobe signal, see wishbone documentation
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input wire STB_I, //Strobe signal, see wishbone documentation
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output wire CYC_O, //Bus cycle signal, see wishbone documentation
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input wire CYC_I, //Bus cycle signal, see wishbone documentation
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output wire [1:0] TGC_O, //Bus cycle tag, see THEAI documentation
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input wire [1:0] TGA_I, //Input address tag, see THEAI documentation
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output wire [1:0] TGA_O, //Output address tag, see THEAI documentation
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input wire [1:0] TGC_I, //Bus cycle tag, see THEAI documentation
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//Control Register
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input wire [15:0] CREG_I
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);
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//Alias this signals
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wire Clock,Reset;
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assign Clock = CLK_I;
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assign Reset = RST_I;
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wire [`DATA_ROW_WIDTH-1:0] w2MEM_WriteData;
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wire [`DATA_ROW_WIDTH-1:0] wUCODE_RAMBus;
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wire [`DATA_ADDRESS_WIDTH-1:0] wDataWriteAddress;
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wire w2IO__AddrIsImm;
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wire [`DATA_ADDRESS_WIDTH-1:0] wUCODE_RAMAddress;
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wire [`DATA_ADDRESS_WIDTH-1:0] w2IO__Adr_O_Pointer;
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wire [`DATA_ADDRESS_WIDTH-1:0] wGEO2_IO__Adr_O_Pointer;
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wire DataWriteEnable;
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wire wUCODE_RAMWriteEnable;
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wire [2:0] RamBusOwner;
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//Unit intercoanection wires
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wire wCU2__MicrocodeExecutionDone;
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wire [`ROM_ADDRESS_WIDTH-1:0] InitialCodeAddress;
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wire [`ROM_ADDRESS_WIDTH-1:0] wInstructionPointer;
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wire [`INSTRUCTION_WIDTH-1:0] wEncodedInstruction,wIO2_MEM__ExternalInstruction;
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wire wCU2__ExecuteMicroCode;
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wire [`ROM_ADDRESS_WIDTH-1:0] wIO2_MEM__InstructionWriteAddr;
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wire [95:0] wDataRead0, wDataRead1;
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wire [`DATA_ADDRESS_WIDTH-1:0] wDataReadAddress0,wDataReadAddress1;
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wire [`DATA_ADDRESS_WIDTH-1:0] wUCODE_RAMReadAddress0,wUCODE_RAMReadAddress1;
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wire [`WIDTH-1:0] w2IO__AddressOffset;
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wire [`DATA_ADDRESS_WIDTH-1:0] w2IO__DataWriteAddress;
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wire w2IO__Store;
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wire w2IO__EnableWBMaster;
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wire [`DATA_ADDRESS_WIDTH-1:0] wIO2_BUSMUX__DataWriteAddress;
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wire [`DATA_ADDRESS_WIDTH-1:0] wIO_2_MEM__DataReadAddress0;
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wire [`DATA_ROW_WIDTH-1:0] wIO2_BUSMUX__Bus;
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wire [`WIDTH-1:0] wIO2__Data;
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wire [`WIDTH-1:0] wIO2_WBM__Address;
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wire wIO2_BUSMUX__DataWriteEnable;
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wire wIO2__Done;
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wire wCU2_GEO__GeometryFetchEnable;
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wire wIFU2__MicroCodeReturnValue;
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wire wCU2_BCU__ACK;
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wire wGEO2_CU__RequestAABBIU;
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wire wGEO2_CU__RequestBIU;
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wire wGEO2_CU__RequestTCC;
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wire wGEO2_CU__GeometryUnitDone;
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wire wGEO2_CU__Sync;
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wire wEXE2__uCodeDone;
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wire wEXE2_IFU__EXEBusy;
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wire [`DATA_ADDRESS_WIDTH-1:0] wEXE2_IDU_DataFordward_LastDestination;
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wire wALU2_EXE__BranchTaken;
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wire wALU2_IFU_BranchNotTaken;
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wire w2IO__SetAddress;
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wire wIDU2_IFU__IDUBusy;
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//Control Registe wires
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wire[15:0] wCR2_ControlRegister;
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wire wCR2_TextureMappingEnabled;
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wire wGEO2_CU__TFFDone;
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wire wCU2_GEO__TriggerTFF;
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wire wIO2_MEM_InstructionWriteEnable;
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wire wCU2_IO__WritePixel;
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wire wGEO2_IO__AddrIsImm;
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wire[31:0] wGEO2_IO__AddressOffset;
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wire wGEO2_IO__EnableWBMaster;
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wire wGEO2_IO__SetAddress;
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wire[`WIDTH-1:0] wGEO2__CurrentPitch,wCU2_GEO_Pitch;
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wire wCU2_GEO__SetPitch,wCU2_GEO__IncPicth;
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`ifdef DEBUG
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wire [`ROM_ADDRESS_WIDTH-1:0] wDEBUG_IDU2_EXE_InstructionPointer;
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`endif
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//--------------------------------------------------------
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///////////////// TODO CHANGE FOR MUXES ////////////////////////////////
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assign w2MEM_WriteData = ( RamBusOwner == `REG_BUS_OWNED_BY_UCODE ) ?
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wUCODE_RAMBus : `DATA_ROW_WIDTH'bz;
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assign w2MEM_WriteData = ( RamBusOwner == `REG_BUS_OWNED_BY_GFU || MST_I == 1'b1) ?
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wIO2_BUSMUX__Bus : `DATA_ROW_WIDTH'bz;
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assign wDataWriteAddress = ( RamBusOwner == `REG_BUS_OWNED_BY_UCODE ) ?
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wUCODE_RAMAddress : `DATA_ADDRESS_WIDTH'bz;
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assign wDataWriteAddress = ( RamBusOwner == `REG_BUS_OWNED_BY_GFU || MST_I == 1'b1) ?
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wIO2_BUSMUX__DataWriteAddress : `DATA_ADDRESS_WIDTH'bz;
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MUXFULLPARALELL_2SEL_GENERIC # ( `DATA_ADDRESS_WIDTH ) MUX_RA0
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(
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.Sel(RamBusOwner[1:0]),
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.I1(`DATA_ADDRESS_WIDTH'b0),
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.I2(wIO_2_MEM__DataReadAddress0),
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.I3(wUCODE_RAMReadAddress0),
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.O1(wDataReadAddress0)
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);
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assign DataWriteEnable = ( RamBusOwner == `REG_BUS_OWNED_BY_UCODE && MST_I == 1'b0) ?
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wUCODE_RAMWriteEnable : 1'bz;
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assign DataWriteEnable = ( RamBusOwner == `REG_BUS_OWNED_BY_GFU || MST_I == 1'b1) ?
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wIO2_BUSMUX__DataWriteEnable : 1'bz;
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assign wCR2_TextureMappingEnabled = wCR2_ControlRegister[ `CR_EN_TEXTURE ];
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//--------------------------------------------------------
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//Control Unit Instance
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ControlUnit CU
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(
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.Clock(Clock),
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.Reset(Reset),
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.iControlRegister( wCR2_ControlRegister ),
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.oRamBusOwner( RamBusOwner ),
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.oGFUEnable( wCU2_GEO__GeometryFetchEnable ),
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.iTriggerAABBIURequest( wGEO2_CU__RequestAABBIU ),
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.iTriggerBIURequest( wGEO2_CU__RequestBIU ),
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.iTriggertTCCRequest( wGEO2_CU__RequestTCC ),
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.oUCodeEnable( wCU2__ExecuteMicroCode ),
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.oUCodeInstructioPointer( InitialCodeAddress ),
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.iUCodeDone( wCU2__MicrocodeExecutionDone ),
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.iIODone( wIO2__Done ),
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.oIOWritePixel( wCU2_IO__WritePixel ),
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.iUCodeReturnValue( wIFU2__MicroCodeReturnValue ),
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.iGEOSync( wGEO2_CU__Sync ),
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.iTFFDone( wGEO2_CU__TFFDone ),
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.oTriggerTFF( wCU2_GEO__TriggerTFF ),
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.MST_I( MST_I ),
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.oSetCurrentPitch( wCU2_GEO__SetPitch ),
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.iGFUDone( wGEO2_CU__GeometryUnitDone )
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);
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//--------------------------------------------------------
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MemoryUnit MEM
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(
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.Clock(Clock),
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.Reset(Reset),
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//Data Bus
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.iDataReadAddress1( wDataReadAddress0 ),
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.iDataReadAddress2( wDataReadAddress1 ),
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.oData1( wDataRead0 ),
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.oData2( wDataRead1 ),
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.iDataWriteEnable( DataWriteEnable ),
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.iDataWriteAddress( wDataWriteAddress ),
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.iData( w2MEM_WriteData ),
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//Instruction Bus
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.iInstructionReadAddress( wInstructionPointer ),
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.oInstruction( wEncodedInstruction ),
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.iInstructionWriteEnable( wIO2_MEM_InstructionWriteEnable ),
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.iInstructionWriteAddress( wIO2_MEM__InstructionWriteAddr ),
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.iInstruction( wIO2_MEM__ExternalInstruction ),
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.iControlRegister( CREG_I ),
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.oControlRegister( wCR2_ControlRegister )
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);
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////--------------------------------------------------------
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ExecutionUnit EXE
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(
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.Clock( Clock),
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.Reset( Reset ),
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.iInitialCodeAddress( InitialCodeAddress ),
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.iEncodedInstruction( wEncodedInstruction ),
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.oInstructionPointer( wInstructionPointer ),
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.iDataRead0( wDataRead0 ),
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.iDataRead1( wDataRead1 ),
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.iTrigger( wCU2__ExecuteMicroCode ),
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.oDataReadAddress0( wUCODE_RAMReadAddress0 ),
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.oDataReadAddress1( wUCODE_RAMReadAddress1 ),
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.oDataWriteEnable( wUCODE_RAMWriteEnable ),
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.oDataWriteAddress( wUCODE_RAMAddress ),
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.oDataBus( wUCODE_RAMBus ),
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.oReturnCode( wIFU2__MicroCodeReturnValue ),
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.oDone( wCU2__MicrocodeExecutionDone )
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);
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////--------------------------------------------------------
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wire wGEO2__RequestingTextures;
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wire w2IO_WriteBack_Set;
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GeometryUnit GEO
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(
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.Clock( Clock ),
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.Reset( Reset ),
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.iEnable( wCU2_GEO__GeometryFetchEnable ),
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.iTexturingEnable( wCR2_TextureMappingEnabled ),
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//Wires from IO
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.iData_WBM( wIO2__Data ),
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.iDataReady_WBM( wIO2__Done ),
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//Wires to WBM
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.oAddressWBM_Imm( wGEO2_IO__AddressOffset ),
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.oAddressWBM_fromMEM( wGEO2_IO__Adr_O_Pointer ),
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.oAddressWBM_IsImm( wGEO2_IO__AddrIsImm ),
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.oEnable_WBM( wGEO2_IO__EnableWBMaster ),
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.oSetAddressWBM( wGEO2_IO__SetAddress ),
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.oSetIOWriteBackAddr( w2IO_WriteBack_Set ),
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//Wires to CU
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.oRequest_AABBIU( wGEO2_CU__RequestAABBIU ),
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.oRequest_BIU( wGEO2_CU__RequestBIU ),
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.oRequest_TCC( wGEO2_CU__RequestTCC ),
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.oTFFDone( wGEO2_CU__TFFDone ),
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//Wires to RAM-Bus MUX
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.oRAMWriteAddress( w2IO__DataWriteAddress ),
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.oRAMWriteEnable( w2IO__Store ),
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//Wires from Execution Unit
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.iMicrocodeExecutionDone( wCU2__MicrocodeExecutionDone ),
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.iMicroCodeReturnValue( wIFU2__MicroCodeReturnValue ),
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.oSync( wGEO2_CU__Sync ),
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.iTrigger_TFF( wCU2_GEO__TriggerTFF ),
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.iBIUHit( wIFU2__MicroCodeReturnValue ),
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.oRequestingTextures( wGEO2__RequestingTextures ),
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.oDone( wGEO2_CU__GeometryUnitDone )
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);
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assign TGA_O = (wGEO2__RequestingTextures) ? 2'b1: 2'b0;
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//---------------------------------------------------------------------------------------------------
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wire[`DATA_ADDRESS_WIDTH-1:0] wIO2__DataReadAddress1;
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assign wDataReadAddress1 = (wCU2_IO__WritePixel == 0) ? wUCODE_RAMReadAddress1 : wIO2__DataReadAddress1;
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assign w2IO__EnableWBMaster = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__EnableWBMaster : wCU2_IO__WritePixel;
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assign w2IO__AddrIsImm = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__AddrIsImm : 1'b1;
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assign w2IO__AddressOffset = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__AddressOffset : 32'b0;
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assign w2IO__Adr_O_Pointer = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__Adr_O_Pointer : `OREG_PIXEL_PITCH;
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wire w2IO_MasterCycleType;
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assign w2IO_MasterCycleType = (wCU2_IO__WritePixel) ? `WB_SIMPLE_WRITE_CYCLE : `WB_SIMPLE_READ_CYCLE;
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317 |
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318 |
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319 |
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320 |
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assign w2IO__SetAddress = (wCU2_IO__WritePixel == 0 )? wGEO2_IO__SetAddress : wCU2_GEO__SetPitch;
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321 |
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|
322 |
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|
323 |
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IO_Unit IO
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324 |
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(
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325 |
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.Clock( Clock ),
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326 |
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.Reset( Reset ),
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327 |
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.iEnable( w2IO__EnableWBMaster ),
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328 |
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.iBusCyc_Type( w2IO_MasterCycleType ),
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329 |
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|
330 |
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.iStore( w2IO__Store ),
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331 |
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.iAdr_DataWriteBack( w2IO__DataWriteAddress ),
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332 |
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.iAdr_O_Set( w2IO__SetAddress ),
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333 |
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.iAdr_O_Imm( w2IO__AddressOffset ),
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334 |
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.iAdr_O_Type( w2IO__AddrIsImm ),
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335 |
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.iAdr_O_Pointer( w2IO__Adr_O_Pointer ),
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336 |
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.iReadDataBus( wDataRead0 ),
|
337 |
|
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.iReadDataBus2( wDataRead1 ),
|
338 |
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.iDat_O_Pointer( `OREG_PIXEL_COLOR ),
|
339 |
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|
340 |
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|
341 |
|
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.oDataReadAddress( wIO_2_MEM__DataReadAddress0 ),
|
342 |
|
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.oDataReadAddress2( wIO2__DataReadAddress1 ),
|
343 |
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.oDataWriteAddress( wIO2_BUSMUX__DataWriteAddress ),
|
344 |
|
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.oDataBus( wIO2_BUSMUX__Bus ),
|
345 |
|
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.oInstructionBus( wIO2_MEM__ExternalInstruction ),
|
346 |
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|
347 |
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.oDataWriteEnable( wIO2_BUSMUX__DataWriteEnable ),
|
348 |
|
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.oData( wIO2__Data ),
|
349 |
|
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.oInstructionWriteEnable( wIO2_MEM_InstructionWriteEnable ),
|
350 |
|
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.oInstructionWriteAddress( wIO2_MEM__InstructionWriteAddr ),
|
351 |
|
|
.iWriteBack_Set( w2IO_WriteBack_Set ),
|
352 |
|
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|
353 |
|
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.oDone( wIO2__Done ),
|
354 |
|
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.MST_I( MST_I ),
|
355 |
|
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//Wish Bone Interface
|
356 |
|
|
.DAT_I( DAT_I ),
|
357 |
|
|
.DAT_O( DAT_O ),
|
358 |
|
|
.ACK_I( ACK_I ),
|
359 |
|
|
.ACK_O( ACK_O ),
|
360 |
|
|
.ADR_O( ADR_O ),
|
361 |
|
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.ADR_I( ADR_I ),
|
362 |
|
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.WE_O( WE_O ),
|
363 |
|
|
.WE_I( WE_I ),
|
364 |
|
|
.STB_O( STB_O ),
|
365 |
|
|
.STB_I( STB_I ),
|
366 |
|
|
.CYC_O( CYC_O ),
|
367 |
|
|
.TGA_I( TGA_I ),
|
368 |
|
|
.CYC_I( CYC_I ),
|
369 |
|
|
.TGC_O( TGC_O )
|
370 |
|
|
|
371 |
|
|
|
372 |
|
|
);
|
373 |
|
|
//---------------------------------------------------------------------------------------------------
|
374 |
|
|
endmodule
|