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1 13 diegovalve
 
2
/**********************************************************************************
3
Theia, Ray Cast Programable graphic Processing Unit.
4
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
5
 
6
This program is free software; you can redistribute it and/or
7
modify it under the terms of the GNU General Public License
8
as published by the Free Software Foundation; either version 2
9
of the License, or (at your option) any later version.
10
 
11
This program is distributed in the hope that it will be useful,
12
but WITHOUT ANY WARRANTY; without even the implied warranty of
13
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
GNU General Public License for more details.
15
 
16
You should have received a copy of the GNU General Public License
17
along with this program; if not, write to the Free Software
18
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19
 
20
***********************************************************************************/
21
 
22
 
23
/*******************************************************************************
24
Module Description:
25
 
26
This is the Main test bench of the GPU. It simulates the behavior of
27
an external control unit or CPU that sends configuration information into DUT.
28
It also implements a second processs that simulates a Wishbone slave that sends
29
data from an external memory. These blocks are just behavioral CTE and therefore
30
are not meant to be synthethized.
31
 
32
*******************************************************************************/
33
`timescale 1ns / 1ps
34
`include "aDefinitions.v"
35
`define CONFIGURATION_PHASE                                             0
36
`define CTE_INITIAL_STATE                                                       0
37
`define CTE_IDLE                                                                                1
38
`define CTE_START_EU_CONFIGURATION_SEQUENCE     2
39
`define CTE_SEND_CONFIGURATION_PACKET                   3
40
`define CTE_ACK_CONFIGURATION_PACKET                    8
41
`define CTE_SEND_LIGHT_PACKET                                           13
42
`define CTE_ACK_LIGTH_PACKET                                            14
43
`define CTE_SEND_RAY_I_TASK                                             15
44
`define CTE_WAIT_FOR_TASK_ACK                                           16
45
`define WAIT_FOR_TASK_COMPLETE                                  17
46
`define CTE_PREPARE_NEW_TASK                                            18
47
`define CTE_RENDER_DONE                                                         19
48
`define CTE_READ_COLOR_DATA                                             20
49
`define CTE_GRANT_BUS_WRITE_PERMISION                   21
50
`define CTE_ACK_GRANT_BUS_PERMISION                             22
51
`define CTE_ACK_READ_COLOR_DATA                                 23
52
`define CTE_SEND_TEXTURE_DIMENSIONS                             24
53
`define CTE_ACK_TEXTURE_DIMENSIONS                              25
54
 
55
 
56
 
57
 
58
`define RESOLUTION_WIDTH                                                        (rSceneParameters[12] >> `SCALE)
59
`define RESOLUTION_HEIGHT                                                       (rSceneParameters[13] >> `SCALE)
60
`define RAYI_TASK                                                                               1
61
`define DELTA_ROW                                                                       (32'h1 << `SCALE)
62
`define DELTA_COL                                                                       (32'h1 << `SCALE)
63
 
64
module TestBench_Theia;
65
 
66
 
67
        //------------------------------------------------------------------------
68
        //**WARNING: Declare all of your varaibles at the begining
69
        //of the file. I hve noticed that sometimes the verilog
70
        //simulator allows you to use some regs even if they have not been 
71
        //previously declared, leadeing to crahses or unexpected behavior
72
        // Inputs
73
        reg Clock;
74
        reg Reset;
75
        reg ExternalBus_DataReady;
76
 
77
        // Outputs
78
        wire ExternalBus_Acknowledge;
79
        wire TaskCompleted;
80
 
81
        //CTE state machin logic
82
 
83
        reg[31:0] CurrentState,NextState;
84
        reg[3:0]  LightCount;
85
        reg[31:0] rLaneA,rLaneB,rLaneC,rLaneD;
86
        reg[16:0] CurrentTaskId;
87
        reg[31:0] CurrentPixelRow, CurrentPixelCol,CurrentRayType;
88
 
89
        reg CTE_WriteEnable;
90
        wire [`WB_WIDTH-1:0] DAT_O;
91
 
92
        reg                                             ACK_O;
93
        wire                                            ACK_I;
94
        wire [`WB_WIDTH-1:0] ADR_I,ADR_O;
95
        wire                                            WE_I,STB_I,CYC_I;
96
        reg CYC_O,WE_O,TGC_O,STB_O;
97
        wire [1:0] TGC_I;
98
        reg [1:0] TGA_O;
99
        wire [1:0] TGA_I;
100
        wire [31:0] DAT_I;
101
        integer ucode_file;
102
 
103
 
104
        reg [31:0] rInitialCol,rInitialRow;
105
        reg [31:0]       rControlRegister[2:0];
106
 
107
 
108
        integer file, log, r, a, b;
109
 
110
 
111
        reg [31:0]  rSceneParameters[31:0];
112
        reg [31:0]       rVertexBuffer[6000:0];
113
        reg [31:0]       rInstructionBuffer[25:0];
114
        `define TEXTURE_BUFFER_SIZE (256*256*3)
115
        reg [31:0]  rTextures[`TEXTURE_BUFFER_SIZE:0];            //Lets asume we use 256*256 textures
116
 
117
        //------------------------------------------------------------------------
118
        //Debug registers
119
        `define TASK_TIMEOUTMAX 50000
120
 
121
 
122
 
123
        //------------------------------------------------------------------------
124
 
125
 
126
 
127
                reg MST_O;
128
//---------------------------------------------------------------       
129
        THEIACORE THEIA
130
                (
131
                .CLK_I( Clock ),
132
                .RST_I( Reset ),
133
                .DAT_I( DAT_O ),
134
                .ADR_O( ADR_I ),
135
                .ACK_I( ACK_O ),
136
                .WE_O ( WE_I ),
137
                .STB_O( STB_I ),
138
                .CYC_O( CYC_I ),
139
                .CYC_I( CYC_O ),
140
                .TGC_O( TGC_I ),
141
                .MST_I( MST_O ),
142
                .TGA_I( TGA_O ),
143
                .ACK_O( ACK_I ),
144
                .ADR_I( ADR_O ),
145
                .DAT_O( DAT_I ),
146
                .WE_I(  WE_O  ),
147
 
148
                .STB_I( STB_O ),
149
                .TGA_O(TGA_I),
150
 
151
 
152
 
153
 
154
                //Control register
155
                .CREG_I( rControlRegister[0][15:0] )
156
                //Other stuff
157
 
158
 
159
 
160
 
161
 
162
 
163
        );
164
        //&
165
//---------------------------------------------------------------               
166
 
167
 
168
        //---------------------------------------------
169
        //generate the clock signal here
170
        always begin
171
                #5  Clock =  ! Clock;
172
 
173
        end
174
        //---------------------------------------------
175
 
176
reg [15:0] rTimeOut;
177
 
178
                `define MAX_INSTRUCTIONS 2
179
 
180
        initial begin
181
                // Initialize Inputs
182
 
183
 
184
                Clock                                   = 0;
185
                Reset                                   = 0;
186
                CTE_WriteEnable                 = 0;
187
                rLaneA                                  = 32'b0;
188
                rLaneB                                  = 32'b0;
189
                rLaneC                                  = 32'b0;
190
                rLaneD                                  = 32'b0;
191
                ExternalBus_DataReady = 0;
192
                rTimeOut              = 0;
193
 
194
 
195
        `ifdef DUMP_CODE
196
                $display("Opening dump file....\n");
197
                ucode_file = $fopen("TestBench.log","w");
198
        `endif
199
 
200
                //Read Config register values
201
                $readmemh("Creg.mem",rControlRegister);
202
 
203
                rInitialRow = rControlRegister[1];
204
                rInitialCol = rControlRegister[2];
205
        //  rControlRegister[0] = 32'b0;
206
 
207
                //Read configuration Data
208
                $readmemh("Params.mem", rSceneParameters        );
209
                //Read Scene Data
210
                $readmemh("Vertex.mem",rVertexBuffer);
211
                //Read Texture Data
212
                $readmemh("Textures.mem",rTextures);
213
                //Read instruction data
214
                $readmemh("Instructions.mem",rInstructionBuffer);
215
 
216
                $display("Control Register: %b",rControlRegister[0]);
217
 
218
 
219
 
220
                $display("Initial Row: %h",rInitialRow);
221
                $display("Initial Column: %h",rInitialCol);
222
 
223
                `LOGME"AABB min %h %h %h\n",rVertexBuffer[0],rVertexBuffer[1],rVertexBuffer[2]);
224
                `LOGME"AABB max %h %h %h\n",rVertexBuffer[3],rVertexBuffer[4],rVertexBuffer[5]);
225
                `LOGME"%h %h %h\n",rVertexBuffer[6],rVertexBuffer[7],rVertexBuffer[8]);
226
                `LOGME"%h %h %h\n",rVertexBuffer[9],rVertexBuffer[10],rVertexBuffer[11]);
227
                `LOGME"%h %h %h\n",rVertexBuffer[12],rVertexBuffer[13],rVertexBuffer[14]);
228
                `LOGME"%h %h %h\n",rVertexBuffer[15],rVertexBuffer[16],rVertexBuffer[17]);
229
                `LOGME"%h %h %h\n",rVertexBuffer[18],rVertexBuffer[19],rVertexBuffer[20]);
230
                //Open output file
231
                file = $fopen("Output.ppm");
232
                log  = $fopen("Simulation.log");
233
                $fwrite(log, "Simulation start time : %dns\n",$time);
234
                $fwrite(log, "Width : %d\n",`RESOLUTION_WIDTH);
235
                $fwrite(log, "Height : %d\n",`RESOLUTION_HEIGHT);
236
 
237
                $fwrite(file,"P3\n");
238
                $fwrite(file,"#This file was generated by Theia's RTL simulation\n");
239
                $fwrite(file,"%d %d\n",`RESOLUTION_WIDTH, `RESOLUTION_HEIGHT );
240
                $fwrite(file,"255\n");
241
 
242
                `LOGME"Running at %d X %d\n", `RESOLUTION_WIDTH, `RESOLUTION_HEIGHT);
243
 
244
                `LOGME"%h\n",rSceneParameters[0]);
245
                `LOGME"%h\n",rSceneParameters[1]);
246
                `LOGME"%h\n",rSceneParameters[2]);
247
 
248
                `LOGME"%h\n",rSceneParameters[3]);
249
                `LOGME"%h\n",rSceneParameters[4]);
250
                `LOGME"%h\n",rSceneParameters[5]);
251
 
252
                `LOGME"%h\n",rSceneParameters[6]);
253
                `LOGME"%h\n",rSceneParameters[7]);
254
                `LOGME"%h\n",rSceneParameters[8]);
255
                CurrentPixelRow = 0;
256
                CurrentPixelCol = 0;
257
                #10
258
                Reset = 1;
259
                ExternalBus_DataReady = 0;
260
 
261
                // Wait 100 ns for global reset to finish
262
                #100  Reset = 0;
263
 
264
        end
265
 
266
        reg [5:0] DataIndex;
267
        reg [31:0] ConfigurationPacketSize;
268
 
269
        reg [7:0] R,G,B;
270
 
271
 
272
//---------------------------------------------
273
 
274
always @ (posedge Clock)
275
begin
276
        rTimeOut = rTimeOut+1'b1;
277
        if (rTimeOut > `TASK_TIMEOUTMAX)
278
        begin
279
                 $display("%dns ERROR: THEIA Timed out after %d of inactivity\n",
280
                 $time(),rTimeOut);
281
                 $stop();
282
        end
283
end
284
 
285
reg [31:0] rSlaveData_O;
286
//reg [31:0] rOutputFrameBuffer[39000:0];
287
reg [31:0] rColor;
288
 
289
reg [7:0] Thingy;
290
//Wish-Bone Slave logic.
291
//
292
//This logic represents a WBS FSM. It will provide
293
//the memory for Vertex and Texture data.
294
//Vertex/Tetxure data is stored in a 4GB RAM.
295
//Vertex data starts at address 0 and ends at address 0x80_000_000.
296
//Texture data starts at address 0x80_000_000 and ends at address
297
//0xFFFFFFFF.
298
//The Bit 31, indcates wheather we look for vertex (b=0)
299
//or texture (b=1)
300
 
301
`define WBS_AFTER_RESET                                 0
302
`define WBS_MOINTOR_STB_I                               1
303
`define WBS_ACK_O                                                       2
304
`define WBS_MOINTOR_STB_I_NEG                   3
305
`define WBS_DONE                    4
306
 
307
        reg [7:0]                        WBSCurrentState,WBSNextState;
308
        reg [31:0]                       rAddress;
309
 
310
        always @(negedge Clock)
311
        begin
312
        if( Reset!=1 )
313
           WBSCurrentState = WBSNextState;
314
                  else
315
                          WBSCurrentState = `WBS_AFTER_RESET;
316
        end
317
 
318
 
319
 
320
        reg [31:0] rConvertedTextureAddress;
321
        //----------------------------------------------------------    
322
        always @(posedge Clock)
323
        begin
324
                case (WBSCurrentState)
325
                //----------------------------------------
326
                `WBS_AFTER_RESET:
327
                begin
328
                        ACK_O = 0;
329
                        rSlaveData_O = 32'b0;
330
 
331
                        WBSNextState = `WBS_MOINTOR_STB_I;
332
                end
333
                //----------------------------------------
334
                `WBS_MOINTOR_STB_I:
335
                begin
336
                        if ( STB_I == 1 )
337
                                WBSNextState = `WBS_ACK_O;
338
                        else
339
                                WBSNextState = `WBS_MOINTOR_STB_I;
340
                end
341
                //----------------------------------------
342
                `WBS_ACK_O:
343
                begin
344
                        if (WE_I == 0)
345
                        begin
346
 
347
                                rAddress = ADR_I;
348
                                if (TGA_I == 2'b01) //replace this by TGA_I
349
                                begin
350
                                 //Multiply pithc (3), Add 2 because the first 2 bytes are text Width, Height
351
                                rConvertedTextureAddress = {1'b0,rAddress[30:0]} + 2;
352
                                if (rConvertedTextureAddress >= `TEXTURE_BUFFER_SIZE)
353
                                        rConvertedTextureAddress = `TEXTURE_BUFFER_SIZE-1;
354
 
355
 
356
                                        rSlaveData_O = rTextures[  rConvertedTextureAddress ];
357
                                        `ifdef DEBUG
358
 
359
                                        `LOGME"WB SLAVE: MASTER Requested read from texture address: %h (%d)Data = %h \n",rAddress, rConvertedTextureAddress,DAT_O );
360
                                        `endif
361
                                end
362
                                else
363
                                begin
364
                                        Thingy = 0;
365
                                        rSlaveData_O = rVertexBuffer[ rAddress ];
366
                                        `ifdef DEBUG
367
                                        `LOGME"WB SLAVE: MASTER Requested read from vertex address: %h Data = %h\n",rAddress,DAT_O);
368
                                        `endif
369
                                end
370
 
371
                        end
372
                        else
373
                        begin
374
                        //      $display("Theia Writes value: %h @ %h (Time to process pixel %d Clock cycle)",DAT_I,ADR_I,rTimeOut);
375
 
376
 
377
                        if (Thingy == 0)
378
                        begin
379
                                $fwrite(file,"\n# %d %d\n",CurrentPixelRow,CurrentPixelCol);
380
                                $write(".");
381
                        end
382
 
383
                        Thingy = Thingy + 1;
384
                        if (CurrentPixelRow >=  `RESOLUTION_WIDTH)
385
                        begin
386
                                CurrentPixelRow = 0;
387
                                CurrentPixelCol = CurrentPixelCol + 1;
388
                                $display("]- %d (%d)",CurrentPixelCol,ADR_I);
389
                                $write("[");
390
                        end
391
 
392
                        if (Thingy == 3)
393
                        begin
394
                                CurrentPixelRow = CurrentPixelRow + 1;
395
                                Thingy = 0;
396
                        end
397
                                rTimeOut = 0;
398
                                R = ((DAT_I >> (`SCALE-8)) > 255) ? 255 : (DAT_I >>  (`SCALE-8));
399
                                $fwrite(file,"%d " , R );
400
 
401
                        end
402
 
403
 
404
                        ACK_O = 1;
405
                        //if (ADR_I >= `RESOLUTION_WIDTH*`RESOLUTION_HEIGHT*3)
406
                        if (CurrentPixelCol >= `RESOLUTION_HEIGHT)
407
                                WBSNextState = `WBS_DONE;
408
                        else
409
                                WBSNextState = `WBS_MOINTOR_STB_I_NEG;
410
                end
411
                //----------------------------------------
412
                `WBS_MOINTOR_STB_I_NEG:
413
                begin
414
                        if ( STB_I == 0 )
415
                        begin
416
                                ACK_O = 0;
417
                                WBSNextState = `WBS_MOINTOR_STB_I;
418
                        end
419
                        else
420
                                WBSNextState = `WBS_MOINTOR_STB_I_NEG;
421
                end
422
                //----------------------------------------
423
                `WBS_DONE:
424
                begin
425
                $display("RESOLUTION_WIDTH = %d,RESOLUTION_HEIGHT= %d",
426
                `RESOLUTION_WIDTH,`RESOLUTION_HEIGHT);
427
                $display("ADR_I = %d\n",ADR_I);
428
                        `LOGME"RENDER COMPLETE");
429
                        `LOGME"Closing File");
430
                        $fclose(file);
431
                        $fwrite(log, "Simulation end time : %dns\n",$time);
432
                        $fclose(log);
433
                        `LOGME"File Closed");
434
                        $stop();
435
                        $fclose(ucode_file);
436
                end
437
                //----------------------------------------
438
                default:
439
                begin
440
                $display("WTF????????????????????????");
441
                end
442
                endcase
443
        end     //end always
444
        //----------------------------------------------------------    
445
 
446
 
447
 
448
 
449
`define TAG_BLOCK_WRITE_CYCLE    2'b01
450
`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b01
451
`define TAG_DATA_ADDRESS_TYPE        2'b10
452
 
453
`define WBM_AFTER_RESET                                                 0
454
`define WBM_WRITE_INSTRUCTION_PHASE1            1
455
`define WBM_ACK_INSTRUCTION_PHASE1                      2
456
`define WBM_WRITE_INSTRUCTION_PHASE2            3
457
`define WBM_ACK_INSTRUCTION_PHASE2                      4
458
`define WBM_END_INSTRUCTION_WRITE_CYCLE   5
459
`define WBM_SEND_DATA_PHASE1                          6
460
`define WBM_ACK_DATA_PHASE1                           7
461
`define WBM_SEND_DATA_PHASE2                          8
462
`define WBM_ACK_DATA_PHASE2                           9
463
`define WBM_SEND_DATA_PHASE3                          10
464
`define WBM_ACK_DATA_PHASE3                           11
465
`define WBM_END_DATA_WRITE_CYCLE          12
466
`define WBM_DONE                          13
467
 
468
reg[31:0] rInstructionPointer;
469
reg[31:0] rAddressToSend;
470
reg[31:0] rDataAddress;
471
reg[31:0] rDataPointer;
472
 
473
reg IncIP,IncIA,IncDP;
474
reg rClearOutAddress;
475
//-----------------------------------------------------
476
always @ (posedge Clock or posedge rClearOutAddress)
477
begin
478
 
479
        if ( IncIA && ~rClearOutAddress)
480
                rAddressToSend = rAddressToSend + 1;
481
        else if (rClearOutAddress)
482
        begin
483
                if (TGA_O == `TAG_INSTRUCTION_ADDRESS_TYPE)
484
                        rAddressToSend =  {16'd1,16'd0};
485
                else
486
                        rAddressToSend = 0;
487
        end
488
 
489
 
490
end
491
//-----------------------------------------------------
492
always @ (posedge ACK_I or posedge Reset )
493
begin
494
 
495
        if ( ACK_I && ~Reset)
496
                rInstructionPointer = rInstructionPointer + 1;
497
        else if (Reset)
498
                rInstructionPointer = 0;
499
 
500
 
501
 
502
end
503
//-----------------------------------------------------
504
reg rResetDp;
505
 
506
always @ (posedge Clock or posedge rResetDp )
507
begin
508
 
509
        if ( ACK_I && ~rResetDp)//IncDP && ~Reset)
510
                rDataPointer = rDataPointer + 1;
511
        else if (rResetDp)
512
                rDataPointer =  32'b0;
513
 
514
 
515
end
516
//-----------------------------------------------------
517
 
518
 
519
 
520
 
521
assign DAT_O = ( MST_O == 1'b1 ) ? wMasteData_O : rSlaveData_O;
522
 
523
wire[31:0] wMasteData_O;
524
 
525
assign wMasteData_O = (TGA_O == `TAG_INSTRUCTION_ADDRESS_TYPE) ? rInstructionBuffer[rInstructionPointer] : rSceneParameters[ rDataPointer  ];
526
assign ADR_O = rAddressToSend;
527
 
528
        reg [7:0]                        WBMCurrentState,WBMNextState;
529
        reg [31:0]                       rWriteAddress;
530
 
531
        always @(posedge Clock or posedge Reset)
532
        begin
533
        if( Reset!=1 )
534
           WBMCurrentState = WBMNextState;
535
                  else
536
                          WBMCurrentState = `WBM_AFTER_RESET;
537
        end
538
 
539
                wire[31:0] wConfigurationPacketSize;
540
                assign wConfigurationPacketSize = rSceneParameters[2];
541
 
542
   reg [31:0]  InstructionIndex;
543
        reg [31:0]  InstructionWriteAddress;
544
        //Send the instructions now...
545
        //----------------------------------------------------------    
546
        always @(posedge Clock)
547
        begin
548
                case (WBMCurrentState)
549
                //----------------------------------------
550
                /*
551
                Wait until the reset secuence is complete to
552
                begin sending stuff.
553
                */
554
                `WBM_AFTER_RESET:
555
                begin
556
                        WE_O <=  0;
557
                        CYC_O <= 0;
558
                        TGC_O <= 0;
559
                        TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE;
560
                        STB_O <= 0;
561
                //      IncIP <= 0;
562
                        IncIA <= 0;
563
                        MST_O   <= 0;
564
                        IncDP <= 0;
565
                        rResetDp <= 1;
566
                        rClearOutAddress <= 1;
567
 
568
                        if (Reset == 0)
569
                                WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE1;
570
                        else
571
                                WBMNextState <= `WBM_AFTER_RESET;
572
                end
573
                //----------------------------------------
574
                /*
575
                CLOCK EDGE 0: MASTER presents a valid address on [ADR_O()]
576
                MASTER presents valid data on [DAT_O()]
577
                MASTER asserts [WE_O] to indicate a WRITE cycle.
578
                MASTER asserts [CYC_O] and [TGC_O()] to indicate the start of the cycle.
579
                MASTER asserts [STB_O] to indicate the start of the phase.
580
                */
581
                `WBM_WRITE_INSTRUCTION_PHASE1:
582
                begin
583
                        WE_O <=  1;                                                                                                     //Indicate write cycle
584
                        CYC_O <= 1;                                                                                                     //Start of the cycle
585
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;                                                //TAG CYCLE: 10 indicated multiple write Cycle
586
                        TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE;                 //TAG Address: 01 means instruction address type.
587
                        STB_O <= ~ACK_I;                                                                                        //Start of phase (you put this in zero to introduce wait cycles)
588
                //      IncIP <= 0;
589
                        IncIA <= 0;
590
                        MST_O   <= 1;
591
                        IncDP <= 0;
592
                        rResetDp <= 1;
593
                        rClearOutAddress <= 0;
594
 
595
 
596
 
597
                        if ( ACK_I )
598
                                WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE1;
599
                        else
600
                                WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE1;
601
 
602
                end
603
                //----------------------------------------
604
                `WBM_ACK_INSTRUCTION_PHASE1:
605
                begin
606
                        WE_O <=  1;
607
                        CYC_O <= 1;
608
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
609
                        TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE;
610
                        STB_O <= 0;      //*                                                                                     //Negate STB_O in response to ACK_I
611
                //      IncIP <= 1;     //*                                                                                     //Increment local inst pointer to send the next 32 bits                                 
612
                        IncIA <= 0;                                                                                                      //leave the instruction write address the same
613
                        MST_O   <= 1;
614
                        IncDP <= 0;
615
                        rResetDp <= 1;
616
                        rClearOutAddress <= 0;
617
 
618
                        if (ACK_I == 0)
619
                                WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE2;
620
                        else
621
                                WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE1;
622
                end
623
                //----------------------------------------
624
                `WBM_WRITE_INSTRUCTION_PHASE2:
625
                begin
626
                        WE_O <=  1;
627
                        CYC_O <= 1;
628
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
629
                        TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE;
630
                        STB_O <= ~ACK_I;
631
                //      IncIP <= 0;
632
                        IncIA <= 0;
633
                        MST_O   <= 1;
634
                        IncDP <= 0;
635
                        rResetDp <= 1;
636
                        rClearOutAddress <= 0;
637
 
638
 
639
                        if ( ACK_I )
640
                                WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE2;
641
                        else
642
                                WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE2;
643
 
644
                end
645
                //----------------------------------------
646
                `WBM_ACK_INSTRUCTION_PHASE2:
647
                begin
648
                        WE_O <=  1;
649
                        CYC_O <= 0;
650
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
651
                        TGA_O <= `TAG_INSTRUCTION_ADDRESS_TYPE;
652
                        STB_O <= 0;      //*
653
 
654
                        MST_O   <= 1;
655
                        IncDP <= 0;
656
                        rResetDp <= 1;
657
 
658
 
659
 
660
                if (rInstructionPointer >= 4)
661
                begin
662
                                IncIA <= 0;//*   
663
                                rClearOutAddress <= 1;
664
                                WBMNextState    <= `WBM_SEND_DATA_PHASE1;
665
                end
666
                else
667
                begin
668
                                IncIA <= 1;//*  
669
                                rClearOutAddress <= 0;
670
                                WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE1;
671
                end
672
 
673
                end
674
        //****************************************
675
        `WBM_SEND_DATA_PHASE1:
676
                begin
677
                        WE_O <=  1;                                                                                                     //Indicate write cycle
678
                        CYC_O <= 1;                                                                                                     //Start of the cycle
679
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;                                                //TAG CYCLE: 10 indicated multiple write Cycle
680
                        TGA_O <= `TAG_DATA_ADDRESS_TYPE;                //TAG Address: 01 means instruction address type.
681
                        STB_O <= ~ACK_I;                                                                                        //Start of phase (you put this in zero to introduce wait cycles)
682
                //      IncIP <= 0;
683
                        IncIA <= 0;
684
                        MST_O   <= 1;
685
                        IncDP <= 0;
686
                        rResetDp <= 0;
687
                        rClearOutAddress <= 0;
688
 
689
 
690
 
691
                        if ( ACK_I )
692
                                WBMNextState <= `WBM_ACK_DATA_PHASE1;
693
                        else
694
                                WBMNextState <= `WBM_SEND_DATA_PHASE1;
695
 
696
                end
697
                //----------------------------------------
698
                `WBM_ACK_DATA_PHASE1:
699
                begin
700
                        WE_O <=  1;
701
                        CYC_O <= 1;
702
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
703
                        TGA_O <= `TAG_DATA_ADDRESS_TYPE;
704
                        STB_O <= 0;      //*                                                                                     //Negate STB_O in response to ACK_I
705
                //      IncIP <= 1;     //*                                                                                     //Increment local inst pointer to send the next 32 bits                                 
706
                        IncIA <= 0;                                                                                                      //leave the instruction write address the same
707
                        MST_O   <= 1;
708
                        IncDP <= 0;
709
                        rResetDp <= 0;
710
                        rClearOutAddress <= 0;
711
 
712
                        if (ACK_I == 0)
713
                                WBMNextState <= `WBM_SEND_DATA_PHASE2;
714
                        else
715
                                WBMNextState <= `WBM_ACK_DATA_PHASE1;
716
                end
717
                //----------------------------------------
718
                `WBM_SEND_DATA_PHASE2:
719
                begin
720
                        WE_O <=  1;
721
                        CYC_O <= 1;
722
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
723
                        TGA_O <= `TAG_DATA_ADDRESS_TYPE;
724
                        STB_O <= ~ACK_I;
725
                //      IncIP <= 0;
726
                        IncIA <= 0;
727
                        MST_O   <= 1;
728
                        IncDP <= 0;
729
                        rResetDp <= 0;
730
                        rClearOutAddress <= 0;
731
 
732
 
733
                        if ( ACK_I )
734
                                WBMNextState <= `WBM_ACK_DATA_PHASE2;
735
                        else
736
                                WBMNextState <= `WBM_SEND_DATA_PHASE2;
737
 
738
                end
739
                //----------------------------------------
740
                `WBM_ACK_DATA_PHASE2:
741
                begin
742
                        WE_O <=  1;
743
                        CYC_O <= 1;
744
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
745
                        TGA_O <= `TAG_DATA_ADDRESS_TYPE;
746
                        STB_O <= 0;      //*
747
                        IncIA <= 0;
748
                        MST_O   <= 1;
749
                        IncDP <= 0;//*           
750
                        rResetDp <= 0;
751
                        rClearOutAddress <= 0;
752
 
753
                        if (ACK_I == 0)
754
                                WBMNextState <= `WBM_SEND_DATA_PHASE3;
755
                        else
756
                                WBMNextState <= `WBM_ACK_DATA_PHASE2;
757
 
758
                end
759
                //----------------------------------------
760
                `WBM_SEND_DATA_PHASE3:
761
                begin
762
                        WE_O <=  1;
763
                        CYC_O <= 1;
764
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
765
                        TGA_O <= `TAG_DATA_ADDRESS_TYPE;
766
                        STB_O <= ~ACK_I;
767
                //      IncIP <= 0;
768
                        IncIA <= 0;
769
                        MST_O   <= 1;
770
                        IncDP <= 0;
771
                        rResetDp <= 0;
772
                        rClearOutAddress <= 0;
773
 
774
 
775
                        if ( ACK_I )
776
                                WBMNextState <= `WBM_ACK_DATA_PHASE3;
777
                        else
778
                                WBMNextState <= `WBM_SEND_DATA_PHASE3;
779
 
780
                end
781
                //----------------------------------------
782
                `WBM_ACK_DATA_PHASE3:
783
                begin
784
                        WE_O <=  1;
785
                        CYC_O <= 1;
786
                        TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
787
                        TGA_O <= `TAG_DATA_ADDRESS_TYPE;
788
                        STB_O <= 0;      //*
789
                        IncIA <= 0;
790
                        MST_O   <= 1;
791
                        IncDP <= 1;//*          
792
                        rResetDp <= 0;
793
                        rClearOutAddress <= 0;
794
 
795
                        WBMNextState <= `WBM_END_DATA_WRITE_CYCLE;
796
 
797
                end
798
                //----------------------------------------
799
                `WBM_END_DATA_WRITE_CYCLE:
800
                begin
801
                        WE_O <=  0;
802
                        CYC_O <= 0;      //*                                                                                             
803
                        TGC_O <= 0;
804
                        TGA_O <= 0;
805
                        STB_O <= 0;
806
                        IncIA <= 1;//*          
807
                        MST_O   <= 1;
808
                        IncDP <= 0;
809
                        rResetDp <= 0;
810
                        rClearOutAddress <= 0;
811
 
812
                        $display("rDataPointer = %d\n",rDataPointer);
813
                        if (rDataPointer > wConfigurationPacketSize*3)
814
                                WBMNextState    <= `WBM_DONE;
815
                        else
816
                                WBMNextState <= `WBM_SEND_DATA_PHASE1;
817
 
818
                end
819
 
820
                //----------------------------------------
821
                /*
822
                Here everything is ready so just start!
823
                */
824
                `WBM_DONE:
825
                begin
826
                        WE_O <=  0;
827
                        CYC_O <= 0;
828
                        TGC_O <= 0;
829
                        TGA_O <= 0;
830
                        STB_O <= 0;
831
                        IncIA <= 0;
832
                        MST_O   <= 0;
833
                        IncDP <= 0;
834
                        rResetDp <= 1;
835
                        rClearOutAddress <= 1;
836
 
837
                        WBMNextState <= `WBM_DONE;
838
                end
839
                //----------------------------------------
840
 
841
 
842
                endcase
843
        end     //end always
844
        //----------------------------------------------------------    
845
 
846
 
847
 
848
 
849
 
850
endmodule
851
 

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