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`timescale 1ns / 1ps
`include "aDefinitions.v"
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010  Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
***********************************************************************************/
//------------------------------------------------
module FFD_POSEDGE_ASYNC_RESET # ( parameter SIZE=`WIDTH )
        (
        input wire Clock,
        input wire Clear,
        input wire [SIZE-1:0] D,
        output reg [SIZE-1:0] Q
        );
 
  always @(posedge Clock or posedge Clear)
    begin
           if (Clear)
        Q = 0;
      else
        Q = D;
    end
endmodule
//----------------------------------------------------
module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
(
        input wire                              Clock,
        input wire                              Reset,
        input wire                              Enable,
        input wire [SIZE-1:0]    D,
        output reg [SIZE-1:0]    Q
);
 
 
always @ (posedge Clock)
begin
        if ( Reset )
                Q <= `WIDTH'b0;
        else
        begin
                if (Enable)
                        Q <= D;
        end
 
end//always
 
endmodule
//------------------------------------------------
module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
(
input wire Clock, Reset,
input wire [SIZE-1:0] Initial,
input wire Enable,
output reg [SIZE-1:0] Q
);
 
 
  always @(posedge Clock )
  begin
      if (Reset)
        Q = Initial;
      else
                begin
                if (Enable)
                        Q = Q + 1;
 
                end
  end
 
endmodule
 
 
module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
 (
 input wire [1:0] Sel,
 input wire [SIZE-1:0]I1, I2, I3,I4,
 output reg [SIZE-1:0] O1
 );
 
always @( * )
 
  begin
 
    case (Sel)
 
      2'b00: O1 = I1;
      2'b01: O1 = I2;
                2'b10: O1 = I3;
                2'b11: O1 = I4;
                default: O1 = SIZE-1'b0;
 
    endcase
 
  end
 
endmodule
 
//--------
module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
( input wire Clock,
  input wire Reset,
  input wire[SIZE-1:0] Initial,
  input wire      Enable,
  output wire[SIZE-1:0] O
);
 
reg [SIZE-1:0] tmp;
 
 
  always @(posedge Clock)
  begin
  if (Reset)
                tmp <= Initial;
        else
        begin
                if (Enable)
                begin
                        if (tmp[SIZE-1])
                                tmp <= Initial;
                        else
                                tmp <= tmp << 1;
                end
        end
  end
 
 
    assign O  = tmp;
endmodule
//------------------------------------------------
module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
 (
 input wire [2:0] Sel,
 input wire [SIZE-1:0]I1, I2, I3,
 output reg [SIZE-1:0] O1
 );
 
always @( * )
 
  begin
 
    case (Sel)
 
      3'b001: O1 = I1;
      3'b010: O1 = I2;
                3'b100: O1 = I3;
                default: O1 = SIZE-1'b0;
 
    endcase
 
  end
 
endmodule
//------------------------------------------------
module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
( input wire Clock,
  input wire Reset,
  input wire[SIZE-1:0] Initial,
  input wire      Enable,
  output wire[SIZE-1:0] O
);
 
reg [SIZE-1:0] tmp;
 
 
  always @(posedge Clock)
  begin
  if (Reset)
                tmp <= Initial;
        else
        begin
                if (Enable)
                        tmp <= tmp << 1;
        end
  end
 
 
    assign O  = tmp;
endmodule
//------------------------------------------------
//------------------------------------------------
module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
( input wire Clock,
  input wire Reset,
  input wire[SIZE-1:0] Initial,
  input wire      Enable,
  output wire[SIZE-1:0] O
);
 
reg [SIZE-1:0] tmp;
 
 
  always @(posedge Clock)
  begin
  if (Reset || tmp[SIZE-1])
                tmp <= Initial;
        else
        begin
                if (Enable)
                        tmp <= tmp << 1;
        end
  end
 
 
    assign O  = tmp;
endmodule
//-----------------------------------------------------------
/*
        Sorry forgot how this flop is called.
        Any way Truth table is this
 
        Q       S       Q_next R
 
 
        1       0        1                0
        1       1       1                0
        X       X       0                 1
 
        The idea is that it toggles from 0 to 1 when S = 1, but if it
        gets another S = 1, it keeps the output to 1.
*/
module FFToggleOnce_1Bit
(
        input wire Clock,
        input wire Reset,
        input wire Enable,
        input wire S,
        output reg Q
 
);
 
 
reg Q_next;
 
always @ (negedge Clock)
begin
        Q <= Q_next;
end
 
always @ ( posedge Clock )
begin
        if (Reset)
                Q_next <= 0;
        else if (Enable)
                Q_next <= (S && !Q) || Q;
        else
                Q_next <= Q;
end
endmodule
 
//--------------------------------------------------------------
//************************OLD MODS***************************//
//************************OLD MODS***************************//
//************************OLD MODS***************************//
//************************OLD MODS***************************//
//-----------------------------------------------------------
 
/*
module UpCounterXXX_16
(
input wire Clock, Reset,
input wire [15:0] Initial,
output reg [15:0] Q
);
 
 
  always @(posedge Clock )
    begin
      if (Reset)
        Q = Initial;
      else
        Q = Q + 1'b1;
      end
 
endmodule
*/
//-----------------------------------------------------------
module UpCounter_16E
(
input wire Clock,
input wire Reset,
input wire [15:0] Initial,
input wire Enable,
output wire [15:0] Q
);
        reg [15:0] Temp;
 
 
  always @(posedge Clock or posedge Reset)
  begin
      if (Reset)
         Temp = Initial;
      else
                        if (Enable)
                                Temp =  Temp + 1'b1;
  end
        assign Q = Temp;
 
endmodule
//-----------------------------------------------------------
module UpCounter_32
(
input wire Clock,
input wire Reset,
input wire [31:0] Initial,
input wire Enable,
output wire [31:0] Q
);
        reg [31:0] Temp;
 
 
  always @(posedge Clock or posedge Reset)
  begin
      if (Reset)
                begin
         Temp = Initial;
                end
      else
                begin
                        if (Enable)
                        begin
                                Temp =  Temp + 1'b1;
                        end
                end
  end
        assign Q = Temp;
 
endmodule
//-----------------------------------------------------------
module UpCounter_3
(
input wire Clock,
input wire Reset,
input wire [2:0] Initial,
input wire Enable,
output wire [2:0] Q
);
        reg [2:0] Temp;
 
 
  always @(posedge Clock or posedge Reset)
  begin
      if (Reset)
         Temp = Initial;
      else
                        if (Enable)
                                Temp =  Temp + 3'b1;
  end
        assign Q = Temp;
 
endmodule
 
 
module FFD32_POSEDGE
(
        input wire Clock,
        input wire[31:0] D,
        output reg[31:0] Q
);
 
        always @ (posedge Clock)
                Q <= D;
 
endmodule
 
//------------------------------------------------
/*
module FF_OPCODE_POSEDGE_SYNCRONOUS_RESET
        (
        input wire Clock,
        input wire Clear,
        input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
        output reg[`INSTRUCTION_OP_LENGTH-1:0]  Q
        );
 
  always @(posedge Clock or posedge Clear)
    begin
           if (Clear)
        Q = `INSTRUCTION_OP_LENGTH'b0;
      else
        Q = D;
    end
endmodule
//------------------------------------------------
 
module FF32_POSEDGE_SYNCRONOUS_RESET
        (
        input wire Clock,
        input wire Clear,
        input wire[31:0] D,
        output reg[31:0]  Q
        );
 
  always @(posedge Clock or posedge Clear)
    begin
           if (Clear)
        Q = 32'b0;
      else
        Q = D;
    end
endmodule
//------------------------------------------------
 
module FF16_POSEDGE_SYNCRONOUS_RESET
        (
        input wire Clock,
        input wire Clear,
        input wire[15:0] D,
        output reg[15:0]  Q
        );
 
  always @(posedge Clock or posedge Clear)
    begin
           if (Clear)
        Q = 16'b0;
      else
        Q = D;
    end
endmodule
*/
//------------------------------------------------
module MUXFULLPARALELL_96bits_2SEL
 (
 input wire Sel,
 input wire [95:0]I1, I2,
 output reg [95:0] O1
 );
 
 
 
always @( * )
 
  begin
 
    case (Sel)
 
      1'b0: O1 = I1;
      1'b1: O1 = I2;
 
    endcase
 
  end
 
endmodule
//------------------------------------------------
 
module MUXFULLPARALELL_16bits_2SEL_X
 (
 input wire [1:0] Sel,
 input wire [15:0]I1, I2, I3,
 output reg [15:0] O1
 );
 
 
 
always @( * )
 
  begin
 
    case (Sel)
 
      2'b00: O1 = I1;
      2'b01: O1 = I2;
                2'b10: O1 = I3;
                default: O1 = 16'b0;
 
    endcase
 
  end
 
endmodule
//------------------------------------------------
module MUXFULLPARALELL_16bits_2SEL
 (
 input wire Sel,
 input wire [15:0]I1, I2,
 output reg [15:0] O1
 );
 
 
 
always @( * )
 
  begin
 
    case (Sel)
 
      1'b0: O1 = I1;
      1'b1: O1 = I2;
 
    endcase
 
  end
 
endmodule
 
 
//------------------------------------------------
/*
module MUXFULLPARALELL_1Bit_1SEL
 (
 input wire Sel,
 input wire I1, I2,
 output reg O1
 );
 
 
 
always @( * )
 
  begin
 
    case (Sel)
 
      1'b0: O1 = I1;
      1'b1: O1 = I2;
 
    endcase
 
  end
 
endmodule
*/
//--------------------------------------------------------------
/*
module FFD_OPCODE_POSEDGE
(
        input wire Clock,
        input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
        output reg[`INSTRUCTION_OP_LENGTH-1:0] Q
);
 
        always @ (posedge Clock)
                Q <= D;
 
endmodule
*/
//--------------------------------------------------------------
/*
module FFD16_POSEDGE
(
        input wire Clock,
        input wire[15:0] D,
        output reg[15:0] Q
);
 
        always @ (posedge Clock)
                Q <= D;
 
endmodule
*/
//--------------------------------------------------------------
 
  module FFT1
  (
   input wire D,
   input wire Clock,
   input wire Reset ,
   output reg Q
 );
 
  always @ ( posedge Clock or posedge Reset )
  begin
 
        if (Reset)
        begin
    Q <= 1'b0;
   end
        else
        begin
                if (D)
                        Q <=  ! Q;
        end
 
  end//always
 
 endmodule
//--------------------------------------------------------------

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Subversion Repositories theia_gpu

[/] [theia_gpu/] [branches/] [beta_1.2/] [rtl/] [Collaterals/] [Collaterals.v] - Blame information for rev 112

Line No.	Rev	Author	Line
1	36	diegovalve	`timescale 1ns / 1ps
2			`include "aDefinitions.v"
3			`/**********************************************************************************`
4			`Theia, Ray Cast Programable graphic Processing Unit.`
5			`Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)`
6
7			`This program is free software; you can redistribute it and/or`
8			`modify it under the terms of the GNU General Public License`
9			`as published by the Free Software Foundation; either version 2`
10			`of the License, or (at your option) any later version.`
11
12			`This program is distributed in the hope that it will be useful,`
13			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
15			`GNU General Public License for more details.`
16
17			`You should have received a copy of the GNU General Public License`
18			`along with this program; if not, write to the Free Software`
19			`Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
20
21			`***********************************************************************************/`
22			`//------------------------------------------------`
23			module FFD_POSEDGE_ASYNC_RESET # ( parameter SIZE=`WIDTH )
24			`(`
25			`input wire Clock,`
26			`input wire Clear,`
27			`input wire [SIZE-1:0] D,`
28			`output reg [SIZE-1:0] Q`
29			`);`
30
31			`always @(posedge Clock or posedge Clear)`
32			`begin`
33			`if (Clear)`
34			`Q = 0;`
35			`else`
36			`Q = D;`
37			`end`
38			`endmodule`
39			`//----------------------------------------------------`
40			module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
41			`(`
42			`input wire Clock,`
43			`input wire Reset,`
44			`input wire Enable,`
45			`input wire [SIZE-1:0] D,`
46			`output reg [SIZE-1:0] Q`
47			`);`
48
49
50			`always @ (posedge Clock)`
51			`begin`
52			`if ( Reset )`
53			Q <= `WIDTH'b0;
54			`else`
55			`begin`
56			`if (Enable)`
57			`Q <= D;`
58			`end`
59
60			`end//always`
61
62			`endmodule`
63			`//------------------------------------------------`
64			module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
65			`(`
66			`input wire Clock, Reset,`
67			`input wire [SIZE-1:0] Initial,`
68			`input wire Enable,`
69			`output reg [SIZE-1:0] Q`
70			`);`
71
72
73			`always @(posedge Clock )`
74			`begin`
75			`if (Reset)`
76			`Q = Initial;`
77			`else`
78			`begin`
79			`if (Enable)`
80			`Q = Q + 1;`
81
82			`end`
83			`end`
84
85			`endmodule`
86	70	diegovalve
87	76	diegovalve
88	36	diegovalve	module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
89			`(`
90			`input wire [1:0] Sel,`
91	76	diegovalve	`input wire [SIZE-1:0]I1, I2, I3,I4,`
92	36	diegovalve	`output reg [SIZE-1:0] O1`
93			`);`
94
95			`always @( * )`
96
97			`begin`
98
99			`case (Sel)`
100
101			`2'b00: O1 = I1;`
102			`2'b01: O1 = I2;`
103	76	diegovalve	`2'b10: O1 = I3;`
104			`2'b11: O1 = I4;`
105	36	diegovalve	`default: O1 = SIZE-1'b0;`
106
107			`endcase`
108
109			`end`
110
111			`endmodule`
112
113	76	diegovalve	`//--------`
114			module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
115			`( input wire Clock,`
116			`input wire Reset,`
117			`input wire[SIZE-1:0] Initial,`
118			`input wire Enable,`
119			`output wire[SIZE-1:0] O`
120			`);`
121
122			`reg [SIZE-1:0] tmp;`
123
124
125			`always @(posedge Clock)`
126			`begin`
127			`if (Reset)`
128			`tmp <= Initial;`
129			`else`
130			`begin`
131			`if (Enable)`
132			`begin`
133			`if (tmp[SIZE-1])`
134			`tmp <= Initial;`
135			`else`
136			`tmp <= tmp << 1;`
137			`end`
138			`end`
139			`end`
140
141
142			`assign O = tmp;`
143			`endmodule`
144	36	diegovalve	`//------------------------------------------------`
145			module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
146			`(`
147			`input wire [2:0] Sel,`
148			`input wire [SIZE-1:0]I1, I2, I3,`
149			`output reg [SIZE-1:0] O1`
150			`);`
151
152			`always @( * )`
153
154			`begin`
155
156			`case (Sel)`
157
158			`3'b001: O1 = I1;`
159			`3'b010: O1 = I2;`
160			`3'b100: O1 = I3;`
161			`default: O1 = SIZE-1'b0;`
162
163			`endcase`
164
165			`end`
166
167			`endmodule`
168			`//------------------------------------------------`
169			module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
170			`( input wire Clock,`
171			`input wire Reset,`
172			`input wire[SIZE-1:0] Initial,`
173			`input wire Enable,`
174			`output wire[SIZE-1:0] O`
175			`);`
176
177			`reg [SIZE-1:0] tmp;`
178
179
180			`always @(posedge Clock)`
181			`begin`
182			`if (Reset)`
183			`tmp <= Initial;`
184			`else`
185			`begin`
186			`if (Enable)`
187			`tmp <= tmp << 1;`
188			`end`
189			`end`
190
191
192			`assign O = tmp;`
193			`endmodule`
194			`//------------------------------------------------`
195			`//------------------------------------------------`
196			module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
197			`( input wire Clock,`
198			`input wire Reset,`
199			`input wire[SIZE-1:0] Initial,`
200			`input wire Enable,`
201			`output wire[SIZE-1:0] O`
202			`);`
203
204			`reg [SIZE-1:0] tmp;`
205
206
207			`always @(posedge Clock)`
208			`begin`
209			`if (Reset \|\| tmp[SIZE-1])`
210			`tmp <= Initial;`
211			`else`
212			`begin`
213			`if (Enable)`
214			`tmp <= tmp << 1;`
215			`end`
216			`end`
217
218
219			`assign O = tmp;`
220			`endmodule`
221			`//-----------------------------------------------------------`
222			`/*`
223			`Sorry forgot how this flop is called.`
224			`Any way Truth table is this`
225
226			`Q S Q_next R`
227
228
229			`1 0 1 0`
230			`1 1 1 0`
231			`X X 0 1`
232
233			`The idea is that it toggles from 0 to 1 when S = 1, but if it`
234			`gets another S = 1, it keeps the output to 1.`
235			`*/`
236			`module FFToggleOnce_1Bit`
237			`(`
238			`input wire Clock,`
239			`input wire Reset,`
240			`input wire Enable,`
241			`input wire S,`
242			`output reg Q`
243
244			`);`
245
246
247			`reg Q_next;`
248
249			`always @ (negedge Clock)`
250			`begin`
251			`Q <= Q_next;`
252			`end`
253
254			`always @ ( posedge Clock )`
255			`begin`
256			`if (Reset)`
257			`Q_next <= 0;`
258			`else if (Enable)`
259			`Q_next <= (S && !Q) \|\| Q;`
260			`else`
261			`Q_next <= Q;`
262			`end`
263			`endmodule`
264
265			`//--------------------------------------------------------------`
266			`//**********************OLD MODS*************************//`
267			`//**********************OLD MODS*************************//`
268			`//**********************OLD MODS*************************//`
269			`//**********************OLD MODS*************************//`
270			`//-----------------------------------------------------------`
271
272			`/*`
273			`module UpCounterXXX_16`
274			`(`
275			`input wire Clock, Reset,`
276			`input wire [15:0] Initial,`
277			`output reg [15:0] Q`
278			`);`
279
280
281			`always @(posedge Clock )`
282			`begin`
283			`if (Reset)`
284			`Q = Initial;`
285			`else`
286			`Q = Q + 1'b1;`
287			`end`
288
289			`endmodule`
290			`*/`
291			`//-----------------------------------------------------------`
292			`module UpCounter_16E`
293			`(`
294			`input wire Clock,`
295			`input wire Reset,`
296			`input wire [15:0] Initial,`
297			`input wire Enable,`
298			`output wire [15:0] Q`
299			`);`
300			`reg [15:0] Temp;`
301
302
303			`always @(posedge Clock or posedge Reset)`
304			`begin`
305			`if (Reset)`
306			`Temp = Initial;`
307			`else`
308			`if (Enable)`
309			`Temp = Temp + 1'b1;`
310			`end`
311			`assign Q = Temp;`
312
313			`endmodule`
314			`//-----------------------------------------------------------`
315			`module UpCounter_32`
316			`(`
317			`input wire Clock,`
318			`input wire Reset,`
319			`input wire [31:0] Initial,`
320			`input wire Enable,`
321			`output wire [31:0] Q`
322			`);`
323			`reg [31:0] Temp;`
324
325
326			`always @(posedge Clock or posedge Reset)`
327			`begin`
328			`if (Reset)`
329			`begin`
330			`Temp = Initial;`
331			`end`
332			`else`
333			`begin`
334			`if (Enable)`
335			`begin`
336			`Temp = Temp + 1'b1;`
337			`end`
338			`end`
339			`end`
340			`assign Q = Temp;`
341
342			`endmodule`
343			`//-----------------------------------------------------------`
344			`module UpCounter_3`
345			`(`
346			`input wire Clock,`
347			`input wire Reset,`
348			`input wire [2:0] Initial,`
349			`input wire Enable,`
350			`output wire [2:0] Q`
351			`);`
352			`reg [2:0] Temp;`
353
354
355			`always @(posedge Clock or posedge Reset)`
356			`begin`
357			`if (Reset)`
358			`Temp = Initial;`
359			`else`
360			`if (Enable)`
361			`Temp = Temp + 3'b1;`
362			`end`
363			`assign Q = Temp;`
364
365			`endmodule`
366
367
368			`module FFD32_POSEDGE`
369			`(`
370			`input wire Clock,`
371			`input wire[31:0] D,`
372			`output reg[31:0] Q`
373			`);`
374
375			`always @ (posedge Clock)`
376			`Q <= D;`
377
378			`endmodule`
379
380			`//------------------------------------------------`
381	70	diegovalve	`/*`
382	36	diegovalve	`module FF_OPCODE_POSEDGE_SYNCRONOUS_RESET`
383			`(`
384			`input wire Clock,`
385			`input wire Clear,`
386			input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
387			output reg[`INSTRUCTION_OP_LENGTH-1:0] Q
388			`);`
389
390			`always @(posedge Clock or posedge Clear)`
391			`begin`
392			`if (Clear)`
393			Q = `INSTRUCTION_OP_LENGTH'b0;
394			`else`
395			`Q = D;`
396			`end`
397			`endmodule`
398			`//------------------------------------------------`
399	70	diegovalve
400	36	diegovalve	`module FF32_POSEDGE_SYNCRONOUS_RESET`
401			`(`
402			`input wire Clock,`
403			`input wire Clear,`
404			`input wire[31:0] D,`
405			`output reg[31:0] Q`
406			`);`
407
408			`always @(posedge Clock or posedge Clear)`
409			`begin`
410			`if (Clear)`
411			`Q = 32'b0;`
412			`else`
413			`Q = D;`
414			`end`
415			`endmodule`
416			`//------------------------------------------------`
417	63	diegovalve
418	36	diegovalve	`module FF16_POSEDGE_SYNCRONOUS_RESET`
419			`(`
420			`input wire Clock,`
421			`input wire Clear,`
422			`input wire[15:0] D,`
423			`output reg[15:0] Q`
424			`);`
425
426			`always @(posedge Clock or posedge Clear)`
427			`begin`
428			`if (Clear)`
429			`Q = 16'b0;`
430			`else`
431			`Q = D;`
432			`end`
433			`endmodule`
434	70	diegovalve	`*/`
435	36	diegovalve	`//------------------------------------------------`
436			`module MUXFULLPARALELL_96bits_2SEL`
437			`(`
438			`input wire Sel,`
439			`input wire [95:0]I1, I2,`
440			`output reg [95:0] O1`
441			`);`
442
443
444
445			`always @( * )`
446
447			`begin`
448
449			`case (Sel)`
450
451			`1'b0: O1 = I1;`
452			`1'b1: O1 = I2;`
453
454			`endcase`
455
456			`end`
457
458			`endmodule`
459			`//------------------------------------------------`
460
461			`module MUXFULLPARALELL_16bits_2SEL_X`
462			`(`
463			`input wire [1:0] Sel,`
464			`input wire [15:0]I1, I2, I3,`
465			`output reg [15:0] O1`
466			`);`
467
468
469
470			`always @( * )`
471
472			`begin`
473
474			`case (Sel)`
475
476			`2'b00: O1 = I1;`
477			`2'b01: O1 = I2;`
478			`2'b10: O1 = I3;`
479			`default: O1 = 16'b0;`
480
481			`endcase`
482
483			`end`
484
485			`endmodule`
486			`//------------------------------------------------`
487			`module MUXFULLPARALELL_16bits_2SEL`
488			`(`
489			`input wire Sel,`
490			`input wire [15:0]I1, I2,`
491			`output reg [15:0] O1`
492			`);`
493
494
495
496			`always @( * )`
497
498			`begin`
499
500			`case (Sel)`
501
502			`1'b0: O1 = I1;`
503			`1'b1: O1 = I2;`
504
505			`endcase`
506
507			`end`
508
509			`endmodule`
510
511
512			`//------------------------------------------------`
513	63	diegovalve	`/*`
514	36	diegovalve	`module MUXFULLPARALELL_1Bit_1SEL`
515			`(`
516			`input wire Sel,`
517			`input wire I1, I2,`
518			`output reg O1`
519			`);`
520
521
522
523			`always @( * )`
524
525			`begin`
526
527			`case (Sel)`
528
529			`1'b0: O1 = I1;`
530			`1'b1: O1 = I2;`
531
532			`endcase`
533
534			`end`
535
536			`endmodule`
537	63	diegovalve	`*/`
538	36	diegovalve	`//--------------------------------------------------------------`
539	63	diegovalve	`/*`
540	36	diegovalve	`module FFD_OPCODE_POSEDGE`
541			`(`
542			`input wire Clock,`
543			input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
544			output reg[`INSTRUCTION_OP_LENGTH-1:0] Q
545			`);`
546
547			`always @ (posedge Clock)`
548			`Q <= D;`
549
550			`endmodule`
551	63	diegovalve	`*/`
552	36	diegovalve	`//--------------------------------------------------------------`
553	63	diegovalve	`/*`
554	36	diegovalve	`module FFD16_POSEDGE`
555			`(`
556			`input wire Clock,`
557			`input wire[15:0] D,`
558			`output reg[15:0] Q`
559			`);`
560
561			`always @ (posedge Clock)`
562			`Q <= D;`
563
564			`endmodule`
565	63	diegovalve	`*/`
566	36	diegovalve	`//--------------------------------------------------------------`
567
568			`module FFT1`
569			`(`
570			`input wire D,`
571			`input wire Clock,`
572			`input wire Reset ,`
573			`output reg Q`
574			`);`
575
576			`always @ ( posedge Clock or posedge Reset )`
577			`begin`
578
579			`if (Reset)`
580			`begin`
581			`Q <= 1'b0;`
582			`end`
583			`else`
584			`begin`
585			`if (D)`
586			`Q <= ! Q;`
587			`end`
588
589			`end//always`
590
591			`endmodule`
592			`//--------------------------------------------------------------`